Ex Parte so et al

Board of Patent Appeals and Interferences

Jun 19, 2009

10745155 (B.P.A.I. Jun. 19, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte KIMMING SO and HON-CHONG HO
____________________

Appeal 2008-005228
Application 10/745,1551
Technology Center 2100
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Decided2: June 19, 2009
____________________

Before JOSEPH L. DIXON, JEAN R. HOMERE, and JAY P. LUCAS,
Administrative Patent Judges.

LUCAS, Administrative Patent Judge.

1 Application filed Dec. 23, 2003. Appellants claim the benefit under
35 U.S.C. § 119 of provisional application 60/487,439 filed on Jul. 15, 2003.
The present Application is a continuation in part of: 10/294,539 filed on
Nov. 14, 2002, now Patent 6,957,306 issued on Oct. 18, 2005; 10/294,091
filed on Nov. 14, 2002, now Patent 7,167,954 issued on Jan. 23, 2007; and
10/294,415 filed on Nov. 14, 2002, now Patent 6,931,494 issued on Aug. 16,
2005. The real party in interest is Broadcom Corporation.

2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail date (paper delivery) or Notification Date (electronic Delivery).
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DECISION ON APPEAL

STATEMENT OF THE CASE
Appellants appeal from a final rejection of claims 1 to 14, 16 to 19,
and 21 to 29 under authority of 35 U.S.C. § 134. The Board of Patent
Appeals and Interferences (BPAI) has jurisdiction under 35 U.S.C. § 6(b).
Claims 15 and 20 are cancelled.
Appellants’ invention relates to a method and system for indicating
through an invalidate designation that data in a cache has been changed and
is no longer reliable. In the words of the Appellants:
In an embedded multiprocessor based system, data from main
memory is often shared between a number of processors (e.g., CPUs).
In many instances, a processor's cache memory is updated based on
data stored in the main memory. Since some data is used more
frequently than others, one or more processor cache memories may
load such frequently used data from main memory. Such cache
memories, for example, may contain inconsistent data over time as
new data is updated in one processor's cache memory and not in
another processor's cache memory. This may cause processing
problems for one or more processors if the data is modified in one
processor's cache memory without appropriately updating the
modification to other memories (e.g., cache memories) located within
the other processors. As a consequence, one or more cache memories
may need to be updated as a result of a modification. If updates are
not made, invalid data may be used by the one or more processors
during subsequent execution of instructions. In many instances, a
software data coherency scheme is applied as opposed to a hardware
data coherency scheme, in order to update a stale or invalid cache line
from a processor's memory cache.

(Spec. ¶ [06]).

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Aspects of the present invention may be found in a system and
method to invalidate one or more blocks of a read-ahead cache
(RAC). The RAC is part of a shared memory based multiprocessor
system. In one embodiment, a method of maintaining data coherency
of a read-ahead cache comprises executing cache control instructions
generated by an execution unit of a control processor, generating a
cache line invalidate request, receiving a read-ahead cache controller
invalidate request by a read-ahead cache controller and transmitting a
read-ahead cache invalidate request to the read-ahead cache. In one
embodiment, the cache controller comprises a data cache controller or
an instruction cache controller. In one embodiment, cache invalidate
instructions are defined by a MIPS instruction set architecture. These
cache invalidate instructions are used to remove a cache line from a
cache memory. In one embodiment, the read-ahead cache controller
invalidate request comprises a memory address and cache identifier
for use in the read-ahead cache. In one example, the read-ahead cache
controller invalidate request comprises a specific action to be
performed on the read-ahead cache. For example, the action may
comprise invalidating a number of blocks or invalidating all blacks of
the read-ahead cache.

(Spec. ¶ [09]).

Claim 1 and claim 8 are exemplary:
1. A method of maintaining data coherency of a read-ahead
cache comprising:
executing, within a single integrated circuit chip, cache control
instructions generated by an execution unit of a control processor
located within said single integrated circuit chip; and
receiving, within said single integrated circuit chip, a read-
ahead cache invalidate request by said read-ahead cache, said read-
ahead cache being located within said single integrated circuit chip.

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8. A method of maintaining data coherency of a read-ahead
cache comprising:
executing cache control instructions generated by an execution
unit of a control processor;
generating a cache line invalidate request;
receiving a read-ahead cache controller invalidate request by a
read-ahead cache controller; and
transmitting a read-ahead cache invalidate request to said read-
ahead cache.

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Taylor US 5,699,551 Dec. 16, 1997
Nemirovsky US 2001/0052053 A1 Dec. 13, 2001
Arimilli US 2002/0112124 A1 Aug. 15, 2002

REJECTIONS
The Examiner rejects the claims as follows:
R1: Claims 1 to 14, 16, 18, 19, and 21 to 29 stand rejected under 35
U.S.C. § 103(a) for being obvious over Taylor in view of Arimilli.
R2: Claim 17 stands rejected under 35 U.S.C. § 103(a) for being
obvious over Taylor in view of Nemirovski.

Groups of Claims:
The claims will be discussed in the order of the arguments. See 37
C.F.R. § 41.37(c)(vii). See also In re McDaniel, 293 F.3d 1379, 1383 (Fed.
Cir. 2002) (“If the brief fails to meet either requirement [of 37 C.F.R. §
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1.192(c)(7)], the Board is free to select a single claim from each group of
claims subject to a common ground of rejection as representative of all
claims in that group and to decide the appeal of that rejection based solely
on the selected representative claim.”).
Appellants contend that the claimed subject matter is not rendered
obvious by Taylor alone, or in combination with Arimilli or Nemirovski, for
failure of the references to teach claimed limitations. The Examiner
contends that each of the claims is properly rejected.
Rather than repeat the arguments of Appellants or the Examiner, we
refer to the Briefs and the Answer for their respective details. Only those
arguments actually made by Appellants have been considered in this
opinion. Arguments which Appellants could have made but chose not to
make in the Briefs have not been considered and are deemed to be waived.

We affirm the rejections.

ISSUE
The issue is whether Appellants have shown that the Examiner erred
in rejecting the claims under 35 U.S.C. § 103(a). The issue turns on whether
the Taylor reference teaches the cache controllers, read-ahead caches, and
invalidation requests in the manner claimed.

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FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.
1. Appellants have invented a method and system for maintaining data
coherency and reliability in a cache supported processor. (Spec. ¶¶ [06]-
[07]). Appellants’ invention includes a multi-level cache system, with
instruction and data caches (#12 and #13) and a second level read-ahead
cache #14. When the data in a pre-fetch or read-ahead cache has been
changed by a data store from one processor (id. ¶ [18]), an invalidate
command is sent to the cache by a cache controller to indicate to other
processors that the data has changed cannot be relied upon (id. ¶ [23]).
2. Figure 2 of Appellants’ Specification is reproduced below:

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The Figure 2 above shows signals used in invalidating blocks of a Read-
Ahead Cache.
3. The Taylor reference teaches computer processor caching including
indicating data in a multilevel cache system as invalid when the data is
no longer reliable. (Col. 11, l. 58; col. 12, ll. 48-68). The reference
teaches primary and secondary level caching, (Fig. 1; col. 5, ll. 1-51),
used for read-ahead caching. (Col. 10, l. 50, et seq.).
4. Figure 1 of Taylor is reproduced below:

Taylor’s Figure 1 teaches the primary and secondary cache structure.
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PRINCIPLES OF LAW
Appellants have the burden on appeal to the Board to demonstrate
error in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86
(Fed. Cir. 2006) (“On appeal to the Board, an applicant can overcome a
rejection [under § 103] by showing insufficient evidence of prima facie
obviousness or by rebutting the prima facie case with evidence of secondary
indicia of nonobviousness.”) (quoting In re Rouffet, 149 F.3d 1350, 1355
(Fed. Cir. 1998)).
“In reviewing the [E]xaminer’s decision on appeal, the Board must
necessarily weigh all of the evidence and argument.” In re Oetiker, 977
F.2d 1443, 1445 (Fed. Cir. 1992).
The content of nonfunctional descriptive material is not entitled to
weight in the patentability analysis. See Ex parte Nehls, 88 USPQ2d 1883
(BPAI 2008) (precedential); Ex parte Curry, 84 USPQ2d 1272 (BPAI 2005)
(informative) aff’d, No. 06-1003 (Fed. Cir. 2006) (Rule 36); Manual of
Patent Examining Procedure (MPEP) § 2106.01 (Eighth ed., Rev. 7, Jul.
2008).
Our reviewing court has held in a number of decisions that a United
States patent speaks for all it discloses as of its filing date, even when used
in combination with other references. In re Zenitz, 333 F.2d 924, 926
(CCPA, 1964) (internal citations omitted).
All of the disclosures in a reference must be evaluated for what they
fairly teach one of ordinary skill in the art. The use of patents as references
is not limited to what the patentees describe as their own inventions or to the
problems with which they are concerned. They are part of the literature of
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the art, relevant for all they contain. In re Lemelson, 397 F2d 1006, 1009
(CCPA 1968) (citing In re Boe, 355 F.2d 961, 965 (CCPA 1966)).

ANALYSIS
From our review of the administrative record, we find that the
Examiner has presented a prima facie case for the rejections of Appellants’
claims under 35 U.S.C. § 103. The prima facie case is presented on pages 4
to 13 of the Examiner’s Answer. In opposition, Appellants present a number
of arguments.
Arguments with respect to the rejection
of claims 1 to 14, 16, 18, 19, and 21 to 29
under 35 U.S.C. § 103 [R1]

Appellants first contend that Examiner erred in rejecting claim 1 by
stating that “[n]owhere cited in the references (Taylor and/or Arimilli) is
there a read-ahead cache invalidate request received by a read-ahead
cache.” (App. Br. 11, middle). This first contention addresses the major
issue of the appeal, namely whether the Taylor reference to “Software
Invalidation in a Multiple Level, Multiple Cache System” can be read to
render the claims obvious over the prior art. The Taylor reference teaches
supporting the processing of the CPU 10 with two functional caches, a
primary cache (#50 for instructions and #52 for data) and a secondary cache
(#70, #71 and #18). (See Figure 1, reproduced above.) In the words of
Taylor: “The first or primary cache is fast, while the second or secondary
cache is large.” (Col. 4, ll. 54-55).
Claim 1 requires a read-ahead cache. Reading ahead wss a well-
known function for a cache at the time of Appellants’ invention, in which
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instructions or data for a processor are pre-read from the usually slower
main memory and kept in the fast local memory which is easily accessed by
the processor ahead of the time that the processor calls for the instruction or
data. Taylor teaches that the cache is used for reading ahead (sometimes
called pre-fetching or lookahead). (Col. 10, ll. 50-63). It is clear that the
primary cache is used for this function (col. 5, ll. 33-51) and it is suggested
by Taylor that both caches are used for this purpose, as both are loaded in
parallel. (Col. 8, l. 50). Thus, we have the teaching of a read-ahead cache in
Taylor.
As mentioned in the introduction above (Spec. ¶ [06]), sometimes in a
multiple processor situation (call them processor 1 and processor 2) or
otherwise, data in the cache is replaced by other data by processor 1, so the
original data is no longer present. If processor 2 still thinks that the original
data is present in the cache, it will be mistaken, and processor 2’s use will
lead to errors. That data has to be labeled as Invalid by an Invalidate
request, usually from a processor. As the Examiner points out, Taylor
teaches the use of the Invalidate command, and describes it as being sent to
both caches to indicate the data should not be used. (Answer 4, bottom;
Taylor, col. 12, ll. 48-68).
One further point concerning this claim is the issue of whether the
control processor and the read-ahead caches are all located within a single
integrated circuit chip, as claimed. (Brief 11, bottom). The Examiner has
pointed to Arimilli for this teaching, and we do not find error with that
reliance. (Answer 5, bottom). However, we have also noted in the primary
reference that Taylor teaches the Figure 1 embodiment all being on a single
chip, except for the floating point controller #12 and the multiply/divide
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execution unit #15. Those elements have been specifically mentioned as
being “off chip”, and it is a reasonable inference that the remaining items of
Figure 1 remain with the processor on the main chip.
With this background, we now reconsider Appellants’ contention that
“[n]owhere cited in the references (Taylor and/or Arimilli) is there a read-
ahead cache invalidate request received by a read-ahead cache.” (Brief 11,
middle). We find that Taylor does indeed teach a read-ahead cache, as
embodied in the primary and secondary caches shown in Figure 1. (FF#3).
We further find that these caches receive an invalidate request, as taught by
Taylor in column 12, lines 47 to 67. We therefore find no error with the
Examiner’s rejection on this point. Therefore, Appellants have not shown
error in the Examiner's initial showing of obviousness of independent
claim.1
With regard to claim 8, Appellants argue that the “Examiner has failed
to show a teaching or suggestion of ‘receiving a read ahead cache controller
invalidate request by a read-ahead cache controller; and transmitting a read-
ahead cache invalidate request to said read-ahead cache.’” (Brief 12,
middle). We have considered Appellants’ argument (Brief 12, bottom and
13) and the Examiner’s reading of the claim limitations. (Answer 16,
bottom). In Taylor, the processor originates the invalidate instruction (col.
13, l. 13), and that is passed on to a cache controller (col. 12, l. 62).
Appellants’ statement that “[n]owhere does Taylor teach a cache controller
transmitting signals to a cache” (Brief 13, middle) lacks credibility, as the
cache controller clearly controls the cache system. (Col. 8, l. 42). We thus
find no error with respect to the rejection of claim 8.
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With regard to claim 10, Appellants argue that Taylor does not teach
the two levels of cache controllers that are indicated by the limitations “read-
ahead cache controller” and “a cache controller.” (Brief 14, middle). We
considered the bare recitation of the cache controllers in the claims, and the
way the Examiner has read the detailed elements of the cache controlling
circuitry components described in the Taylor reference. (Answer 17, 18). We
can appreciate how the Examiner is reading the components, and note that
signals are transmitted and received by the various connected components
listed. We find no error in this rejection, over the bare limitations in the
claims.
Appellants argue that the Taylor reference does not teach the
invalidation request comprising data values corresponding to bits in a
control register of a read-ahead cache controller. For the reasons cited by
the Examiner (Answer 18, 19), we disagree with Appellants' contention.
Taylor’s controller clearly has the recited control bits in the cache op-codes
that control the Invalidate command. (Col. 8, l. 45 and col. 12, l. 47).
Appellants argue that Taylor does not teach the index invalidate
instructions of claim 16. (Brief 15, bottom). We endorse and adopt the
response of the Examiner, and find no error in the Examiner’s rejection.
(Answer 19, bottom). Similarly, with regard to Appellants’ arguments
concerning claim 18 involving “store tag” instructions, claim 21, and claim
22 (Brief 16, 17 and 19), we endorse and adopt the Examiner’s response,
and find no error in the Examiner’s rejection. (Answer 20, 21).
Appellants’ arguments concerning claims 22 (Brief 19, middle) are
noted. We have also reviewed the Examiner’s arguments. (Answer 22, top).
Appellants’ arguments are not sufficiently convincing to dispel the
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discussion in Taylor of registers containing the addresses to index into the
cache, and the instructions linked to tags stored in the PTAR array, forming
a sufficient teaching in the prior art for the rejection. (Taylor, col. 8, ll. 60-
68). Similarly, the Examiner points to a Taylor teaching that renders claim
23, concerning the invalidation of blocks in the read-ahead cache, obvious.
(Answer 23, middle).
Appellants’ arguments concerning claims 24 to 29 have been
considered. (Brief 21 to 25, top). However, in view of the Examiner’s
arguments (Answer 23, bottom to 27, bottom) concerning the Taylor
reference teachings, we decline to find error in the rejection.

Arguments with respect to the rejection
of claim 17
under 35 U.S.C. § 103 [R2]

Appellants have not argued this rejection separately in the Brief, or
the Reply Brief of record. The rejection is affirmed pro forma.

CONCLUSION OF LAW
Based on the findings of facts and analysis above, we conclude that
the Examiner did not err in rejecting claims 1 to 14, 16 to 19, and 21 to 29
under 35 U.S.C. § 103 [R1 and R2].

DECISION
The Examiner's rejections of claims 1 to 14, 16 to 19, and 21 to 29
under 35 U.S.C. § 103 [R1 and R2] are Affirmed.
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

msc

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