Waskiewicz, Peter P.

Patent Trials and Appeals Board

Oct 29, 2020

2019003555 (P.T.A.B. Oct. 29, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/977,605 06/28/2013 Peter P. Waskiewicz JR. P42828US 2233
96162 7590 10/29/2020
Law Office of R. Alan Burnett, PS
c/o CPA Global
900 Second Avenue South, Suite 600
Minneapolis, MN 55402
EXAMINER
MISIURA, BRIAN THOMAS
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
10/29/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
alan@patentlylegal.com
docketing@cpaglobal.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte PETER P. WASKIEWICZ JR.
____________________

Appeal 2019-003555
Application 13/977,605
Technology Center 2100
____________________

Before ALLEN R. MacDONALD, MICHAEL J. STRAUSS, and
PHILLIP A. BENNETT, Administrative Patent Judges.

MacDONALD, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from a Final
Rejection of claims 23–32 and 37–51. Appeal Br. 2. The Examiner objects
to claims 33–36, but they are otherwise indicated as allowable. Final Act. 1,
9. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE.

1 Appellant identifies the real party in interest is Intel Corporation.
Appeal Br. 3.
Appeal 2019-003555
Application 13/977,605

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CLAIMED SUBJECT MATTER
Claim 23 is illustrative of the claimed subject matter (emphasis,
formatting, and bracketed material added):
23. A method for configuring interrupts in a computer system
employing a multi-core microprocessor having a central
processing unit (CPU) with a plurality of processor cores
comprising:
[A.] mapping interrupt vectors to the plurality of processor cores
in the CPU, each interrupt vector being mapped to a
particular processor core;
[B.] detecting that an interrupt workload of a first processor core
has fallen below a threshold;
and in response thereto,
[C.] reconfiguring each of the interrupt vectors mapped to the
first processor core to be remapped to a processor core other
than the first processor core.
REFERENCES2
The Examiner relies on the following references:
Name Reference Date
Song US 2009/0172423 A1 June 2, 2009
Solomita US 7,581,052 B1 Aug. 25, 2009
van de Ven US 7,962,679 B2 June 14, 2011
Patale US 8,312,175 B2 Nov. 13, 2012
Saripalli US 8,762,994 B2 June 24, 2014

2 All citations herein to the references are by reference to the first named
inventor/author only.
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REJECTIONS
A.
The Examiner rejects claims 23, 24, 29–32, 38–40, 45, and 49–51
under 35 U.S.C. § 103(a) as being unpatentable over the combination of van
de Ven, Saripalli, and Song. Final Act. 2–7. We select claim 23 as the
representative claim for this rejection. Appellant’s Appeal Brief contentions
discussed herein as to claim 23 are determinative as to this rejection. 3
Therefore, except for our ultimate decision, we do not address claims
24, 29–32, 38–40, 45, and 49–51 further herein.
B.
The Examiner rejects claims 25–28, 41–43, and 46–48 under
35 U.S.C. § 103(a) as being unpatentable over the combination of van de
Ven, Saripalli, Song, and Solomita. Final Act. 7–8.
The Examiner rejects claims 37 and 44 under 35 U.S.C. § 103(a) as
being unpatentable over the combination of van de Ven, Saripalli, Song, and
Patale. Final Act. 8–9.
The contentions discussed herein as to claim 23 are determinative as
to these rejections. Therefore, except for our ultimate decision, we do not
address the merit of 35 U.S.C. § 103(a) rejections of claims 25–28, 37, 41–
44, and 46–48 further herein.

3 We cite herein to the Appeal Brief filed June 5, 2018.
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OPINION
We have reviewed the Examiner’s rejections in light of Appellant’s
arguments that the Examiner has erred. Appellant’s contentions we discuss
are determinative as to the rejections on appeal. Therefore, Appellant’s
other contentions are not discussed in detail herein.
A. First Argument
Appellant contends that the Examiner erred in rejecting claim 23
under 35 U.S.C. § 103(a) because:
First, there is absolutely no disclosure in van de Ven
concerning detecting an interrupt workload across a plurality of
processing cores (or processing elements or PEs ). The interrupt
workload is detected at the system level only (i.e., the
combination of the four processors). Also [a] processor is not a
processor core, and the system of four physical processing
devices, i.e. processors 205, 210, 215, and 220, do not constitute
a microprocessor.
Appeal Br. 17.
We are unpersuaded by Appellant’s argument. Contrary to
Appellant’s assertion that “the interrupt workload is detected at the system
level only (i.e., the combination of the four processors [205, 210, 215, and
220]),” van de Ven also discloses that interrupts can be distributed among
the four processors based on the category of interrupt, and the amount of
interrupt activity in a selected category can be determined, i.e., determined at
the individual processor level.
To illustrate, during a performance mode, interrupt
sources may be grouped into categories and/or classes, such as
legacy, storage, timer, Ethernet, and other. These categories are
distributed among processors 205, 210, 215, and 220 according
to fair distribution of interrupt activity amount, numa [non-
uniform memory access] affinity, and previous assignment. As
a result, assume, during a performance mode, the Ethernet
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interrupts are assigned to processor 205, the storage and
legacy interrupts are assigned to processor 210, the timer
interrupts are assigned to processor 215, and the other interrupts
are assigned to processor 220. Processor 205 further distributes
the ethernet/networking interrupts among its cache domains,
which here includes a first cache domain of PE 206 and 207
sharing one data cache and a second cache domain of PE 208 and
209 sharing a second data cache.
At this point, all interrupts may be serviced. However, in
another embodiment, when the amount of Ethernet interrupt
activity is over an Ethernet threshold, then selected Ethernet
interrupt are further assigned specifically to PEs 206-209,
accordingly. Note that each interrupt type, class, or category
may have its own defined activity threshold. Therefore, on
processor 210, legacy interrupts may have a lower threshold than
storage interrupts.
van de Ven, col. 7, lines 45–67 (emphasis added).
B. Second Argument
B.1.
As reproduced supra, steps B and C of claim 23 require:
[B.] detecting that an interrupt workload of a first processor core
has fallen below a threshold;
and in response thereto,
[C.] reconfiguring each of the interrupt vectors mapped to the
first processor core to be remapped to a processor core other
than the first processor core.

B.2.
In rejecting claim 23, the Examiner finds:
Per Claim 23, van de Ven discloses . . . if the detected
interrupt workload has fallen below a threshold, limiting
interrupt assignment to a single processor core so that other
processor cores may enter low power states (Col. 6 lines 49-55).
Final Act. 3 (emphasis added).
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B.3.
Appellant contends that the Examiner erred in rejecting claim 23
under 35 U.S.C. § 103(a) because:
The Examiner . . . states the van de Ven discloses, “if the
detected interrupt workload has fallen below a threshold, limiting
interrupt assignment to a single processor core so that other
processor cores may enter low power states.” van de Ven simply
does not disclose this. van de Ven does not disclose anything
relating to assigning any interrupts to a processor core, either in
Col. 5 line 27 - Col. 6 line 64 or elsewhere. The Examiner is
clearly wrong in this assertion.
Appeal Br. 17.
B.4.
As articulated by the Federal Circuit, the Examiner’s burden of
proving non-patentability is by a preponderance of the evidence. See In re
Caveney, 761 F.2d 671, 674 (Fed. Cir. 1985) (“preponderance of the
evidence is the standard that must be met by the PTO in making rejections”).
“A rejection based on section 103 clearly must rest on a factual basis[.]” In
re Warner, 379 F.2d 1011, 1017 (CCPA 1967). “The Patent Office has the
initial duty of supplying the factual basis for its rejection. It may not . . .
resort to speculation, unfounded assumptions or hindsight reconstruction to
supply deficiencies in its factual basis.” Id. We conclude the Examiner’s
analysis fails to meet this standard because the rejection does not adequately
explain the Examiner’s findings of fact.
We agree with Appellant that “van de Ven does not disclose anything
relating to assigning any interrupts to a processor core, either in Col. 5 line
27 - Col. 6 line 64 or elsewhere.” Appeal Br. 17 (emphasis added). Rather,
as discussed supra, we determine that van de Ven discloses detecting an
interrupt workload at (a) the system level (all four processors together), or
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(b) at the individual processor level. We further determine that the
Examiner has not provided sufficient articulation reasoning for extending
van de Ven’s disclosures of assigning and detecting an interrupt workload to
an even lower structural level of an individual processor core.4
We conclude, consistent with Appellant’s argument, that there is
currently insufficient articulated reasoning to support the Examiner’s finding
that van de Ven teaches, suggests, or otherwise renders obvious “detecting
that an interrupt workload of a first processor core has fallen below a
threshold” (emphasis added) required by claim 23.
Therefore, we conclude that there is insufficient articulated reasoning
to support the Examiner’s final conclusion that claim 23 would have been
obvious to one of ordinary skill in the art at the time of Appellant’s
invention.

CONCLUSION
Appellant has demonstrated the Examiner erred in rejecting claims
23–32 and 37–51 as being unpatentable under 35 U.S.C. § 103(a).
The Examiner’s rejections of claims 23–32 and 37–51 as being
unpatentable under 35 U.S.C. § 103(a) are reversed.

4 Although we determine that (a) van de Ven does not disclose assigning and
detecting an interrupt workload at an individual processor core level, and
(b) the Examiner has not otherwise provided sufficient articulated reasoning,
the Examiner is not precluded from using the currently cited references as
support for extending van de Ven’s disclosures to the processor core level to
thereby provide the needed articulated reasoning.

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Application 13/977,605

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DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
23, 24, 29–
32, 38–40,
45, 49–51
103(a) van de Ven, Saripalli,
Song
23, 24,
29–32,
38–40,
45, 49–51
25–28, 41–
43, 46–48
103(a) van de Ven, Saripalli,
Song, Solomita
25–28,
41–43,
46–48
37, 44 103(a) van de Ven, Saripalli,
Song, Patale
37, 44
Overall
Outcome

23–32,
37–51

REVERSED