VMware, Inc.

Patent Trials and Appeals Board

Aug 27, 2021

2020003765 (P.T.A.B. Aug. 27, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/174,376 06/06/2016 Adrian Marinescu C954 8171
152606 7590 08/27/2021
Olympic Patent Works PLLC
4979 Admiral Street
Gig Harbor, WA 98332
EXAMINER
LU, KEVIN X
ART UNIT PAPER NUMBER
2199
MAIL DATE DELIVERY MODE
08/27/2021 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ADRIAN MARINESCU

Appeal 2020-003765
Application 15/174,376
Technology Center 2100

Before, JOHN A. EVANS, JASON J. CHUNG, and JOYCE CRAIG,
Administrative Patent Judges.

CRAIG, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision rejecting claims 1–20, which constitute all the claims
pending in this application. See Non-Final Act. 1. We have jurisdiction
under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the term “Appellant” to refer to “applicant” as defined in 37 C.F.R.
§ 1.42 (2019). Appellant identifies the real party in interest as VMWARE,
INC. Appeal Br. 1.
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Application 15/174,376

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CLAIMED SUBJECT MATTER
The claims are directed to flow-control of shared computational
resources in multi-processor computer systems and multi-core-processor-
based systems. Spec. ¶ 1; Title. Claim 1, reproduced below, is illustrative of
the claimed subject matter:
1. A flow-control component of a multi-processing-entity
computer system, the flow-control component comprising:
a shared computational resource;
two or more local access pools, together comprising a
distributed access pool, each local access pool uniquely
associated with a processing entity; and
a process or thread that accesses the shared
computational resource when a local access pool associated
with the processing entity on which the process or thread
executes contains at least one shared-computational-resource
access and when the process or thread first removes a shared-
computational-resource access from the local access pool before
accessing the shared computational resource.
Appeal Br. 29 (Claims App.) (emphasis added to disputed limitation).
REFERENCES
The prior art relied upon by the Examiner is:
Name Reference Date
Simmons et al.
(“Simmons”)
US 6,574,654 B1 June 3, 2003
Nguyen US 2014/0108728 A1 Apr. 17, 2014
REJECTIONS
Claims 1–20 stand rejected under 35 U.S.C. § 112(b) as indefinite for
failing to particularly point out and distinctly claim the subject matter which
the inventor or a joint inventor regards as the invention. Non-Final Act. 3–5.
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Claims 1–7, 9–16, and 18–20 stand rejected under 35 U.S.C. § 103 as
unpatentable over Simmons. Non-Final Act. 6–11.
Claims 8 and 17 stand rejected under 35 U.S.C. § 103 as unpatentable
over Simmons and Nguyen. Non-Final Act. 11–12.
ANALYSIS
Indefiniteness Rejection of Claims 1–20
The Examiner rejected claims 1–20 for indefiniteness under 35 U.S.C.
§ 112(b) because:
a. it is unclear what is meant by “a process or thread that accesses
the shared. . . . when a local access pool associated with . . . and
when the process or thread first . . .” because it is unclear
whether the two “when” limitations are meant to be dependent
and work in conjunction with each other to achieve “a process
or thread that accesses the shared computational resource,” or
whether a process or thread that accesses the shared
computational resource occurs when either of the “when”
actions is performed.
b. it is unclear what is meant by “a process or thread that accesses
the shared computational resource. . . .when the process or
thread first removes a shared-computational-resource access
from the local access pool before accessing the shared
computational resource” because no part of the Specification
describes an instance where the same process that calls to
request access for the resource is dependent on that same thread
calls to removes a shared-computational-resource access, see
Fig. 15F and in contrast with Fig. 15G.
c. it is unclear whether “a process or thread that accesses the
shared computational resource when a local access pool
associated with the processing entity on which the process or
thread executes contains at least one shared-computational-
resource access” means “a process or thread that accesses the
shared computational resource” is predicated on the occurrence
(when) that local access pool already accessed it, or that “a
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Application 15/174,376

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process or thread that accesses the shared computational
resource,” the access itself, is represented as executed when the
local access pool contains at least one shared-computational-
resource access.
Non-Final Act. 3–4.
“[I]f a claim is amenable to two or more plausible claim constructions,
the USPTO is justified in requiring the applicant to more precisely define the
metes and bounds of the claimed invention by holding the claim . . .
indefinite.” Ex parte Miyazaki, 89 USPQ2d 1207, 1211 (BPAI 2008)
(precedential); accord Ex parte McAward, Appeal No. 2015-006416, 2017
WL 3669566, at *4 (PTAB 2017) (precedential).
Appellant has persuaded us that claim 1 is not amenable to two or
more plausible claim constructions. We agree with Appellant that, in claim
1, a process or thread can access the shared computational resource only
when the conditions specified by both of the two “when” clauses occur. See
Appeal Br. 15. We are also persuaded that the Specification describes that
the instruction on line 1558 of Appellant’s Figure 15F removes a shared-
computational-resource access pool, and the instruction on line 1560 of
Figure 15F determines whether there was at least one shared-computational-
resource access in the local access pool prior to removal of a shared-
computational-resource access from the local access pool carried out in the
preceding instruction, on line 1558. Id. at 16–17; see also Spec. ¶¶ 75, 82.
For these reasons, we are persuaded that the Examiner erred in
rejecting claims 1–20 for indefiniteness. Accordingly, we reverse the
Examiner’s § 112(b) rejection of claims 1–20.
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Obviousness Rejections of Claims 1–20
With regard to representative claim 1, Appellant has persuaded us that
the Examiner’s reliance on the teachings of Simmons is in error. In
particular, we are persuaded that paragraphs 18 and 19 of Simmons, relied
on by the Examiner, do not teach or suggest the last limitation recited in
claim 1, italicized above.
In particular, the Examiner found Simmons teaches that “when a
shadow lock exists, it means there is at least one shared computation-
resource access as shadow lock for specific modes are removed when no
thread on the node wants to access the shared resource in the particular
mode.” Non-Final Act. (citing Simmons cols. 18: 48–57, 19: 31–42).
Appellant argues that Simmons is directed to a lock-based contention
control system, which is distinguishable from the invention claimed in claim
1. Appeal Br. 22–23. Appellant argues that the Simmons Abstract “clearly
indicates that the shadow resource objects grant locks, while the current
application states that locks are not used when the ‘local access pools’”
contain a sufficient number of shared-computer-resource accesses. Id. at 24.
Appellant further argues that Figure 3 of Simmons, relied on by the
Examiner, is insufficient to support the Examiner’s finding that a shadow
resource object teaches or suggests a “local access pool,” as recited in claim
1.
Appellant has persuaded us that the Examiner erred. We agree with
Appellant that:
In paragraphs [0071-0074] [of the Specification], with reference
to Figures 14A-C, which illustrate a traditional approach to
flow control of a resource in a multi-processing-entity computer
system, the current application provides a detailed explanation
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of why locks, which are blocking mechanisms used to single-
thread access to a computational resource, result in significant
inefficiencies in a multi-core processor or other multi-
processing-entity environment. Then, in paragraphs [0075-
0085], with reference to Figures 15A-M, the current application
discusses the currently disclosed non-blocking approach that
avoids most of these inefficiencies by providing local access
pools to each of the processing entities, so that a processing
entity can retrieve access rights, or accesses, from the local
access pool assigned to the processing entity without using
locks or other synchronization mechanisms.
Reply Br. 22. Additionally, the Specification describes that if “a processor or
thread is not able to gain access to the computational resource, contention
control and exclusive locking by cache controllers may result from an
attempt to redistribute accesses among processing entities, “but this is
generally an infrequent occurrence.” Spec. ¶ 75.
The Examiner has not explained sufficiently why, in the cited
portions, Simmons’s use of locks for controlling access to a shared
computational resource teaches or suggests the disputed limitation in light of
the Specification’s description of the claimed flow-control component as
distinguishable from a lock-based contention control system.
Because we are persuaded that the Examiner erred in rejecting claim
1, and grouped claims 2–7, 9–16, and 18–20, we reverse the Examiner’s
obviousness rejection of those claims. We also reverse the Examiner’s
obviousness rejection of claims 8 and 17, as the Examiner does not find that
Nguyen teaches or suggests the disputed limitation not found in Simmons.
CONCLUSION
The Examiner’s decision rejecting claims 1–20 is reversed.
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DECISION SUMMARY
In summary:
Claim(s)
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1–20 112(b) Indefiniteness 1–20
1–7, 9–16,
18–20
103 Simmons 1–7, 9–16,
18–20
8, 17 103 Simmons, Nguyen 8, 17
Overall
Outcome
1–20

REVERSED