VMware, Inc.

Patent Trials and Appeals Board

Aug 17, 2021

2020002443 (P.T.A.B. Aug. 17, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/387,332 12/21/2016 Andrei Warkentin D288 6497
136237 7590 08/17/2021
Barta, Jones & Foley, P.C.
(Patent Group - VMware)
3308 Preston Road
#350-161
Plano, TX 75093
EXAMINER
CHAN, DANNY
ART UNIT PAPER NUMBER
2186
NOTIFICATION DATE DELIVERY MODE
08/17/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docket@bjfip.com
ipadmin@vmware.com
uspto@dockettrak.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte ANDREI WARKENTIN, CYRIEN LAPLACE,
ALEXANDER FAINKICHEN, YE LI, and REGIS DUCHESNE
____________

Appeal 2020-002443
Application 15/387,332
Technology Center 2100
____________

Before CARL W. WHITEHEAD JR., JAMES B. ARPIN, and
PHILLIP A. BENNETT, Administrative Patent Judges.

ARPIN, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a), the Examiner’s final
rejection of claims 1–20, all of the pending claims. Final Act. 2.2 We have
jurisdiction under 35 U.S.C. § 6(b).
We reverse.

1 Appellant refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant
identifies the real party-in-interest as VMware, Inc. Appeal Br. 1.
2 In this Decision, we refer to Appellant’s Appeal Brief (“Appeal Br.,” filed
October 23, 2019); the Final Office Action (“Final Act.,” mailed April 17,
2019), the Advisory Action (“Adv. Act.,” mailed July 25, 2019), and the
Examiner’s Answer (“Ans.,” mailed November 25, 2019); and the
Specification (“Spec.,” filed December 21, 2016). Rather than repeat the
Examiner’s findings and Appellant’s contentions in their entirety, we refer to
these documents.
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Application 15/387,332
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STATEMENT OF THE CASE
Appellant’s claimed methods, systems, and media relate to
“provid[ing] for constructing bootloader address space corresponding to an
expected base virtual address (VA).” Spec. ¶ 4. The Specification discloses,
“Many computer system platforms do not provide guaranteed memory
locations, do not have low memory addresses, and/or may have memory at
extremely high addresses. . . . However, these bootloaders need to know
where the move goes and rely on platform knowledge which may be
unavailable.” Id. ¶ 2.
As noted above, claims 1–20 are pending. Claims 1, 8, and 15 are
independent. Appeal Br. A-1 (claim 1), A-2–A-3 (claim 8), A-4 (claim 15)
(Claims App.). Claims 2–7 depend directly from claim 1, claims 9–14
depend directly from claim 8, and claims 16–20 depend directly from
claim 15. Id. at A-1–A-5.
Claim 1, reproduced below with disputed limitations emphasized, is
representative.
1. A computer-implemented method for constructing
bootloader address space, the method comprising:
initiating, by a bootloader, a loading of an operating
system (OS); and
prior to the OS being loaded, the bootloader performing
the following operations:
determining a machine address (MA) at which the
bootloader has been loaded into memory;
determining a difference between an expected virtual
address (VA) and a loaded MA;
defining, based on the determined difference, a page table
that maps the bootloader loaded at the determined MA to the
expected VA;
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setting an exception handling vector to point to the
expected VA associated with the bootloader;
enabling a memory management unit (MMU) which uses
the defined page table for address translation; and
in response to a page fault exception resulting from
enabling the MMU, executing the bootloader at the expected VA
via the exception handling vector.
Id. at A-1 (emphases added). Each of claims 8 and 15 recite limitations
corresponding to the disputed limitations of claim 1. Id. at A-2–A-4; see
Final Act. 7 (rejecting claim 8), 8–10 (rejecting claim 15).
REFERENCES AND REJECTION
The Examiner relies upon the following references:
Name3 Reference Published Filed
Lee US 2016/0132369 A1 May 12, 2016 Nov. 6, 2015
Warkentin US 2016/0170679 A1 June 16, 2016 Dec. 16, 2014
The Examiner rejects claims 1–20 as obvious under 35 U.S.C. § 103
over the combined teachings of Warkentin and Lee. Final Act. 2–10.
We review the appealed rejections for error based upon the issues
identified by Appellant, and in light of the contentions and evidence
produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010)
(precedential). Appellant and the Examiner focus their contentions and
findings, respectively, on claim 1, so do we. See Appeal Br. 15; Ans. 12–13.
Because we determine that reversal of the rejection of independent claim 1,
as well as of independent claims 8 and 15, is dispositive, except for our

3 All reference citations are to the first named inventor only.
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ultimate decision, we do not discuss the merits of the rejections of claims 2–
7, 9–14, and 16–20 further herein. We address the rejection below.
ANALYSIS
1. Non-Obviousness of Claim 1 Over Warkentin and Lee
As noted above, the Examiner rejects independent claim 1 as obvious
over the combined teachings of Warkentin and Lee. Final Act. 3–5. In
particular, the Examiner finds that Warkentin teaches or suggests a majority
of the limitations recited in claim 1. Id. at 3–4.
Nevertheless, the Examiner finds:
Warkentin do not explicitly teach initiating, by a
bootloader, a loading of an operating system (OS); and prior to
the OS being loaded, the bootloader performing the following
operations. Although Warkentin teaches performing said
“following operations”, Warkentin does not explicitly state the
operations occur before an OS is loaded. Warkentin uses a
bootstrap [central processing unit (CPU)] and the OS on the
bootstrap CPU to bring-up/initialize a secondary CPU, but is
silent on whether it results in loading of an OS on the secondary
CPU.
Final Act. 4 (emphasis added). The Examiner finds, however:
In summary, Lee describes the booting of a multi-processor
device in a sequential manner, where one processor and its
operating system are booted first, and then it causes the booting
of a second processor and its operating system. This is similar
to Warkentin where a bootstrap CPU and its operating system are
booted first, and then it causes the booting of a secondary
processor.
Id. at 5 (emphasis added; citing Lee ¶¶ 139–140).
The Examiner finds a person of ordinary skill in the relevant art would
have had reason to combine the teachings of Warkentin and Lee to achieve
the methods of claim 1. Id. at 5. In particular, the Examiner finds:
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The combination of Warkentin with Lee yields performing the
operations prior to the second OS being loaded on the second
processor. One of ordinary skill in the art would be motivated to
have a second operating system in the secondary processor of
Warkentin to perform different types of programmable functions
[Lee [¶¶ 78–79], which would provide the user with better
performance of the multiprocessor device (due to specialization)
and the ability to handle more operations of different types.
Id. (emphasis added); see Ans. 11–12.
Appellant contends the Examiner errs for two reasons: (a) “due to
fundamental differences between the claimed invention and at least one of
the cited references,” and/or (b) “the rejection is impermissibly based on a
hindsight reconstruction of the claimed invention based on the Appellant’s
own application.” Appeal Br. 11. For the reasons given below, we agree
with Appellant.
a. Claim Interpretation
“Both anticipation under § 102 and obviousness under § 103 are two-
step inquiries. The first step in both analyses is a proper construction of the
claims. . . . The second step in the analyses requires a comparison of the
properly construed claim to the prior art.” Medichem, S.A. v. Rolabo, S.L.,
353 F.3d 928, 933 (Fed. Cir. 2003) (internal citations omitted); see In re
Geerdes, 491 F.2d 1260, 1262 (CCPA 1974) (“Before considering the
rejections . . ., we must first [determine the scope of] the claims . . . .”).
During examination of a patent application, pending claims are given their
broadest reasonable interpretation consistent with the specification. In re
Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004); In re
Prater, 415 F.2d 1393, 1404-05 (CCPA 1969).
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The Examiner determines here,
the purpose of the bootloader as described in Appellant’s
Specification is to initialize the OS of a VCI or VM. Virtualized
environments are created by executing software in hardware
following power-on initialization procedures in which a main OS
of a computing device is loaded. Therefore, the OS referred to
in the instant claims is a second OS that is used on a [virtual
machine (VM)] or [virtual computing instance (VCI)] rather than
a main OS used to initialize the computing device. Under the
broadest reasonable interpretation of the claims in light of
the specification, the claimed OS may be a second OS that is
loaded after loading a first/main OS and after performing the
“specific bootloader operations”.
Ans. 5 (bolding added; citing Spec. ¶¶ 13, 19); see Adv. Act. 2 (“The
operations performed in Warkentin are after loading of the first CPU and the
first OS to prepare for loading of the secondary CPU. Warkentin in view of
Lee thus teaches performing the claimed operations to prepare for loading
the secondary CPU and its secondary OS prior to the secondary OS being
loaded.”).
Claim interpretation is a question of law, which we review de novo.
For the reasons given below, we disagree with the Examiner’s interpretation
of the disputed limitations.
Here, claim 1 recites, “initiating, by a bootloader, a loading of an
operating system (OS); and prior to the OS being loaded, the bootloader
performing the following operations.” Appeal Br. A-1 (Claims App.).
“[A]n operating system (OS)” refers to one or more operating systems.
Baldwin Graphic Systems, Inc. v. Siebert, Inc., 512 F.3d 1338, 1342-43
(Fed. Cir. 2008) (“That ‘a’ or ‘an’ can mean ‘one or more’ is best described
as a rule, rather than merely as a presumption or even a convention.”;
citations omitted); see also Harari v. Lee, 656 F.3d 1331, 1341 (Fed. Cir.
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2011). Moreover, as the Specification makes clear, “[w]hen introducing
elements of aspects of the disclosure or the examples thereof, the articles ‘a,’
‘an,’ ‘the,’ and ‘said’ are intended to mean that there are one or more of the
elements.” Spec. ¶ 122; see id. ¶¶ 45 (“The processor(s) 122 include any
quantity of processing units programmed to execute computer executable
program code for implementing aspects of the examples.”), 46 (“The
computer executable program code, such as bootloader code, may be
performed by the processor(s) 122, by multiple processors within the
computing device 100, or performed by a processor external to the
computing device 100.”). Thus, in the disputed limitations, recitation of “the
OS” draws its antecedent basis from “an operating system (OS),” however
many OSs there are. Therefore, contrary to the Examiner, we interpret
claim 1 as reciting performing the bootloader operations on any processor
“prior to the OS being loaded.” See Appeal Br. 11–12 (describing the
recited “following operations” as “bootloader operations”).
Consequently, the Examiner bases the obviousness rejection of
claim 1 on an incorrect interpretation of the disputed limitations. Because of
this incorrect interpretation, the Examiner fails to address fundamental
differences between the claimed methods and the applied references.
b. No Reason to Combine
Among other things, Appellant also contends the Examiner fails to
provide an adequate reason, supported by evidence, for a person of ordinary
skill in the relevant art to have combined the teachings of Warkentin and Lee
to achieve the methods of claim 1. Appeal Br. 13–15. In particular,
Appellant contends the Examiner relies on an impermissible hindsight
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reconstruction of the claimed methods based on Appellant’s teachings. Id. at
14–15. For the reasons given below, we agree with Appellant.
Warkentin discloses preparing a secondary CPU’s MMU to load an
OS. In particular, Warkentin discloses:
As part of “bringing up” a multiple central processing unit
(CPU) system, an operating system (OS) that is executing on a
bootstrap CPU (the CPU on which an OS kernel is initialized first
on) brings up one or more secondary CPUs (here bring-up refers
to the OS procedure for initializing the secondary CPUs).
Warkentin ¶ 1 (emphasis added). Further, Warkentin discloses:
Bootstrap CPU 130 and secondary CPUs 140 are general-
purpose processing units that can perform most tasks. For
instance, an operating system 112 (stored in memory 110) may
execute instructions on bootstrap CPU 130 and secondary
CPUs 140 in any combination. However only bootstrap
CPU 130 orchestrates initialization procedures (typically at
start-up or reset) for computer system 100 – including secondary
CPUs 140. Notably, such initialization procedures include
transitioning each secondary CPU 140 from an initial state that
is defined by the architecture or firmware to a desired operational
state.
Id. ¶ 14 (emphasis added). Thus, Warkentin discloses that an OS already is
initiated and loaded on bootstrap CPU 130, and bootstrap CPU 130 then
may “bring-up “any number of secondary CPUs 140.
Lee discloses:
An electronic device includes a first processor; and a second
processor; and a third processor. The second processor is
configured to detect an event, select one of the first and third
processors to perform one or more operations associated with
the event, and cause the selected processor to perform the one or
more operations.
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Lee, Abstr. (emphasis added); see id. ¶¶ 71, 73, 78 (describing
middleware 330). Thus, Lee discloses one processor selecting from among
other processors, another processor to perform a particular operation.
Specifically, Lee discloses that a first processor with a loaded
operating system may supply a boot binary code to a second processor, so
that the second processer may load an operating system. Lee ¶ 139 (“[I]f the
booting of the first operating system is completed, the first processing
core 721 may load a boot binary code of the second operating system on the
second memory 733 (e.g., an SRAM) through the first memory 723.”); see
id. ¶ 140. According to the Examiner, this has the advantage of improving
performance of the multiprocessor device by increasing specialization and
the ability to handle more operations of different types. Final Act. 5 (citing
Lee ¶¶ 78–79).
The Examiner finds:
The combination of Warkentin and Lee yields booting of a
first CPU and its own OS, which then performs the claimed
“bootloader operations”4 in order to boot a second CPU having
the second OS. (This is similar to what is required for booting
an OS in a VCI or VM - hardware and its main OS will be booted
upon powering on a computing device, and the computing
device’s main OS runs initialization software to boot a VM that
has a virtual processor and virtual OS/second OS).
Ans. 8. Thus, as noted above, the Examiner finds that the language of
claim 1 does not prohibit a first CPU with an operating system already
loaded thereon from performing the “bootloader operations” on a second

4 “The initialization operations of Warkentin are ‘the specific bootloader
operations’ of instant claim 1. Warkentin, in summary, utilizes a bootstrap
CPU and an OS in the bootstrap CPU to perform operations for bringing up
a secondary CPU.” Ans. 5–6; see Appeal Br. 11–12.
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CPU prior to loading an operating system on the second CPU. See Adv.
Act. 2 (“Examiner provided Lee as the second reference to show the concept
of a first processing unit having its own operating system to boot a second
processing unit also having its own operating system, where the operating
systems perform different functions.”); but see supra Section 1.a. (rejecting
this interpretation of claim 1).
The U.S. Supreme Court explained, “[u]nder the correct analysis, any
need or problem known in the field of endeavor at the time of invention and
addressed by the patent can provide a reason for combining the elements in
the manner claimed.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 420
(2007) (emphasis added). Here, the Examiner fails to show how the
identified problem, namely, “better performance of the multiprocessor
device (due to specialization) and the ability to handle more operations of
different types,” is addressed by the instant application. See Final Act. 5
(emphases added); Ans. 8. As our reviewing court explained, “[a]t its core,
our anti-hindsight jurisprudence is a test that rests on the unremarkable
premise that legal determinations of obviousness, as with such
determinations generally, should be based on evidence rather than on mere
speculation or conjecture.” Alza Corp. v. Mylan Labs., Inc., 464 F.3d 1286,
1290 (Fed. Cir. 2006) (emphasis added).
Moreover, the claimed methods are intended, “in response to a page
fault exception resulting from enabling the MMU, to execut[e] the
bootloader at the expected VA via the exception handling vector.” Appeal
Br. A-1 (Claims App.). The Examiner finds, “Lee’s teachings allow
Warkentin’s secondary CPU to have its own OS. Thus the bootloader
operations in Warkentin are performed prior to loading the second OS in Lee
in the combination of Warkentin and Lee.” Ans. 10. The Examiner,
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however, fails to show why a person of ordinary skill in the relevant art
would have had reason first to load an operating system on a CPU without
the benefit of “a page table that maps the bootloader loaded at the
determined MA to the expected VA,” so that it then can load an operating
system on a different CPU with the benefit of such a mapping. See Spec.
¶¶ 15 (“The resulting page fault resumes execution of a second portion of
the bootloader in virtual memory through a redirect via an exception
handling vector. This reduces boot failures and improves portability of the
bootloader across varying architectures and platforms.”); 16 (“This property
ensures that once the MMU is enabled or reinitialized and the translation
lookaside buffer (TLB) is flushed, the bootloader continues execution as if
nothing happened where the expected VA happens to coincide with the
current MA or execution continues at the next expected instruction within
the current VA via a page fault exception.”).
The Examiner finds, “Regarding applicant’s arguments that Examiner
used impermissible hindsight reasoning, Examiner disagrees because
applicant’s disclosure does not even suggest a second CPU with a second
OS relied on by the Examiner in addressing the claims, and thus there is no
hindsight reasoning.” Adv. Act. 2. This finding is not accurate. As noted
above, the Specification discloses multiple processors (see Spec. ¶¶ 41–46),
and claim 1 broadly recites OSs for loading on multiple processors (see
supra Section 1.a. (interpretation of claim 1)). Thus, the Examiner’s
improper reconstruction of Appellant’s claimed methods is based, in part, on
a misreading of the Specification and an inaccurate interpretation of claim 1.
On this record, we are persuaded the Examiner relies impermissibly
on hindsight gleaned from Appellant’s disclosure to assemble the teachings
of the references in an attempt to achieve the claimed methods. Absent
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Appellant’s disclosure, we are not persuaded the Examiner adequately
shows a person of ordinary skill in the relevant art would have had reason to
combine the references in the manner proposed. See Appeal Br. 14–15.
Because these deficiencies in the Examiner’s rejection of claim 1 are
dispositive, we do not reach Appellant’s other challenges to the rejection of
claim 1. Consequently, we are persuaded that the Examiner errs in rejecting
claim 1, and we do not sustain the obviousness rejection of claim 1.
2. The Remaining Claims
As noted above, Appellant challenges the rejection of independent
claims 8 and 15 for substantially the same reasons as claim 1. Appeal
Br. 16; see Final Act. 7 (rejecting claim 8), 8–10 (rejecting claim 15). Thus,
we also are persuaded that the Examiner errs in rejecting claims 8 and 15 for
substantially the same reasons set forth above with respect to claim 1.
Therefore, we do not sustain the obviousness rejection of claims 8 and 15.
Each of claims 2–7, 9–14, and 16–20 depends directly or indirectly
from independent claim 1, 8, or 15. Appeal Br. A-1–A-5 (Claims App.).
Because we are persuaded the Examiner errs with respect to the obviousness
rejection of claim 1, as well as of claims 8 and 15, we also are persuaded the
Examiner errs with respect to the obviousness rejections of claims 2–7, 9–
14, and 16–20. For this reason, we do not sustain the rejections of claims 2–
7, 9–14, and 16–20.
DECISION
1. The Examiner errs in rejecting claims 1–20 under 35 U.S.C. § 103 as
obvious over the combined teachings of Warkentin and Lee.
2. Thus, on this record, claims 1–20 are not unpatentable.
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CONCLUSION
For the above reasons, we reverse the Examiner’s decision rejecting
claims 1–20.
In summary:
Claims
Rejected
35 U.S.C.
§
References/Basis Affirmed Reversed
1–20 103 Warkentin, Lee

1–20

REVERSED