VLSI Technology LLC

Patent Trials and Appeals Board

Jan 12, 2021

IPR2019-01195 (P.T.A.B. Jan. 12, 2021)

Trials@uspto.gov Paper 29
571-272-7822 Date: January 12, 2021

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

INTEL CORPORATION,
Petitioner,

v.

VLSI TECHNOLOGY LLC,
Patent Owner.
____________

IPR2019-01195
Patent 8,081,026 B1
____________

Before BART A. GERSTENBLITH, MINN CHUNG, and
KIMBERLY McGRAW, Administrative Patent Judges.

CHUNG, Administrative Patent Judge.

JUDGMENT
Final Written Decision
Determining Some Challenged Claims Unpatentable
35 U.S.C. § 318(a)

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I. INTRODUCTION
In this inter partes review, instituted pursuant to 35 U.S.C. § 314,
Intel Corporation (“Petitioner”) challenges the patentability of claims 13, 14,
17, 18, and 20 (the “challenged claims”) of U.S. Patent No. 8,081,026 B1
(Ex. 1101, “the ’026 patent”), owned by VLSI Technology LLC (“Patent
Owner”). This Final Written Decision is entered pursuant to 35 U.S.C.
§ 318(a) and 37 C.F.R. § 42.73. For the reasons discussed below, we
determine Petitioner has shown by a preponderance of the evidence that
claims 13 and 14 of the ’026 patent are unpatentable, but has not proven by a
preponderance of the evidence that claims 17, 18, and 20 of the ’026 patent
are unpatentable.
II. BACKGROUND
A. Procedural History
On June 28, 2019, Petitioner filed a Petition (Paper 3, “Pet.”)
requesting inter partes review of the challenged claims of the ’026 patent.
Patent Owner filed a Preliminary Response (Paper 7, “Prelim. Resp.”).
Petitioner then filed an authorized reply to address Patent Owner’s
arguments in the Preliminary Response regarding discretion under 35 U.S.C.
§ 314(a) (Paper 9), to which Patent Owner filed an authorized sur-reply
(Paper 10).
On January 13, 2020, applying the standard set forth in 35 U.S.C.
§ 314(a), which requires demonstration of a reasonable likelihood that
Petitioner would prevail with respect to at least one challenged claim, we
instituted an inter partes review of all challenged claims of the ’026 patent
based on the ground presented in the Petition. Paper 11 (“Inst. Dec.”), 59.
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After institution, Patent Owner filed a Patent Owner Response
(Paper 15, “PO Resp.”), Petitioner filed a Reply to Patent Owner Response
(Paper 17, “Pet. Reply”), and Patent Owner filed a Sur-reply (Paper 24, “PO
Sur-reply”). An oral hearing was held on October 6, 2020, and a copy of the
hearing transcript has been entered into the record. Paper 28 (“Tr.”).
B. Related Matters
According to the parties, the ’026 patent is the subject of the
following district court litigation: VLSI Technology LLC v. Intel Corp.,
No. 18-966-CFC (D. Del.). Pet. 2; Paper 6, 2. Petitioner also filed a petition
for inter partes review in IPR2019-01194, challenging claims 1, 2, 4, 5, and
7 of the ’026 patent. Pet. 2. We instituted trial in IPR2019-01194 on
January 13, 2020. IPR2019-01194, Paper 11.
C. The ’026 Patent
The ’026 patent describes supplying an output supply voltage to a
power gated circuit included in an integrated circuit. Ex. 1101, 1:7–9. As
background, the ’026 patent describes that seemingly identical integrated
circuits fabricated using the same design may actually differ from each other
due to variations in the semiconductor manufacturing process. Id. at 1:13–
22. For example, ideally identical integrated circuits may differ in their
operating speed, some being faster than others. Id. at 1:20–22. In view of
the variations in the manufacturing process, the fastest circuits are
considered “best process case” integrated circuits, whereas the slowest
circuits are deemed “worst process case” integrated circuits. Id. at 1:23–30.
According to the ’026 patent, faster circuits generally have higher leakage
current (id. at 1:20–23), which means that the fastest integrated circuits have
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the highest leakage current and the slowest integrated circuits have the
lowest leakage current (id. at 1:27–30). The ’026 patent describes that, as a
result of this direct correspondence between the speed of the circuits and the
amount of leakage current, the competing or conflicting requirements of
high speed and low current consumption for integrated circuits can reduce
the yield of the manufacturing process because some circuits may satisfy the
speed requirements but have too high current consumption, whereas other
circuits may comply with the current consumption requirements but are too
slow to meet the speed requirements. Id. at 1:34–40.
According to the ’026 patent, applying a lower supply voltage to an
integrated circuit reduces both the speed and the current leakage of the
circuit, which may allow a very fast integrated circuit that was rejected for
being too leaky to have acceptable performance ranges for both speed and
current consumption, thereby increasing the yield of the semiconductor
manufacturing process. Ex. 1101, 3:4–11.
Figure 1 of the ’026 patent is reproduced below.

Figure 1 schematically shows a block diagram of an exemplary integrated
circuit. Id. at 1:62–63.
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As shown in Figure 1, integrated circuit 10 includes power gated
circuit 30, power gating switch 20, and control circuit 50 for controlling
power gating switch 20 by selecting control signal 103 that determines the
conductivity of the power gating switch. Id. at 2:40–44. According to the
’026 patent, this conductivity determines the difference between input
supply voltage 101 provided to power gating switch 20 and output supply
voltage 102 that is provided to power gated circuit 30 from power gating
switch 20. Id. at 2:44–54.
As shown in Figure 1, integrated circuit 10 also includes mode
indicator generator 40 and leakage indicator generator 45. Ex. 1101, 3:35–
37. The ’026 patent describes that mode indicator generator 40 generates
mode indicator 104 that indicates a desired mode of power gated circuit 30
(id. at 3:39–41) and leakage indicator generator 45 generates leakage
indicator 105 that indicates a leakage level of power gated circuit 30 (id. at
3:46–48). As depicted in Figure 1, control circuit 50 receives mode
indicator 104 and leakage indicator 105. Id. at 4:4–7. According to the
’026 patent, control circuit 50 can select the value of control signal 103
based on mode indicator 104 and on leakage indicator 105. Id. at 4:7–9.
The ’026 patent describes that leakage indicator generator 45 can
comprise a memory in which a leakage level value is stored during the
manufacturing process of integrated circuit 10 or during a leakage test
conducted after the production of integrated circuit 10. Id. at 3:48–52.
According to the ’026 patent, leakage indicator generator 45 can include
“fuses, one time programmable element or other programmable elements
that can be programmed to reflect the determined leakage.” Id. at 3:61–64.
The ’026 patent describes that leakage indicator 105 can indicate whether
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integrated circuit 10 has a leakage level that corresponds to a best process
case, typical process case, or worst process case. Id. at 3:64–67.
As described in the ’026 patent, power gated circuit 30 can operate in
at least the following modes: (i) a performance oriented mode (also referred
to as high throughput mode or high performance mode), (ii) a retention
mode, and (iii) a power gated mode. Ex. 1101, 2:57–60. The ’026 patent
describes that, during the retention mode, power gated circuit 30 can store
data in retention circuits and consume less power in comparison to the
performance oriented mode, whereas, during the power gated mode, power
gated circuit 30 is shut down and data is not retained. Id. at 2:63–67. The
’026 patent notes that additional modes can exist in which a different
trade-off between speed and leakage can be provided. Id. at 2:60–62.
The ’026 patent describes that control circuit 50 can select a
performance value for control signal 103 when (i) leakage indicator 105
indicates that a leakage of power gated circuit 30 is below a low leakage
threshold and (ii) mode indicator 104 indicates that power gated circuit 30 is
requested to operate at a performance oriented mode. Ex. 1101, 4:30–37.
Control circuit 50 can also be arranged to select a leakage reduction value of
control signal 103 suitable to reduce leakage while allowing power gated
circuit 30 to operate in performance mode when (i) leakage indicator 105
indicates that the leakage of power gated circuit 30 is above the low leakage
threshold and (ii) mode indicator 104 indicates that power gated circuit 30 is
requested to operate at the performance oriented mode. Id. at 4:38–45. The
performance value of the control signal causes a higher conductivity of
power gating switch 20, with a smaller difference between the values of
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input supply voltage 101 and output supply voltage 102 than the leakage
reduction value of the control signal. Id. at 5:10–14.
According to the ’026 patent, the low leakage threshold assists in
differentiating between integrated circuits of different types in that faster
integrated circuits will receive lower output supply voltage levels. Id.
at 4:46–48. The value of the low leakage threshold can be based on a
desired speed of the integrated circuit and on leakage limitations. Id. at
4:49–51.
The ’026 patent describes that control circuit 50 can be arranged to
select a retention value of the control signal 103 when mode indicator 104
indicates that power gated circuit 30 is requested to enter a retention mode
and select a shut-down value of control signal 103 when mode indicator 104
indicates that power gated circuit 30 should be shut down. Id. at 5:3–9.
D. Illustrative Claims
Of the challenged claims, only claim 13 is independent. Claims 13
and 14 are illustrative of the challenged claims and are reproduced below,
with bracketing used by the parties.
13. [A] A method for supplying an output supply voltage to a
power gated circuit, the method comprising:
[B] providing to an input port of a power gating switch an input
supply voltage;
[C] receiving, by a control circuit, a mode indicator that indicates
of a desired mode of the power gated circuit;
[D] receiving, by the control circuit, a leakage indicator that
indicates of a leakage level of the power gated circuit;
[E] selecting, by the control circuit, a value of a control signal
based on the mode indicator and on the leakage indicator;
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[F] supplying the control signal to a control port of the power
gating switch;
[G] providing, from an output port of the power gating switch,
the output supply voltage to the power gated circuit;
[H] wherein a relationship between a value of the input supply
voltage and a value of the output supply voltage is responsive
to the value of the control signal.
Ex. 1101, 16:40–57.
14. The method according to claim 13, comprising:
selecting a performance value of the control signal when (i) the
leakage indicator indicates that a leakage of the power gated
circuit is below a low leakage threshold and (ii) the mode
indicator indicates that the power gated circuit is requested to
operate at a performance oriented mode;
selecting a leakage reduction value of the control signal when
(i) the leakage indicator indicates that the leakage of the
power gated circuit is above the low leakage threshold and
(ii) the mode indicator indicates that the power gated circuit
is requested to operate at the performance oriented mode; and
selecting a shut down value of the control signal when the mode
indicator indicates that the power gated circuit should be shut
down.
Id. at 16:58–17:6.
E. Applied References and Asserted Grounds of Unpatentability
Petitioner cites the following references in its challenge to
patentability.
Reference and Date Designation Exhibit No.
U.S. Patent Application Publication No.
2008/0136507 A1 (published June 12, 2008) Kim 1104
U.S. Patent Application Publication No.
2007/0147159 A1 (published June 28, 2007) Lee 1105
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Petitioner asserts the following grounds of unpatentability (Pet. 6, 26–
79).
Claims Challenged 35 U.S.C. § Reference(s)/Basis
13, 14 1021 Kim
17, 18, 20 103(a) Kim, Lee

F. Testimonial Evidence
Petitioner relies on two Declarations from David Harris, Ph.D. in
support of its Petition and Reply. Ex. 1102 (“Harris Declaration”); Ex. 1130
(“Harris Reply Declaration”). Patent Owner cross-examined Dr. Harris via
deposition. Ex. 2010 (“Harris Dep.”).
In support of its Patent Owner Response, Patent Owner relies on the
Declaration of Professor Murali Annavaram. Ex. 2009 (“Annavaram
Declaration”). Petitioner cross-examined Dr. Annavaram by deposition.
Ex. 1131 (“Annavaram Dep.”).
III. ANALYSIS
A. Level of Ordinary Skill in the Art
We begin our analysis by addressing the level of ordinary skill in the
art. Citing the testimony of its declarant, Dr. Harris, Petitioner asserts that a
person of ordinary skill in the art at the time of the invention of the

1 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
(2011) (“AIA”), amended 35 U.S.C. §§ 102 and 103. Because the
’026 patent has an effective filing date prior to the effective date of the
applicable AIA amendments, we refer to the pre-AIA versions of §§ 102 and
103.
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’026 patent would have had a Master’s degree in Electrical Engineering or
Computer Engineering, plus at least two years of experience in integrated
circuit design, or alternatively a Bachelor’s degree in one of those fields plus
at least four years of experience in integrated circuit design. Pet. 16 (citing
Ex. 1102 ¶ 49). In our Institution Decision, we found Petitioner’s proposal
consistent with the level of ordinary skill in the art reflected by the prior art
of record, see Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001);
In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In re Oelrich, 579
F.2d 86, 91 (CCPA 1978), and, therefore, preliminarily adopted Petitioner’s
unopposed position as to the level of ordinary skill in the art. Inst. Dec. 15.
Neither Patent Owner, in its Response, nor Dr. Annavaram, in his
declaration, proposes a level of ordinary skill in the art. Instead, Patent
Owner states that “Patent Owner applies Petitioner’s stated skill level for
this response” (PO Resp. 26), and Dr. Annavaram similarly states that “[f]or
the purpose of this declaration, I adopt Dr. Harris’ definition of a [person of
ordinary skill in the art]” (Ex. 2009 ¶ 24).
Nothing in the full record persuades us that our preliminary finding as
to the level of ordinary skill in the art was incorrect. Based on the complete
record, because our preliminary finding is consistent with the level of
ordinary skill in the art reflected by the prior art of record, we maintain and
reaffirm that one of ordinary skill in the art at the time of the invention
would have had a Master’s degree in Electrical Engineering or Computer
Engineering, plus at least two years of experience in integrated circuit
design, or alternatively a Bachelor’s degree in one of those fields plus at
least four years of experience in integrated circuit design. Inst. Dec. 15; see
Pet. 16 (citing Ex. 1102 ¶ 49).
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B. Claim Construction
In an inter partes review, we apply the same claim construction
standard that would be used in a civil action under 35 U.S.C. § 282(b),
following the standard articulated in Phillips v. AWH Corp., 415 F.3d 1303
(Fed. Cir. 2005) (en banc). See Changes to the Claim Construction Standard
for Interpreting Claims in Trial Proceedings Before the Patent Trial and
Appeal Board, 83 Fed. Reg. 51,340, 51,358 (Oct. 11, 2018) (amending
37 C.F.R. § 42.100(b) effective November 13, 2018) (now codified at 37
C.F.R. § 42.100(b) (2019)). In applying such standard, claim terms are
generally given their ordinary and customary meaning, as would be
understood by a person of ordinary skill in the art, at the time of the
invention and in the context of the entire patent disclosure. Phillips, 415
F.3d at 1312–13. “In determining the meaning of the disputed claim
limitation, we look principally to the intrinsic evidence of record, examining
the claim language itself, the written description, and the prosecution
history, if in evidence.” DePuy Spine, Inc. v. Medtronic Sofamor Danek,
Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips, 415 F.3d at
1312–17).
In the Petition, Petitioner asserts that no express constructions are
necessary in this proceeding. Pet. 15–16. Petitioner also notes that the
parties in the related district court litigation did not propose constructions for
any claim terms from the ’026 patent. Id. at 16.
In our Decision on Institution, we rejected Patent Owner’s argument
that claim 14 requires the control circuit to “select among” “a performance
value of the control signal,” “a leakage reduction value of the control
signal,” and “a shut down value of the control signal.” Dec. Inst. 47–49
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(citing Prelim. Resp. 42; Ex. 2007, 1578). We noted that claim 14 does not
recite selecting among the three recited values. Id. at 48. We were not
persuaded by Patent Owner’s citation to a general dictionary definition of
“select” as to “take a choice from among several; pick out,” citing to other
general dictionary definitions that did not recite “among.” Id. (citing
Ex. 3002, 1; Ex. 3003, 1017).
In its Patent Owner Response, Patent Owner proposes a construction
for only one term—“select”—recited in all challenged claims. PO Resp. 26–
34. Citing dictionary definitions (Ex. 3002;2 Ex. 2007), Patent Owner
asserts that the term “select” should be construed to mean “[t]o choose or
pick out in preference to another or others,” which requires “a set of more
than one item be available from which one or more items are chosen in
preference to another or others.” Id. at 26–27 (citing Ex. 3002; Ex. 2007;
Ex. 2009 ¶ 67; Inst. Dec. 48). Patent Owner further contends that the term
“select” should be accorded the same meaning in each claim because “claim
terms are normally used consistently throughout the patent.” Id. at 27–29
(quoting Phillips, 415 F.3d at 1314). As a corollary, Patent Owner argues
that an alternative dictionary definition (Ex. 3003)3 discussed in the
Institution Decision (Inst. Dec. 48), “[t]o identify, within a set of items, all
items that meet a particular criterion,” should be rejected because the
definition is inconsistent with the language of claim 17, which requires

2 Oxford English Dictionary (Ex. 3002), available at
https://www.oed.com/view/Entry/175028?isAdvanced=false&result=2&rske
y=LW57Dp&.
3 IEEE 100 THE AUTHORITATIVE DICTIONARY OF IEEE STANDARDS TERMS
(7th ed. 2000) (Ex. 3003).
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“selecting the leakage reduction value out of a group of leakage reduction
values.” PO Resp. 28 (emphasis added) (citing Ex. 3003; Ex. 1101, 18:5–8).
Petitioner replies that no express construction is necessary and that the
term “select” should be accorded its plain and ordinary meaning. Pet. Reply
2–3. Petitioner also argues that the definition of “select” provided by
Exhibit 3003 should not be excluded from the scope of the claims. Id. at 3.
As an initial matter, we note that the definitions from the dictionaries
discussed above indicate that “to select” or “selecting” something generally
involves choosing or picking out something. See Ex. 2007, 1578 (defining
“select” as “[t]o take as a choice from among several; pick out” (emphases
added)); Ex. 3002, 1 (defining “select” as “[t]o choose or pick out in
preference to another or others” (emphases added)); Ex. 3003, 1017
(defining “select” as “[t]o identify, within a set of items, all items that meet a
particular criterion” (emphasis added)). As discussed below, “selecting,” as
recited in the challenged claims, also involves choosing or picking out
something at a general level.
But our analysis does not stop there because the challenged claims do
not merely recite selecting something in general. Rather, the challenged
claims recite more particularized selection clauses by setting forth specific
limitations that modify the recitation of “selecting” in each claim. For
example, claim 13 recites “selecting,” by the control circuit, a value of a
control signal “based on” the mode indicator and on the leakage indicator.
Ex. 1101, 16:48–50. Claim 14, on the other hand, recites “selecting” a
performance value, a leakage reduction value, and a shut down value
“when” the conditions recited for one of the values are met. Id. at 16:59–
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17:6. Claim 17 recites “selecting” the leakage reduction value “out of a
group” of leakage reduction values. Id. at 18:5–7.
To the extent Patent Owner argues that these particularized selection
clauses recited in different claims must have the same or similar meaning
because they all use the word “selecting” (see PO Resp. 28–29), we disagree
with Patent Owner. See IGT v. Bally Gaming Int’l, Inc., 659 F.3d 1109,
1117 (Fed. Cir. 2011) (“We caution that claim language must be construed
in the context of the claim in which it appears. Extracting a single word
from a claim divorced from the surrounding limitations can lead
construction astray. Claim language must be construed in the claim in
which it appears.” (emphasis added)). The selection clauses recited in these
claims are plainly different on the face of the claims when considering the
material differences in the claim language set forth above. According the
same meaning to the limitations that recite “select . . . based on” indicators,
“select . . . when” certain conditions are met, and “select . . . out of a group”
of values would be improper because it would blur the material differences
in the claim language recited expressly in the claims. Instead, we interpret
the selection clauses recited in the challenged claims “in the context of the
particular claim in which the disputed term appears” and “in the context of
the entire patent, including the specification.” Phillips, 415 F.3d at 1313. In
other words, we do not construe the single word “selecting” in isolation, but,
rather, interpret the full selection clauses recited in the challenged claims in
the context of the entire patent.
Claim 13 recites “selecting, by the control circuit, a value of a control
signal based on the mode indicator and on the leakage indicator.” In our
view, the plain meaning of this limitation is clear on the face of the claim—a
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value of a control signal is selected based on two indicators, the mode
indicator and the leakage indicator.
The plain meaning of the term is supported by the Specification of the
’026 patent, which states:
The control circuit 50 is connected to the leakage indicator
generator for receiving the mode indicator 104. The control
circuit is further connected to the mode indicator generator 40,
for receiving the leakage indicator 105. The control circuit 50
can select the value of the control signal 103 based on the mode
indicator 104 and on the leakage indicator 105. The control
circuit 50 can output a control signal 103 that has a value that is
determined based on one or more indicators.
Ex. 1101, 4:4–11 (emphases added). Thus, at least in this example, the
Specification indicates that “selecting . . . a value of a control signal based
on the mode indicator and on the leakage indicator” recited in claim 13 is
synonymous to determining the value based on the recited indicators.
Determining the value of the control signal based on the mode indicator and
on the leakage indicator, as described in the Specification, is consistent with
the plain meaning of the claim language—i.e., the value of the control signal
is selected based on the mode indicator and on the leakage indicator.
Although Patent Owner proposes to construe “select” as “[t]o choose
or pick out in preference to another or others” (PO Resp. 27–29), Patent
Owner also asserts that “selecting a value of a control signal based on the
mode indicator and on the leakage indicator” recited in claim 13 requires the
indicators to “play a role in deciding which of the multiple values will be
chosen or picked” (id. at 32–33 (emphasis added)). To the extent Patent
Owner argues claim 13’s selecting a value “based on the mode indicator and
on the leakage indicator” requires selecting a value from or among a group
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of multiple values, we disagree with Patent Owner’s argument.4 As noted
above, claim 17 recites selecting a value “out of a group of” values. This
shows that the patentee knew how to use the words selecting out of a group
of values to describe the selection recited in claim 17. If the patentee had
intended to similarly describe the selection recited in claim 13, it could have
done so using the language of claim 17, but did not. See Intellectual
Ventures I LLC v. T-Mobile USA, Inc., 902 F.3d 1372, 1379 (Fed. Cir. 2018)
(citing Unwired Planet, LLC v. Apple Inc., 829 F.3d 1353, 1359 (Fed. Cir.
2016)). We disagree with the “[selecting from among] multiple values”
aspect of Patent Owner’s construction because it would blur the material
differences in the claim language of claim 13 and claim 17 discussed above.
In support of its argument, Patent Owner cites Figures 3 and 4 of the
’026 patent, which, according to Patent Owner, describe “different curves
correlating the level of control signals and the supply voltage as a function
of the process conditions (which indirectly indicates a leakage level and is
therefore a leakage indicator), the mode of operation (retention mode versus
performance-oriented mode) and temperature.” PO Resp. 33 (emphasis
added) (citing Ex. 1101, 5:55–9:37, Figs. 3, 4). Patent Owner further asserts
that “when a mode indicator indicates a performance oriented mode, curves
in Figure 3 will be referenced” and that “the appropriate value or level of the
control signal will then be read from the chosen curves and be selected
accordingly.” Id. (emphasis added) (citing Ex. 2009 ¶ 81). Patent Owner
argues “[i]n this selection process, both the mode indicator and the leakage

4 As discussed above, Patent Owner notes that the dictionary definition it
proposed in the Preliminary Response for “select” was “to take as a choice
from among several.” PO Resp. 25–26 (emphasis added) (citing Ex. 2007).
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indicator affect which curve(s) will be selected and which associated value
of the control signal will be picked in the end.” Id. (emphasis added) (citing
Ex. 2009 ¶ 81; Ex. 1101, 5:48–51).
The term “performance oriented mode,” however, is recited in
claim 14, not in claim 13. As discussed above, claim 14 depends from
claim 13 and recites additional selecting steps, including selecting “a
performance value of the control signal when (i) the leakage indicator
indicates that a leakage of the power gated circuit is below a low leakage
threshold and (ii) the mode indicator indicates that the power gated circuit is
requested to operate at a performance oriented mode.” Ex. 1101, 16:59–64
(emphasis added). Again, Patent Owner does not explain adequately why
the subject matter of the selection step recited in claim 14 is the same as or is
included in the subject matter of the selection step recited in claim 13,
despite the material differences in the claim language on the face of the
claims discussed above. Accordingly, we disagree with Patent Owner’s
argument that claim 13 requires the mode indicator and the leakage indicator
to “play a role in deciding which of the multiple values will be chosen or
picked” in the manner recited in claim 14 or described in the embodiment of
Figure 3 of the ’026 patent. See PO Resp. 32–33.
Nonetheless, to the extent Patent Owner’s proposed definition
indicates that selecting a value “based on” indicators involves “deciding” a
value to choose or pick based on indicators, we agree with Patent Owner
because this aspect of Patent Owner’s proposed construction is consistent
with the Specification’s description of “select[ing] the value of the control
signal based on the mode indicator and on the leakage indicator” as
determining the value based on the recited indicators.
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Other than finding that the selection clause recited in claim 13
encompasses determining the value of the control signal based on the mode
indicator and on the leakage indicator, for purposes of this Final Written
Decision, we need not provide an express construction for other terms within
claim 13’s selection clause—“selecting, by the control circuit, a value of a
control signal based on the mode indicator and on the leakage indicator.”
See Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir.
1999) (holding that only terms that are in controversy need to be construed,
and “only to the extent necessary to resolve the controversy”); see also
Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013,
1017 (Fed. Cir. 2017) (applying Vivid Techs. in the context of an inter partes
review).
Turning next to claim 14, the claim recites:
14. The method according to claim 13, comprising:
selecting a performance value of the control signal when (i) the
leakage indicator indicates that a leakage of the power gated
circuit is below a low leakage threshold and (ii) the mode
indicator indicates that the power gated circuit is requested to
operate at a performance oriented mode;
selecting a leakage reduction value of the control signal when
(i) the leakage indicator indicates that the leakage of the
power gated circuit is above the low leakage threshold and
(ii) the mode indicator indicates that the power gated circuit
is requested to operate at the performance oriented mode; and
selecting a shut down value of the control signal when the mode
indicator indicates that the power gated circuit should be shut
down.
Ex. 1101, 16:58–17:6.
In the Institution Decision, although we determined that we need not
expressly construe any claim term for purposes of deciding whether to
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institute a review (Inst. Dec. 17), we addressed Patent Owner’s apparent or
implicit claim construction argument that claim 14 requires “selecting
among” “a performance value of the control signal,” “a leakage reduction
value of the control signal,” and “a shut down value of the control signal.”
Id. at 47–49 (emphases added) (citing Prelim. Resp. 42). Considering the
claim language, we noted that claim 14 does not recite selecting “among” a
performance value, a leakage reduction value, and a shut down value. Id. at
48. Rather, the claim merely recites “selecting a performance value of the
control signal,” “selecting a leakage reduction value of the control signal,”
and “selecting a shut down value of the control signal.” Id. (citing Ex. 1101,
16:58–17:6). We also found that the plain meaning of the claim language,
“selecting” a value “when” the recited conditions are met, is consistent with
the written description in the Specification. Id. at 48–49 (citing Ex. 1101,
4:30–45, 5:3–9). In addition, we noted that the plain language of the claim
appears to be consistent with the definition from an IEEE dictionary that
defines “select” as “[t]o identify, within a set of items, all items that meet a
particular criterion.” Id. at 48 (citing Ex. 3003, 1017).
At trial, Patent Owner does not argue claim 14 requires “selecting
among” the three types of control signal values recited in claim 14. See
generally PO Resp. Thus, nothing in the full record persuades us that our
preliminary construction of claim 14 was incorrect. Based on the complete
record, we determine that claim 14 does not require “selecting among” “a
performance value of the control signal,” “a leakage reduction value of the
control signal,” and “a shut down value of the control signal.”
Patent Owner asserts that the IEEE dictionary definition discussed
above conflicts with the language of claim 17, which depends from claim 14
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and additionally recites “selecting the leakage reduction value out of a group
of leakage reduction values . . . .” PO Resp. 28 (emphasis added) (citing
Ex. 1101, 18:5-8). In the Institution Decision, we considered the IEEE
definition to interpret the selection clause recited in claim 14, not claim 17.
See Inst. Dec. 47–48. As discussed above, we disagree with Patent Owner
that selection clauses recited in different challenged claims must have the
same or similar meaning. Claim 14 recites “selecting” a performance value,
a leakage reduction value, and a shut down value “when” the conditions
recited for each value are met. Ex. 1101, 16:59–17:6. Claim 17, on the
other hand, recites “selecting” the leakage reduction value “out of a group”
of leakage reduction values. Id. at 18:5–7. The selection clauses recited in
these claims are plainly different on the face of the claims when considering
the material differences in the claim language set forth above. Patent Owner
does not explain adequately why the selection clauses recited in claim 14
must have the same meaning as the selection clause recited in claim 17
despite the material differences in the language of the claims.
Patent Owner also asserts that the aspect of the IEEE dictionary
definition that states “select” means identifying “all items” that meet a
particular criterion conflicts with the language of claim 17 because claim 17
recites selecting a value “out of a group” of values, not all values that meet a
condition. PO Resp. 28. We, however, do not interpret claim 14 as
selecting “all items” that meet the recited conditions. As discussed above,
the plain meaning of claim 14’s selection clauses is “selecting” a value—
i.e., “a performance value,” “a leakage reduction value,” and “a shut down
value”—of the control signal “when” the recited conditions are met. Thus,
the plain language of claim 14 is consistent with the aspect of the IEEE
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dictionary definition to the extent the dictionary defines “select” as
“identify[ing]” or picking “an item” that “meets a particular criterion.” We
did not suggest adopting in our Institution Decision, nor do we adopt for this
Final Written Decision the choosing “all items” aspect of the IEEE
dictionary.
Patent Owner further asserts that the selection recited in the
challenged claims requires the indicators to “play a role in deciding which of
the multiple values will be chosen or picked,” citing Figures 3 and 4 of the
’026 patent. PO Resp. 32–33 (emphasis added).
To the extent Patent Owner argues the selection clause recited in
claim 14 requires selecting a value from or among a group of multiple
values, we disagree with Patent Owner’s argument for reasons similar to
those discussed above with respect to claim 13. As discussed above, the
patentee knew how to describe the concept of selecting a value out of a
group of values for claim 17. If the patentee had intended to similarly
describe the method of selection recited in claim 14, it could have done so
using the language of claim 17, but did not. We disagree with the
“[selecting from among] multiple values” aspect of Patent Owner’s
construction because it would blur the material differences in the language
of claim 14 and claim 17 discussed above.
To the extent Patent Owner argues “selecting” “a performance value,”
“a leakage reduction value,” and “a retention value” recited in claims 14, 17,
18, or 20 requires using functional relationships depicted in the curves
shown on Figures 3 and 4, we disagree with Patent Owner’s argument. We
depart from the plain and ordinary meaning in only two instances: (1) when
a patentee acts as his own lexicographer and (2) when the patentee disavows
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the full scope of the claim term in the specification or during prosecution.
Poly-Am., L.P. v. API Indus., Inc., 839 F.3d 1131, 1136 (Fed. Cir. 2016)
(citing Hill–Rom Servs., Inc. v. Stryker Corp., 755 F.3d 1367, 1371 (Fed.
Cir. 2014)). Here, Patent Owner argues neither lexicography nor disavowal,
and the words “play a role” do not appear in any of the challenged claims.
In our view, the plain meaning of the additionally recited limitations
of claim 14 is clear on the face of the claim—a performance value, a leakage
reduction value, and a shut down value of the control signal are selected
“when” the conditions recited in the limitations are met.5 Similar to our
analysis of claim 13, we perceive no ambiguities in the claim language that
require an express construction of the limitations recited in claim 14.
Turning to the Specification, the ’026 patent describes as follows:
[T]he control circuit 50 may select the performance value of the
control signal 103 when the leakage indicator 105 indicates that
the integrated circuit 10 is slow (and hence exhibit less leakage)
in comparison to most integrated circuits of a batch of integrated
circuits that includes the integrated circuit 10. Similarly, the
control circuit 50 may select the leakage reduction value of the
control signal 103 when the leakage indicator 105 indicates that
the integrated circuit 10 is fast (and hence has high leakage) in
comparison to most integrated circuits of a batch of integrated
circuits that includes the integrated circuit 10.
Ex. 1101, 4:59–5:2 (emphases added). These disclosures in the
Specification are consistent with the plain meaning and the modified IEEE
dictionary definition discussed above. They are also consistent with the
alternative dictionary definition discussed in the Institution Decision—“[t]o

5 The parties do not argue the terms “performance value,” “leakage
reduction value,” or “shut down value” are ambiguous, nor do the parties
propose constructions for these terms.
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choose or pick out in preference to another or others.” See Ex. 3002, 1; Inst.
Dec. 61.
Based on the complete record, we determine that the selection clauses
recited in the claim 14 are not limited as Patent Owner argues.
We need not construe any other claim terms for purposes of this Final
Written Decision. See Vivid Techs., 200 F.3d at 803.
C. Anticipation by Kim
Petitioner contends claims 13 and 14 are unpatentable as anticipated
by Kim. Pet. 26–57.
1. Relevant Principles of Law
A claim is unpatentable under 35 U.S.C. § 102 only if a single prior
art reference expressly or inherently describes each and every limitation set
forth in the claim. See Perricone v. Medicis Pharm. Corp., 432 F.3d 1368,
1375 (Fed. Cir. 2005); Verdegaal Bros., Inc. v. Union Oil Co., 814 F.2d 628,
631 (Fed. Cir. 1987). Further, a reference cannot anticipate “unless [it]
discloses within the four corners of the document not only all of the
limitations claimed[,] but also all of the limitations arranged or combined in
the same way as recited in the claim.” Net MoneyIN, Inc. v. VeriSign, Inc.,
545 F.3d 1359, 1371 (Fed. Cir. 2008). Although the elements must be
arranged in the same way as in the claim, “the reference need not satisfy an
ipsissimis verbis test,” i.e., identity of terminology is not required. In re
Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009); In re Bond, 910 F.2d 831,
832 (Fed. Cir. 1990). Moreover, the prior art reference is read from the
perspective of one with ordinary skill in the art. In re Graves, 69 F.3d 1147,
1152 (Fed. Cir. 1995) (“A reference anticipates a claim if it discloses the
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claimed invention such that a skilled artisan could take its teachings in
combination with his own knowledge of the particular art and be in
possession of the invention.” (citation and quotation marks omitted)); In re
Preda, 401 F.2d 825, 826 (CCPA 1968) (“[I]n considering the disclosure of
a reference, it is proper to take into account not only specific teachings of the
reference but also the inferences which one skilled in the art would
reasonably be expected to draw therefrom.”). We analyze this asserted
ground based on anticipation with the principles identified above in mind.
2. Overview of Kim (Ex. 1104)
Kim relates generally to die-to-die process variation compensation for
digital circuits. Ex. 1104 ¶ 7. In particular, Kim describes an array of sleep
transistors that can be used to reduce leakage of a circuit by enabling a
combination of sleep transistors. Id. at code (57). As background, Kim
describes that “as transistor sizes have become ever smaller, the leakage
power consumption during active modes has become a serious problem
thereby resulting in some fast dies that are excessively leaky to . . . be
discarded.” Id. ¶ 8. According to Kim, therefore, “it would be desirable to
find a way to retain and use these ‘leaky’ dies.” Id. Kim purports to provide
this desired solution.
As presented in some embodiments disclosed herein, it has been
discovered that for fast but leaky dies, desired performance and
leakage reduction can be attained at the same time by, if
necessary, turning on a sub-combination of the sleep transistors
during active modes, depending on the leakage characteristics of
a particular chip or group of associated chips.
Id. ¶ 10 (emphases added).
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Figure 1 of Kim is reproduced below.

Figure 1 is a schematic diagram of an exemplary processor chip with a
programmable sleep transistor array and a virtual supply. See Ex. 1104
¶¶ 2, 11. As shown in Figure 1, chip 100 comprises an array of sleep
transistors P1 to PN, NAND gates G1 to GN, and test/operation register 110
comprising memory cells C1 to CN. Id. ¶ 11.
Kim describes that sleep transistors P1 to PN are PMOS transistors
that are coupled to a high supply voltage reference (VCC) and NAND gates
G1 to GN. See id. Each of NAND gates G1 to GN is coupled to a memory
cell (one of memory cells C1 to CN) associated with the particular NAND
gate and sleep transistor combination. Id. As depicted in Figure 1, sleep
transistors P1 to PN are used to provide a virtual high supply voltage
(VVCC) from a high supply reference voltage (VCC). See id. ¶¶ 11, 21, 23;
Fig. 1.
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Figure 5 of Kim is reproduced below.

Figure 5 is a block diagram of a computer system having a microprocessor
with at least one programmable sleep transistor array in an exemplary
embodiment. Id. ¶ 6. As depicted in Figure 5, microprocessor 502 includes
programmable sleep transistor array (PTSA) 503. Id. ¶ 23. Also,
microprocessor 502 is coupled to power supply 504 to receive power for
operation. Id. Kim describes that PTSA 503 receives power from power
supply 504 and provides a virtual high supply voltage (VVCC) to one or
more functional blocks within microprocessor 502 to reduce leakage during
an active mode. Id.
Kim provides disclosures on programming a programmable sleep
transistor array to obtain suitable sleep transistor array combinations to
supply a virtual supply voltage that reduces leakage in a processor or chip.
Id. ¶¶ 10–23. As depicted in Figure 1, test/operation register 110 has a
signal (labeled Prog.) to program the memory cells. Id. ¶ 14. Figure 1 also
shows a sleep mode signal (labeled Sleep) coupled to each of the NAND
gates. Id. ¶ 11. Kim describes that the Sleep signal controls the sleep
transistors that have been designated for active use once the cells are
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programmed for normal operation (e.g., burned at the factory or loaded at
start-up). Id. ¶ 16. Referencing Figure 1, Kim describes that, in the depicted
embodiment, when the Sleep signal is asserted (Low), NAND gates G1 to
GN all output a High, which turns off the sleep transistors. Id. On the other
hand, when the Sleep signal is de-asserted (High) during an active mode, the
NAND gates are controlled by the cells, C1 to CN, that are used for normal
operation. Id. Kim describes that when a cell outputs a High signal to its
NAND gate, the sleep transistor coupled to the gate is turned on, whereas a
cell output of a Low causes the sleep transistor to be turned off. Id.
Figure 2 of Kim is reproduced below.

Figure 2 shows an exemplary routine for identifying a suitable
combination of enabled sleep transistors in a programmable sleep transistor
array. Id. ¶ 3.
Kim describes that routine 201, shown in Figure 2, is used for testing
a chip to determine sleep transistor combinations to be turned on during an
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active mode in order to provide a virtual supply voltage (VVCC) to the chip
or a functional block of the chip. Id. ¶¶ 17, 18. According to Kim,
routine 201 may be performed during the manufacturing process to test chips
and determine the amount of leakage in a chip during an active mode. Id.
¶ 17. Kim describes that routine 201 may also be used to program the
memory cells in the test/operation register at the start-up of an operation in
order to determine a suitable array of enabled sleep transistors during normal
operation. Id. ¶¶ 20, 22. Referencing Figure 1, Kim also describes that
test/operation register 110 (i.e., memory cells C1 to CN) should be
programmable during a test phase (e.g., during the manufacturing process)
and should also be programmable for normal operation. Id. ¶ 14. According
to Kim, both types of programming may be achieved using the same
structure. Id.
Regarding the steps performed by routine 201, Kim describes that
initially at step 202, each sleep transistor in an array is enabled, e.g., by
programming each memory cell with a value of 1. Id. ¶ 18. Next, at
step 204, with the sleep transistor array providing a virtual supply voltage to
the chip or a functional block of the chip, the active leakage in the chip is
measured. Id. Then at step 206, a determination is made whether the active
leakage is excessive. Id. ¶ 19. If the answer is Yes (i.e., the leakage is
excessive), then the conductance of the sleep transistor array is decremented,
e.g., by turning off one or more sleep transistors in the array. Id. Then, the
routine loops back to step 204 to measure the leakage with the modified
sleep transistor array combination (having a decreased conductance), and
then proceeds again to step 206 to check if the newly measured leakage is
excessive. Id. This process continues until the measured active leakage is
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not excessive, at which time the routine proceeds to step 208 to determine
whether the chip is sufficiently fast. Id. ¶¶ 19, 20. If the chip is fast enough
(with the reduced virtual supply voltage provided to the chip by the sleep
transistor array combination determined in steps 204 and 206 that results in
non-excessive leakage), then at step 210 the determined enabled transistor
array combination is stored or programmed into register 110. Id. ¶ 20. For
example, the combination may be burned into the register if it is one time-
programmable memory, or it may be stored to be part of a start-up routine to
be programmed into the register when the chip starts up. Id. If, on the other
hand, the chip is determined to be not sufficiently fast, then at step 214 the
chip may be discarded or otherwise devalued. Id.
Once determined, an enabled transistor combination may be saved to
be programmed at startup of an operation or during the manufacturing
process. Id. ¶ 22.
3. Independent Claim 13
Petitioner contends that the embodiments depicted in Figures 4 and 5
disclose all of the circuit elements and signals recited in claim 13, including
“a power gated circuit,” “a power gating switch,” “an input supply voltage,”
“an output supply voltage,” “a control circuit,” “a control signal,” “a mode
indicator,” and “a leakage indicator.” Pet. 26–48. Petitioner asserts that the
operation of the circuit elements shown in Kim’s Figures 4 and 5 discloses
the steps recited in claim 13. Id. at 29–52. Patent Owner does not dispute
Petitioner’s contentions on all but one of the limitations of claim 13—
namely, “selecting . . . a value of a control signal based on the mode
indicator and on the leakage indicator” as recited in claim element 13[E].
PO Resp. 34–35; PO Sur-reply 8–10. For the reasons discuss below, we
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determine that Petitioner has demonstrated, by a preponderance of the
evidence, that claim 13 is unpatentable under 35 U.S.C. § 102 as anticipated
by Kim.
a. Preamble
The preamble of claim 13 recites “method for supplying an output
supply voltage to a power gated circuit.” Petitioner asserts that, to the extent
that the preamble is limiting, Kim teaches a method for supplying an output
supply voltage to a power gated circuit. Pet. 26.6
Figures 4 and 5 of Kim, as annotated by Petitioner in different colors,
are reproduced below.

Id. at 27. Annotated Figures 4 and 5 reproduced above show Petitioner’s
identification of claim 13’s recited circuit elements and signals allegedly
present in Kim.

6 Because Petitioner has shown that the recitations of the preamble are
disclosed by Kim, we need not determine whether the preamble is limiting.
See Vivid Techs., 200 F.3d at 803.
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Petitioner’s color annotations are described below in the context of
our discussion of Petitioner’s mapping of various circuit elements and
signals of Kim to the allegedly corresponding circuit elements and signals
recited in claim 13. For example, Petitioner asserts that sleep transistor
array P1–PN shown in Annotated Figures 4 and 5 (annotated in grey)
discloses the “power gating switch” recited in claim 13. Pet. 27. Petitioner
argues that, as shown in the figures, Kim’s sleep transistor array P1–PN
receives input voltage VCC (annotated in green) (the recited “input supply
voltage”) and provides virtual supply voltage VVCC (annotated in purple)
(the recited “output supply voltage”) to “one or more functional blocks
within the processor 502” (annotated in yellow) (the recited “power gated
circuit”). Id. at 26–27 (citing Ex. 1104, Figs. 4, 5, ¶ 23). Petitioner contends
that Kim’s sleep transistor array P1–PN is a “power gating switch” because
it switches output supply voltage VVCC to the functional blocks in
processor 502 (the recited “power gated circuit”) ON and OFF. Id. at 27–28
(citing Ex. 1104 ¶ 16). Petitioner also asserts that the “functional blocks
within [Kim’s] processor 502” are the “power gated circuit” recited in
claim 13 because the blocks in Kim’s processor 502 receive the gated virtual
supply voltage VVCC provided by Kim’s power gating switch. Id. at 28
(citing Ex. 1104 ¶ 23; Ex. 1101, 2:55–56, 7:57–63 (describing an “NMOS
power gating switch” and a “PMOS power gating switch”)).
As discussed above, Patent Owner does not dispute Kim teaches the
preamble of claim 13. See PO Resp. 34–35.
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We agree with Petitioner’s analysis and find, based on the complete
record and for the reasons explained by Petitioner, that Petitioner has
demonstrated sufficiently Kim discloses the preamble of claim 13.7
b. Claim Elements 13[B] and 13[G]
We next address claim element 13[B], which recites “providing to an
input port of a power gating switch an input supply voltage,” and claim
element 13[G], which recites “providing, from an output port of the power
gating switch, the output supply voltage to the power gated circuit.” We
address these claim elements together because they both relate to the subject
matter of providing a gated supply voltage to a power gated circuit by a
power gating switch.
Petitioner presents an annotated version of Figure 4 of Kim (not
reproduced herein) and identifies the connection between input supply
voltage VCC (the recited “input supply voltage”) and the sources of sleep
transistors P1–PN as the “input port of a power gating switch” recited in
claim 13. Pet. 29 (citing Ex. 1104 ¶ 11 (explaining the sleep transistors “are
coupled [to] a high supply reference (VCC)”), Fig. 4)). Petitioner also maps
the recited “output port of the power gated circuit” to the drains of sleep
transistor array P1–PN (the recited “power gating switch.”) Id. at 46.
Petitioner asserts that the output of sleep transistor array P1–PN is virtual
supply voltage VVCC (the recited “output supply voltage”) and that the
output voltage VVCC is supplied to “one or more functional blocks” within

7 We also find that Patent Owner has waived any argument directed to the
preamble of claim 13. See Paper 12 (Scheduling Order), 7 (“Patent Owner is
cautioned that any arguments for patentability not raised in the response may
be deemed waived.”).
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processor 502 (annotated in yellow in Annotated Figures 4 and 5 reproduced
above) (the recited “power gated circuit”). Id. at 44–45 (citing Ex. 1104
¶ 23, Figs. 4, 5).
Thus, Petitioner asserts that Kim discloses “providing to an input port
of a power gating switch an input supply voltage” and “providing, from an
output port of the power gating switch, the output supply voltage to the
power gated circuit,” as recited in claim 13.
As discussed above, Patent Owner does not dispute Kim teaches the
limitations of claim 13 discussed in this subsection. See PO Resp. 34–35.
We agree with Petitioner’s analysis and find, based on the complete
record and for the reasons explained by Petitioner, that Petitioner has
demonstrated sufficiently Kim discloses all of the limitations recited in
claim elements 13[B] and 13[G].8
c. Claim Element 13[C]
Turning next to claim element 13[C], which recites “receiving, by a
control circuit, a mode indicator that indicates of a desired mode of the
power gated circuit,” Petitioner references Annotated Figures 4 and 5
reproduced above and identifies NAND gates G1–GN (annotated in red) as
the recited “control circuit” and the Sleep signal (annotated in blue) as the
recited “mode indicator.” Pet. 31, 33. Regarding the operational aspects of
these structural elements, Petitioner asserts that NAND gates G1–GN (the
recited “power gating switch”) receives a Sleep signal (the recited “mode
indicator”) that indicates whether processor 502 (the recited “power gated

8 We also find that Patent Owner has waived any argument directed to these
limitations of claim 13. See Paper 12, 7.
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circuit”) will be in an active mode or a sleep mode. Id. at 31–32 (citing
Ex. 1104 ¶¶ 11, 16, Figs. 4, 5). Petitioner contends that when Kim’s NAND
gates G1–GN receive a low Sleep signal, NAND gates G1–GN all output a
high, which turns OFF all transistors in sleep transistor array P1–PN. Id. at
32–33 (citing Ex. 1104 ¶¶ 16, 23 (“[W]hen the Sleep signal is asserted
(Low), then the NAND gates G1 to GN all output a High, which turn off the
sleep transistors.”)). Petitioner argues that functional blocks within
processor 502 are thus “gated” from supply voltage VCC, placing the
functional blocks in a sleep state. Id. at 32 (citing Ex. 1104 ¶¶ 16, 23). On
the other hand, when Kim’s NAND gates G1–GN receive a high Sleep
signal, “the NAND gates are in effect controlled by the cells, C1 to CN,”
which turns ON at least some of sleep transistors P1–PN. Id. at 32–33
(citing Ex. 1104 ¶¶ 10, 16, 23). Thus, Petitioner asserts that when NAND
gates G1–GN receive a high Sleep signal, Kim’s sleep transistor array
provides the gated supply voltage VVCC to functional blocks within the
processor 502, placing the functional blocks in an active state. Id.
Petitioner argues that because Kim’s Sleep signal indicates the desired
mode (active or sleep) of processor 502 (the recited “power gated circuit”),
the Sleep signal is “a mode indicator that indicates a desired mode of the
power gated circuit.” Id. at 33 (citing Ex. 1102 ¶ 72). Thus, Petitioner
asserts that Kim discloses “receiving, by a control circuit, a mode indicator
that indicates of a desired mode of the power gated circuit,” as recited in
claim 13. Id. at 31–33.
As discussed above, Patent Owner does not dispute Kim teaches the
limitation of claim 13 discussed in this subsection. See PO Resp. 34–35.
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We agree with Petitioner’s analysis and find, based on the complete
record and for the reasons explained by Petitioner, that Petitioner has
demonstrated sufficiently Kim discloses “receiving, by a control circuit, a
mode indicator that indicates of a desired mode of the power gated circuit,”
as recited in claim element 13[C].9
d. Claim Element 13[D]
Next, Petitioner provides an annotated version of Kim’s Figure 4,
which we refer to as Second Annotated Version of Figure 4, and asserts that
Kim teaches claim element 13[D], which recites “receiving, by the control
circuit, a leakage indicator that indicates of a leakage level of the power
gated circuit.” Pet. 34–35.

9 We also find that Patent Owner has waived any argument directed to this
element of claim 13. See Paper 12, 7.
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Second Annotated Version of Kim’s Figure 4 provided in the Petition
is reproduced below.

Pet. 35 (citing Ex. 1104, Fig. 4). Second Annotated Version of Kim’s
Figure 4 reproduced above shows Petitioner’s identification of “leakage
indicator that indicates of a leakage level of the power gated circuit.”
Referencing Second Annotated Version of Figure 4, Petitioner asserts
that Kim teaches that register 110 includes memory cells C1–CN (annotated
in brown). Pet. 34–35 (citing Ex. 1104, Fig. 4). Petitioner identifies the
output of Kim’s memory cells C1–CN as the recited “leakage indicator that
indicates of a leakage level of the power gated circuit.” Id. at 38.
Petitioner cites routine 201 depicted in Figure 2 of Kim (reproduced
in Section III.C.2. above) and asserts that “Kim details how memory
cells C1-CN are used in ‘routine 201 for testing a chip . . . to determine the
amount of leakage in a chip’ and ‘sleep transistor combinations to be turned
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on . . . during an active mode.’” Id. at 35 (citing Ex. 1104, Fig. 2, ¶¶ 17–20).
Petitioner asserts that Kim’s routine 201 discloses
(1) turning ON all sleep transistors P1-PN (step 202),
which maximizes the output level for virtual supply voltage
VVCC, Ex. 1104, [0018];
(2) measuring “the active leakage in the chip (or functional
block supplied by [VVCC])” (step 204), id., [0018], [0023]
(explaining that “functional blocks” can be “functional blocks
within the processor 502”);
(3) determining “if the active leakage is excessive”
(step 206), id., [0019];
(4) if leakage is excessive, turning OFF at least one sleep
transistor to decrease the output level for virtual supply voltage
VVCC (step 212), id., [0019]; see also id., [0016] (“[D]uring an
active mode, the NAND gates in effect are then controlled by the
cells, C1 to CN ….. If a sleep transistor was designated to be on
during an active mode, then its cell outputs a High to its NAND
gate, causing the transistor to be turned on. Alternatively, if a
sleep transistor was designated to be off, then its cell outputs a
Low, causing the transistor to be turned off during the active
mode.”);
(5) repeating steps 204 (measure leakage), 206
(determining if the measured leakage is excessive), and 212
(decreasing VVCC) until the measured leakage is not excessive,
id.; and
(6) “stor[ing] the enabled transistor array combination …
so that it will be programmed into the register 110 [410],” and
using those stored values to determine the level of VVCC during
active mode, id., [0016], [0020]; Ex. 1102, ¶ 75.
Pet. 36–37 (citing Ex. 1104 ¶¶ 16, 18, 19, 20, 22, 23; Ex. 1102 ¶ 75).
According to Petitioner, the cited disclosure of Kim teaches that the output
of memory cells C1–CN reflects the amount of measured leakage in
processor 502, and is used to determine which sleep transistors P1–PN will
be ON or OFF when the processor is in an active mode. Id. at 37–38.
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Citing the testimony of Dr. Harris, Petitioner provides examples of the
amount of measured leakage in processor 502 indicated by the output of
memory cells C1–CN. Pet. 38 (citing Ex. 1104 ¶¶ 16–20; Ex. 1102 ¶ 76).
Petitioner argues that because Kim’s routine 201 starts with turning ON all
sleep transistors P1–PN, if processor 502 is found to not have excessive
leakage at the very first execution of Kim’s step 206, the output from
cells C1–CN would have the value of all ones (1s) after completion of
routine 201, indicating that processor 502, as found, has low leakage. Id.
Petitioner contends that, if, on the other hand, processor 502 is found to have
higher leakage, routine 201 would execute step 206 more than once, turning
OFF some transistors in the sleep transistor array, and the output from Kim’s
cells C1–CN would include some zeroes (0s) upon completion of
routine 201. Id. (citing Ex. 1104 ¶¶ 16–20; Ex. 1102 ¶ 76). In other words,
the output from Kim’s memory cells C1–CN, as determined by the value
stored in the cells at the end of executing routine 201, would indicate the
leakage level of processor 502 as found at the beginning of the testing—that
is, a leakage level lower than the excessive level threshold (when the output
of the memory cells is all ones (1s)) or a leakage level at or higher than the
excessive level threshold (when the output of the memory cells includes
some zeroes (0s)). See id. Petitioner argues, therefore, the output of Kim’s
memory cells C1–CN is the claimed “leakage indicator that indicates a
leakage level of the power gated circuit.” Id.
Petitioner asserts that Kim measures leakage during manufacturing
and then stores in memory cells C1–CN the results of the leakage
measurement, which determines during operation which sleep transistors
will be ON and OFF in an active mode. Pet. 38–39 (citing Ex. 1104 ¶ 20).
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According to Petitioner, this is similar to the disclosure in the ’026 patent,
which describes that “leakage indicator” can be used “during the
manufacturing process of the integrated circuit 10 or based on a leakage test
conducted after the production of the integrated circuit 10 . . ., [and] can
include measuring the actual leakage of the integrated circuit 10, or
determining indirectly the leakage.” Id. at 38 (quoting Ex. 1101, 3:46–54).
Petitioner further asserts that Kim discloses “receiving, by the control
circuit, a leakage indicator that indicates of a leakage level of the power
gated circuit,” as recited in claim 13 because Kim describes that NAND
gates G1–GN (the recited “control circuit”) receive the output of memory
cells C1–CN (the recited “leakage indicator that indicates a leakage level of
the power gated circuit”). Pet. 39 (citing Ex. 1104, Figs. 1, 4, ¶ 11 (“The
NAND gates each have two inputs, one coupled to a sleep mode signal
(Sleep) and the other coupled to a memory cell (one of C1 to CN) associated
with the particular NAND gate and sleep transistor combination.” (emphasis
by Petitioner)); Ex. 1102 ¶ 78).
As discussed above, Patent Owner does not dispute Kim teaches the
limitation of claim 13 discussed in this subsection. See PO Resp. 34–35.
We agree with Petitioner’s analysis and find, based on the complete
record and for the reasons explained by Petitioner, that Petitioner has
demonstrated sufficiently Kim discloses all of the limitations recited in
claim element 13[D].10

10 We also find that Patent Owner has waived any argument directed to this
element of claim 13. See Paper 12, 7.
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e. Claim Element 13[E]
Turning next to claim element 13[E] which recites “selecting, by the
control circuit, a value of a control signal based on the mode indicator and
on the leakage indicator,” Petitioner identifies the collective output of
NAND gates G1–GN as the recited “control signal.” Pet. 41. As discussed
above, Petitioner asserts that during a sleep mode of Kim, the Sleep signal is
asserted low, which in turn causes NAND gates G1–GN to all output a high
signal that turns off all their respective sleep transistors P1–PN. Id. (citing
Ex. 1104 ¶ 16 (“[W]hen the Sleep signal is asserted (Low), then the NAND
gates G1 to GN all output a High, which turn off the sleep transistors.”).
Petitioner argues, therefore, the output (the recited “control signal”) from
NAND gates G1–GN (the recited “control circuit”) is based on the Sleep
signal (the recited “mode indicator”). Id. (citing Ex. 1102 ¶ 81).
Petitioner also asserts that during an active mode of Kim, the output
of NAND gates G1–GN is based on both the Sleep signal (which is
de-asserted high) and the output of memory cells C1–CN (which adjusts the
value11 of the output of the NAND gates G1–GN in accordance with the
leakage measurements and adjustments made using the method of Figure 2).
Id. at 41–42 (citing Ex. 1104 ¶ 16; Ex. 1102 ¶ 82).
Petitioner asserts that Kim discloses that NAND gates G1–GN (the
recited “control circuit”) output a control signal that selectively turns

11 As discussed below in the section on claim 14, Petitioner’s declarant,
Dr. Harris, illustrates various values of the collective output of NAND
gates G1–GN in the context of his testimony on claim 14. See Ex. 1102 ¶ 94
(providing a table of various values (comprising ones (1s) and zeroes (0s))
of the collective output of NAND gates G1–GN for an example case of
5 NAND gates).
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individual transistors in sleep transistor array P1–PN ON or OFF such that
virtual supply voltage VVCC is output to processor 502 at a level different
from the level of input supply voltage VCC. Id. at 39–40 (citing Ex. 1104,
Fig. 4, ¶ 16). Petitioner argues that because the value of the collective
output of NAND gates G1–GN (the recited “control signal”) is determined
by NAND gates G1–GN (the recited “control circuit”) based on the Sleep
signal (the recited “mode indicator”) and on the outputs of memory
cells C1–CN (the recited “leakage indicator”), Kim discloses “selecting, by
the control circuit, a value of a control signal based on the mode indicator
and on the leakage indicator,” as recited in claim 13. Id. at 41–42.
Petitioner argues that during a sleep mode, the Sleep signal is asserted
low, which in turn causes NAND gates G1–GN to all output a high signal
that turns off all their respective sleep transistors P1–PN. Pet. 41 (citing
Ex. 1104 ¶ 16 (“[W]hen the Sleep signal is asserted (Low), then the NAND
gates G1 to GN all output a High, which turn off the sleep transistors.”)).
Petitioner asserts, therefore, the output (the claimed “control signal”) from
Kim’s NAND gates G1–GN (the claimed “control circuit”) is based on the
Sleep signal (the claimed “mode indicator”). Id. Petitioner further asserts
that during an active mode, the output of NAND gates G1–GN is based on
both the Sleep signal (which is de-asserted high) and the outputs of memory
cells C1–CN (which adjust the value of the NAND gates G1–GN outputs in
accordance with the leakage measurements and adjustments made using the
method of Figure 2). Id. at 41–42 (citing Ex. 1104 ¶ 16). Petitioner argues
because the value of Kim’s NAND gate outputs (the claimed “value of the
control signal”) depends on both the “Sleep signal” (the claimed “mode
indicator”) and the outputs of memory cells C1–CN (the claimed “leakage
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indicator”), Kim teaches “selecting, by the control circuit, a value of a
control signal based on the mode indicator and on the leakage indicator,” as
recited in claim 13. Id. at 43.
Patent Owner asserts that Kim’s NAND gates “decide[] whether to
pass through the bit pattern in the memory cells C1-CN, based solely on the
value of the sleep signal” and “do not affect which of the two bit patterns (all
1’s or -B) will be outputted as the control signal.” PO Resp. 34–35. Citing
the testimony of its declarant, Dr. Annavaram, Patent Owner contends that
Kim’s NAND gate operates such that “[i]f the sleep signal is 0, it does not
pass through those bits and outputs all 1’s instead; and if the sleep signal is
low, it passes through the bit pattern with inversion.” Id. (citing Ex. 2009
¶ 84).
As discussed above in Section III.B (Claim Construction), Patent
Owner argues that “select[ing] a value of a control signal based on the mode
indicator and on the leakage indicator” recited in claim 13 requires the
indicators to “play a role in deciding which of the multiple values will be
chosen or picked.” Id. at 32–33.12 Patent Owner argues that the output of
Kim’s NAND gates (the claimed “control signal”) is not “based on” the bit
pattern in Kim’s memory cells C1–CN (the claimed “leakage indicator”)
because “a bit pattern that is being passed through with inversion” does not
“play a role” in selecting the value of the control signal. Id. at 32–33 (citing

12 As discussed in Section III.B, to the extent Patent Owner argues claim 13
requires selecting a value from or among a group of multiple values, we
disagree with Patent Owner’s argument. Claim 13 does not require selecting
a value among several or multiple (i.e., more than two) values.
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Ex. 2009 ¶ 82); see also id. at 34–35 (making the same argument, citing
Ex. 2009 ¶¶ 80–82, 84, 85).
In reply, Petitioner asserts that Kim’s sleep signal (the claimed “mode
indicator”) and the memory cell signal value (the claimed “leakage
indicator”) affect what control signal value is chosen because when Kim’s
sleep signal indicates “an active mode,” the outputs of Kim’s NAND gates
(the claimed “value of the control signal”) are controlled by the [values in]
cells, C1–CN. Pet. Reply 10–11 (citing Pet. 39–42 (citing Ex. 1104 ¶ 16)).
We agree with Petitioner’s argument and disagree with Patent
Owner’s argument. As Petitioner persuasively argues (Pet. Reply 10–11
(citing Pet. 39–42)), when the sleep signal is active (or 1), the output of
Kim’s NAND gates (the claimed “value of the control signal”) would be
different for different value of Kim’s memory cells C1–CN (the claimed
“leakage indicator”) because, as Patent Owner concedes, the value of the
output of Kim’s NAND gates equals the value of Kim’s memory cells C1–
CN “with inversion” (PO Resp. 33–34 (citing Ex. 2009 ¶ 82)).
During the oral hearing, Patent Owner acknowledged that, when the
“bit pattern” of Kim’s memory cells C1–CN is allowed to “pass through,”
the output of Kim’s NAND gates will be different depending on the value of
Kim’s memory cells C1–CN.
JUDGE CHUNG: If you have a different bit pattern, when the
bit pattern is allowed to pass through, the different bit pattern
[passed through] will affect the output, right?
MS. ZHONG: With respect -- I'm sorry.
JUDGE CHUNG: Go ahead.
MS. ZHONG: Your Honor has the --
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JUDGE CHUNG: So my question is, isn’t it the case the value
of the bit pattern does have an effect on the output because
depending on what the bit pattern is the output will be different?
MS. ZHONG: Yes. So I think it comes back to what the claim
language is. The claim language is a control circuit arranged to
select a value. It’s not a control circuit being arranged to produce
or output a value. That’s different. Select doesn’t equal to
produce or output.
Tr. 47:7–23. Because the output of Kim’s NAND gates will be different
depending on the value of Kim’s memory cells C1–CN allowed to “pass
through,” we agree with Petitioner that the value of Kim’s memory cells C1–
CN (the claimed “leakage indicator”) “plays a role” in deciding what the
output of Kim’s NAND gates (the claimed “value of the control signal”) will
be.
Moreover, Patent Owner acknowledged that the output of Kim’s
NAND gate is determined based on the inputs to the NAND gates (i.e., the
sleep signal input and the memory cell signal input).
JUDGE CHUNG: But, knowing a little bit about how a NAND
gate works, isn’t it the case that the input to the NAND gates, G1
through GN, with the input of the sleep signal and the C1 through
CN signal, isn’t it the case that input to the NAND gate
determines what the output is?
MS. ZHONG: Okay. So any logic gate, the output will depend
on the input. That’s for sure.
Tr. 44:18–25; but see id. at 45:3–10 (stating that even if the “output is in
control of the input, . . . that does not mean the selection is based on that
input”). Thus, we find that Kim’s NAND gate (the claimed “control
circuit”) operates to determine its output (the claimed “value of the control
signal”) based on its input of the sleep signal (the claimed “mode indicator”)
and the memory cell value input (the claimed “leakage indicator”). As
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discussed in Section III.B, the Specification indicates that “select[ing] the
value of the control signal based on the mode indicator and on the leakage
indicator” recited in claim 13 is synonymous to determining the value based
on the recited indicators. See Ex. 1101, 4:4–11. Thus, the evidence of
record shows that Kim teaches “selecting, by the control circuit, a value of a
control signal based on the mode indicator and on the leakage indicator,” as
recited in claim 13.
As discussed above, Patent Owner asserts that the term “select”
should be construed to mean “[t]o choose or pick out in preference to
another or others.” PO Resp. 27–29 (citing Ex. 3002). Patent Owner
contends that Kim does not disclose “selecting, by the control circuit, a
value of a control signal based on the mode indicator and on the leakage
indicator” under this construction. PO Sur-reply 8–9.
We disagree with Patent Owner’s argument. On the contrary, we find
that Patent Owner’s description of the operation of Kim’s NAND gate—“[i]f
the sleep signal is 0, it does not pass through those bits and outputs all 1’s
instead; and if the sleep signal is low, it passes through the bit pattern with
inversion” (PO Resp. 33)—meets Patent Owner’s proposed definition. That
is, when the sleep signal (the claimed “mode indicator”) is 0, the NAND
gates choose the output to be a signal of all 1s (the claimed “value of the
control signal”) in preference to another value, e.g., the value determined by
the output of the memory cells C1–CN. When, on the other hand, the sleep
signal is 1, the NAND gates choose the output to be a signal of the inverse
(or complement) of the output of the memory cells C1–CN (the claimed
“leakage indicator”), as opposed to another value, e.g., all 1s. Thus, Kim’s
NAND gates select the value of the control signal based on the mode
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indicator and on the leakage indicator even under Patent Owner’s proposed
construction of “select.”
Petitioner persuasively argues that the ’026 patent describes selecting
the value of the control signal by a control circuit comprising “one or more
logical gates,” such as Kim’s NAND gates. Pet. Reply 12 (citing Ex. 1101,
4:22–25; Ex. 1130 ¶¶ 21, 23–31, 34–36). In the cited portion of his Reply
Declaration, Dr. Harris cites the following disclosure from the Specification:
In the shown example, the control circuit 50 includes a digital
circuit 51 that is arranged to (i) receive indicators (such as the
mode indicator 104, the leakage indicator 105 and (ii) send a
digital control signal 108 to a digital to analog converter (DAC)
52. . . . The digital circuit 51 can include a storage element such
as a register or multiple flip flops, can include one or more logical
gates, can include a combination of a storage element and one or
more logical gates, and the like.
Ex. 1130 ¶ 35 (emphases added) (citing Ex. 1101, 4:15–25). Dr. Harris
testifies that “Kim’s NAND gates exactly match the ’026 patent’s disclosed
control circuit,” producing the same output given the same inputs. Id. We
are persuaded by Petitioner’s argument and evidence that Kim’s NAND
gates are logical gates similar to the ’026 patent’s disclosed control circuit
comprising one or more logical gates, producing the control signal output
based on the inputs of the mode indicator and the leakage indicator.
For the foregoing reasons and based on the complete record, we
determine that Petitioner has demonstrated sufficiently that Kim discloses
“selecting, by the control circuit, a value of a control signal based on the
mode indicator and on the leakage indicator,” as recited in claim
element 13[E], notwithstanding the arguments from Patent Owner.
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f. Claim Element 13[F]
Next, Petitioner provides an annotated version of Kim’s Figure 4,
which we refer to as Third Annotated Version of Figure 4, and asserts that
Kim discloses “supplying the control signal to a control port of the power
gating switch,” as recited in claim element 13[F]. Pet. 42–43.
Third Annotated Version of Kim’s Figure 4 provided in the Petition is
reproduced below.

Id. at 43. Third Annotated Version of Kim’s Figure 4 reproduced above
shows Petitioner’s identification of “a control port” and a “control signal”
allegedly present in Kim. Id.
Referencing Third Annotated Version of Figure 4 Petitioner contends
that the port (annotated in dark grey circles) driving the gates of sleep
transistors P1–PN (the recited “power gating switch”) is the “control port of
the power gating switch” recited in claim 13. Id. at 42–43. As discussed
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above, Petitioner identifies the collective output of NAND gates G1–GN as
the recited “control signal.” Id. at 41. Figure 4 of Kim shows that the output
of NAND gates G1–GN is connected to the gates of sleep transistors P1–PN
(the recited “control port of the power gating switch”). Ex. 1104, Fig. 4.
Thus, Petitioner asserts that Figure 4 of Kim shows NAND gates G1–GN
“supplying the control signal to a control port of the power gating switch,”
as recited in claim 13. Id. at 42–43.
As discussed above, Patent Owner does not dispute Kim teaches the
limitations of claim 13 discussed in this subsection. See PO Resp. 34–35.
We agree with Petitioner’s analysis and find, based on the complete
record and for the reasons explained by Petitioner, that Petitioner has
demonstrated sufficiently Kim discloses “supplying the control signal to a
control port of the power gating switch,” as recited in claim element 13[F].13
g. Claim Element 13[H]
Turning next to claim element 13[H] which recites “a relationship
between a value of the input supply voltage and a value of the output supply
voltage is responsive to the value of the control signal,” Petitioner references
Annotated Figures 4 and 5 reproduced above and asserts that Kim discloses
NAND gates G1–GN (annotated in red) output a control signal that
selectively turns individual transistors in sleep transistor array P1–PN
(annotated in grey) ON or OFF such that virtual supply voltage VVCC
(annotated in purple) is output to processor 502 (annotated in yellow) at a

13 We also find that Patent Owner has waived any argument directed to this
limitation of claim 13. See Paper 12, 7.
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level different from the level of input supply voltage VCC (annotated in
green). Pet. 48–49 (citing Ex. 1104, Figs. 4, 5, ¶ 16; Ex. 1102 ¶ 88).
Petitioner also cites routine 201 depicted in Figure 2 of Kim and the
description of routine 201 provided in the related text of Kim, as teaching
reducing or decrementing the conductance of the sleep transistor array by
turning ON or OFF one or more sleep transistors in a loop to find a
combination of enabled sleep transistors resulting in satisfactory leakage in a
functional block of Kim’s processor. Id. at 49–51 (citing Ex. 1104, Fig. 2,
claim 8, ¶¶ 10, 16, 18, 19; Ex. 1102 ¶ 90). According to Petitioner, Kim
further discloses that the output of NAND gates G1–GN (the recited “control
signal”) determines multiple voltage differences between VCC (the recited
“input supply voltage”) and VVCC (the recited “output supply voltage”)
because Kim describes, for example,
(1) when the Sleep signal is low, the outputs of the NAND gates
turn OFF every transistor P1-PN, such that VVCC will be lower
than VCC); (2) when the Sleep signal changes from low to high,
the NAND gate outputs (in step 202) turn ON every transistor
P1-PN, such that VCC and VVCC will be as close as possible;
and (3) when there is excessive leakage, the NAND gates turn
ON some sleep transistors and turn others OFF, which will
increase the difference between VCC and VVCC.
Id. at 51 (citing Ex. 1104 ¶¶ 16, 18–20; Ex. 1102 ¶ 91).
To summarize, Petitioner argues that Kim discloses “a relationship
between a value of the input supply voltage and a value of the output supply
voltage is responsive to the value of the control signal,” as recited in
claim 13, because Kim describes that the voltage difference between VCC
(the recited “input supply voltage”) and VVCC (the recited “output supply
voltage”) is determined by the conductance of sleep transistor array, which
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depends on the combination of enable transistors in the array (i.e., which
transistor is ON or OFF), which, in turn, depends on the value of the output
of NAND gates G1–GN (the recited “control signal”). Id. at 48–52.
As discussed above, Patent Owner does not dispute Kim teaches the
limitations of claim 13 discussed in this subsection. See PO Resp. 34–35.
We agree with Petitioner’s analysis and find, based on the complete
record and for the reasons explained by Petitioner, that Petitioner has
demonstrated sufficiently Kim discloses “a relationship between a value of
the input supply voltage and a value of the output supply voltage is
responsive to the value of the control signal,” as recited in claim element
13[H].14
h. Conclusion on Claim 13
Based on the complete record and the foregoing discussion of the
arguments and evidence presented by Petitioner and Patent Owner, we
determine that Petitioner has demonstrated sufficiently that Kim discloses all
limitations recited in claim 13. Accordingly, based on the complete record,
we determine that Petitioner has demonstrated, by a preponderance of the
evidence, that claim 13 is unpatentable under 35 U.S.C. § 102 as anticipated
by Kim.
4. Dependent Claim 14
Claim 14 depends from claim 13 and further recites
selecting a performance value of the control signal when (i) the
leakage indicator indicates that a leakage of the power gated
circuit is below a low leakage threshold and (ii) the mode

14 We also find that Patent Owner has waived any argument directed to this
limitation of claim 13. See Paper 12, 7.
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indicator indicates that the power gated circuit is requested to
operate at a performance oriented mode;
selecting a leakage reduction value of the control signal when
(i) the leakage indicator indicates that the leakage of the
power gated circuit is above the low leakage threshold and
(ii) the mode indicator indicates that the power gated circuit
is requested to operate at the performance oriented mode; and
selecting a shut down value of the control signal when the mode
indicator indicates that the power gated circuit should be shut
down.
Ex. 1101, 16:58–17:6.
Petitioner contends that Kim discloses the additionally recited
limitations of claim 14. Pet. 52–57. As discussed above in Section III.C.3,
Petitioner asserts that Kim discloses that the value of the collective output of
NAND gates G1–GN (the recited “control signal”) is selected based on the
Sleep signal (the recited “mode indicator”) and on the output of memory
cells C1–CN (the recited “leakage indicator”). Id. at 41. Addressing the
additionally recited limitations of claim 14, Petitioner contends that Kim
also discloses selecting various values of the control signal as recited in
claim 14, based on various conditions indicated by the “leakage indicator”
and the “mode indicator.” Id. at 52–57.
As an initial matter, Dr. Harris illustrates exemplary values for the
outputs of Kim’s NAND gates G1–GN for the case of N=5, i.e., when there
are 5 NAND gates in Kim’s chip 100, by providing a table in his
Declaration.
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Table A, provided by Dr. Harris in paragraph 94 of his Declaration, is
reproduced below.

Ex. 1102 ¶ 94 (Table A). Table A, provided by Dr. Harris, illustrates
various values of the collective output of Kim’s NAND gates G1–G5 during
various modes of Kim’s processor or chip. Id.; see also Pet. 52 (citing
Ex. 1102 ¶¶ 93–97).
In his Declaration, Dr. Harris explains that
As shown in Table A, during Kim’s sleep mode, all of the NAND
gates output a High, or digital “1” signal. . . . This turns OFF all
of Kim’s transistors P1-PN during sleep mode. Other values of
Kim’s NAND gates outputs, i.e., when at least one of the NAND
gates outputs a Low, or digital “0” signal, correspond to Kim’s
active mode. . . . When at least one of the NAND gates outputs
a Low, then at least one of the transistors P1-PN are ON,
providing a conduction path between the input supply voltage
VCC and the virtual supply voltage VVCC.
Ex. 1102 ¶ 95 (citing Ex. 1104 ¶ 16).
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As discussed above in our overview of Kim (Section III.C.2.) and also
discussed in the Petition, Kim teaches determining suitable combinations of
transistors in the sleep transistor array by executing routine 201 during a test
phase of manufacturing. See Ex. 1104 ¶¶ 20, 22; see also Pet. 21 (citing
Ex. 1104 ¶¶ 14, 20, 22). Petitioner asserts that Kim also teaches using the
configuration information determined from the testing phase (stored in a
register) during an active state of normal operation to “determine which of
NAND gates G1-GN output low or high signals, which in turn determines
which sleep transistors P1-PN are ON and OFF.” Pet. 21–22 (citing
Ex. 1104 ¶ 16; Ex. 1102 ¶ 54).
Addressing the recitation “selecting a performance value of the
control signal when (i) the leakage indicator indicates that a leakage of the
power gated circuit is below a low leakage threshold and (ii) the mode
indicator indicates that the power gated circuit is requested to operate at a
performance oriented mode,” Petitioner asserts that Kim’s testing operation
when the chip under testing is found to not have excessive leakage prior to
testing and subsequent normal operation during an active mode using such
test results discloses these limitations. Id. at 53–54 (citing Ex. 1104 ¶¶ 16,
18; Ex. 1102 ¶¶ 98–100). First, Petitioner argues that because Kim’s
routine 201 starts with turning ON all sleep transistors P1–PN, if
processor 502 is found to not have excessive leakage at the very first
execution of Kim’s step 206, the output from cells C1–CN would have the
value of all ones (1s) after completion of routine 201. Id. at 53 (citing
Ex. 1104 ¶¶ 16, 18; Ex. 1102 ¶ 98); see also id. at 38 (describing the same
cell value determination). In other words, according to Petitioner and
Dr. Harris, Kim discloses that if the leakage level of the chip (the recited
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“power gated circuit”), as found, is determined to be not excessive (i.e.,
“below a low leakage threshold” as recited in the claim) during testing,
Kim’s memory cell value determined at the end of testing would be all
ones (1s). See id. at 38, 53; Ex. 1102 ¶ 98.
Dr. Harris further explains that Kim describes that when this stored
value is used to drive the output of memory cells C1–CN (the “leakage
indicator” indicating “a leakage of the power gated circuit is below a low
leakage threshold” as recited in the claim) during an active mode of normal
operation, i.e., when the Sleep signal (the recited “mode indicator”) is High
during normal operation, the value of the output of NAND gates G1–GN
would be all zeroes (0s) (i.e., selecting the “value of the control signal”),
causing all of the sleep array transistors to be turned ON. Ex. 1102 ¶ 99.
This in turn would cause the sleep transistor array (the recited “power gating
switch”) to have maximum conductance and supply a highest output voltage
(VCC or close to VCC) to the chip or the processor, allowing the processor
to have the highest speed. See Pet. 50–51 (citing Ex. 1104 ¶ 18); Ex. 1102
¶¶ 90, 97. Thus, Petitioner argues Kim’s all zeroes (0s) output of NAND
gates G1–GN discloses “a performance value of the control signal” recited
in claim 14. Pet. 53–54 (citing Ex. 1102 ¶¶ 99–100). Petitioner argues Kim,
therefore, discloses “selecting a performance value of the control signal
when (i) the leakage indicator indicates that a leakage of the power gated
circuit is below a low leakage threshold and (ii) the mode indicator indicates
that the power gated circuit is requested to operate at a performance oriented
mode,” as recited in claim 14. Id. at 52–54.
Petitioner presents similar arguments and evidence in its contention
that Kim discloses “selecting a leakage reduction value of the control signal
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when (i) the leakage indicator indicates that the leakage of the power gated
circuit is above the low leakage threshold and (ii) the mode indicator
indicates that the power gated circuit is requested to operate at the
performance oriented mode,” as recited in claim 14, except that Petitioner
relies on Kim’s testing that results in the output of memory cells C1–CN
having some zeroes (0s) because the chip tested, as found, was determined
to have a leakage level that is excessive, i.e., “above the low leakage
threshold,” as recited in claim 14. Id. at 54–56 (citing Ex. 1104 ¶¶ 16–20;
Ex. 1102 ¶¶ 101–103).
Similar to our discussion above, Petitioner asserts that when Kim’s
testing-determined memory cell value having some 0s is used to drive the
NAND gates G1–GN during an active mode of normal operation (i.e., when
the Sleep signal is High), the NAND gates turn some sleep transistors ON
and turn others OFF, which will decrease the conductance of the sleep
transistor array and increase the difference between VCC and VVCC. Id. at
50–51 (citing Ex. 1104 ¶¶ 16, 18–20; Ex. 1102 ¶ 91), 54–56 (citing Ex. 1104
¶¶ 16–20; Ex. 1102 ¶¶ 102–103). Thus, Petitioner argues the value of the
output of NAND gates G1–GN with some zeroes (0s) and some ones (1s)
discloses “a leakage reduction value of the control signal” recited in
claim 14. Id. at 54–56. Petitioner asserts, therefore, Kim’s NAND gates
G1–GN “select a leakage reduction value of the control signal when (i) the
leakage indicator indicates that the leakage of the power gated circuit is
above the low leakage threshold and (ii) the mode indicator indicates that the
power gated circuit is requested to operate at the performance oriented
mode,” as recited in claim 14. Id.
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Addressing the recitation “selecting a shut down value of the control
signal when the mode indicator indicates that the power gated circuit should
be shut down,” Petitioner asserts that Kim discloses this limitation when
Kim’s Sleep signal is Low during the sleep mode of normal operation. Id. at
56–57 (citing Ex. 1104 ¶¶ 9, 16; Ex. 1102 ¶¶ 104–105). Petitioner contends
Kim teaches that “when the Sleep signal is asserted (Low) . . ., the NAND
gates G1 to GN all output a High” (id. at 56 (citing Ex. 1104 ¶ 16)) and that
“that value of the NAND gates turns OFF all of the PMOS transistors and
shuts down the function blocks of processor 502” (id. (citing Ex. 1104 ¶¶ 9,
16)). Petitioner argues that an output of all ones (1s) from NAND gates G1–
GN is therefore a “shut down value of the control signal,” as recited in
claim 14, because it turns OFF the array of sleep transistors and disconnects
the processor from the supply voltage VCC. Id. at 56–57 (citing Ex. 1102
¶¶ 118–119).
Patent Owner makes several arguments disputing Petitioner’s
contentions. PO Resp. 35–54; PO Sur-reply 10–15.
First, Patent Owner asserts that claim 14 recites selecting by a control
circuit at least three different types of control signal values—“a performance
value,” “a leakage reduction value,” and “a shutdown value.” PO Resp. 36.
Patent Owner contends that Kim’s NAND gates G1–GN (the clamed
“control circuit”), however, can output at most two values (the claimed
“value of the control signal”) during the entire product life of Kim’s
processors because Kim’s NAND gates output either all 1s (when the Sleep
signal is 0) or the bit pattern (or its complement) stored in Kim’s memory
cell C1–C2, which has a fixed value determined during the testing phase. Id.
at 36–39 (citing Ex. 1104 ¶¶ 16, 20, 22; Ex. 2009 ¶ 93).
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Petitioner responds by citing the disclosures in the Specification of the
’026 patent that describe the same or similar method of determining a fixed
value of the leakage indicator during testing, which is thereafter used during
the normal operation. Pet. Reply 13–14 (citing Pet. 38; Ex. 1101, 3:61–67).
Petitioner reproduces the relevant passage as follows.
The leakage indicator generator 45 can include, for example:
fuses, one time programmable element or other programmable
elements that can be programmed to reflect the determined
leakage. The leakage indicator 105 can, for example, indicate
whether the integrated circuit 10 has a leakage level that
corresponds to a best process case, typical process case or worst
process case.
Id. at 13 (quoting Ex. 1101, 3:61–67). Petitioner argues that in the
’026 patent, just as in Kim,
In any particular instance of such a device, that single fixed value
of the leakage indicator will result in the control circuit selecting
either the performance value of the control signal or the leakage
reduction value of the control signal, but not both (the control
circuit would also select the shut down value of the control signal
when the mode indicator indicated a shut down mode).
Id. at 13–14 (second emphasis added) (citing Ex. 1130 ¶¶ 39–40). Petitioner
argues, therefore, claim 14 does not require “a particular control circuit (e.g.,
a particular instance of a manufactured circuit) to select both a performance
value of the control signal and a leakage reduction value.” Id. at 12.
Patent Owner responds that, if the embodiment of the ’026 patent
cited by Petitioner describes “control circuits that select only one of a
performance value or a leakage reduction value during the entire device life,
then those examples would also fall outside the claim scope.” PO Sur-reply
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11–12 (citing Intamin Ltd. v. Magnetar Techs., Corp., 483 F.3d 1328, 1336–
37 (Fed. Cir. 2007)).
We disagree with Patent Owner that Kim must perform all three steps
in order to satisfy the limitations of claim 14. The selecting steps recited in
claim 14 are subject to the conditions recited in the claim. That is, claim 14
recites “selecting a performance value of the control signal when (i) the
leakage indicator indicates that a leakage of the power gated circuit is below
a low leakage threshold and (ii) the mode indicator indicates that the power
gated circuit is requested to operate at a performance oriented mode,”
“selecting a leakage reduction value of the control signal when (i) the
leakage indicator indicates that the leakage of the power gated circuit is
above the low leakage threshold and (ii) the mode indicator indicates that the
power gated circuit is requested to operate at the performance oriented
mode,” and “selecting a shut down value of the control signal when the
mode indicator indicates that the power gated circuit should be shut down.”
Ex. 1101, 16:59–17:6 (emphases added). In other words, the claim language
indicates that the selecting steps recited in claim 14 are conditional or
contingent steps that are performed only when the recited conditions are met.
If the recited conditions are not met, the selecting steps need not be
performed. This interpretation of claim 14 is consistent with the
Specification, which describes as follows:
[T]he control circuit 50 may select the performance value of the
control signal 103 when the leakage indicator 105 indicates that
the integrated circuit 10 is slow (and hence exhibit less leakage)
in comparison to most integrated circuits of a batch of integrated
circuits that includes the integrated circuit 10. Similarly, the
control circuit 50 may select the leakage reduction value of the
control signal 103 when the leakage indicator 105 indicates that
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the integrated circuit 10 is fast (and hence has high leakage) in
comparison to most integrated circuits of a batch of integrated
circuits that includes the integrated circuit 10.
Ex. 1101, 4:59–5:2 (emphases added). Thus, the claim language and the
Specification indicate that the selecting steps recited in claim 14 are
performed only when the recited conditions are met. This interpretation of
claim 14 is consistent with the embodiment cited by Petitioner, where the
leakage level of the gated circuit is measured during testing or
manufacturing and then used as a leakage indicator to control the leakage
during the normal operation of the circuit. See Pet. Reply 13–17 (citing Pet.
38; Ex. 1101, 3:61–67).
A “claim interpretation that excludes a preferred embodiment from
the scope of the claim is rarely, if ever, correct.” Network-1 Techs., Inc. v.
Hewlett-Packard Co., 981 F.3d 1015, 1024 (Fed. Cir. 2020) (quoting MBO
Labs., Inc. v. Becton, Dickinson & Co., 474 F.3d 1323, 1333 (Fed. Cir.
2007)); see also GE Lighting Sols., LLC v. AgiLight, Inc., 750 F.3d 1304,
1311 (Fed. Cir. 2014) (“[W]here claims can reasonably [be] interpreted to
include a specific embodiment, it is incorrect to construe the claims to
exclude that embodiment, absent probative evidence on the contrary.”
(quoting Oatey Co. v. IPS Corp., 514 F.3d 1271, 1277 (Fed. Cir. 2008)).
Here, Patent Owner does not point to any intrinsic evidence, such as express
claim language, or statements made during prosecution or in the
Specification that indicate the patentee’s intent to exclude the disclosed
embodiment from the scope of claim 14.
In view of the claim language and the Specification, we interpret the
selecting steps recited in claim 14 as conditional or contingent steps that are
performed only when the recited conditions are met. We find, therefore,
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claim 14 does not require all three recited steps be performed by a control
circuit for Kim to anticipate. See Cybersettle, Inc. v. Nat’l Arbitration
Forum, Inc., 243 Fed. Appx. 603, 607 (Fed. Cir. 2007) (nonprecedential) (“It
is of course true that method steps may be contingent. If the condition for
performing a contingent step is not satisfied, the performance recited by the
step need not be carried out in order for the claimed method to be
performed.”); cf. Ex Parte Schulhauser, 2016 WL 6277792, at *3 (PTAB
Apr. 28, 2016) (precedential) (determining that under the broadest
reasonable interpretation standard that conditional steps of the method claim
did not need to be performed “if the condition precedent recited in the claim
is not met”).
Thus, we find that Kim discloses the additionally recited limitations of
claim 14.
Next, Patent Owner argues that the bit patterns stored in Kim’s
memory cells are merely passed through the NAND gates (PO Resp. 36–37,
PO Sur-reply 16) and Kim therefore does not teach the selections recited in
claim 14 because “such pass-through does not involve ‘choos[ing] or
pick[ing] out [a control signal value] in preference to another or others’ by
the control circuit based on the leakage indicator” (PO Sur-reply 12–13).
We disagree with Patent Owner’s argument for the reasons discussed
above in Section III.C.3(e). As discussed in the same section, when the
sleep signal (the claimed “mode indicator”) is 0, Kim’s NAND gates choose
the output to be a signal of all 1s (the claimed “value of the control signal”)
in preference to another value, e.g., the value determined by the output of the
memory cells C1–CN. When, on the other hand, the sleep signal is 1, the
NAND gates choose the output to be a signal of the complement of the
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output of the memory cells C1–CN (the claimed “leakage indicator”), as
opposed to another value, e.g., all 1s. Thus, Kim’s NAND gates select the
value of the control signal based on the mode indicator and on the leakage
indicator even under Patent Owner’s proposed construction of “select.”
Kim also teaches the limitations of claim 14 under the modified IEEE
dictionary definition discussed above—“identify[ing]” or picking “an item”
that “meets a particular criterion.” Based on the evidence presented by
Petitioner, Kim’s NAND gates identify or pick (or determine) the output
value of all 0s (the claimed “performance value of the control signal”) when
the following criteria or conditions are met: (i) Kim’s memory cells C1–CN
(the claimed “leakage indicator”) have the value of all 1s, indicating the
leakage of the functional blocks of processor 502 is below a leakage
threshold (as determined at the end of testing and saved in the cells or
register) and (ii) the Sleep signal (the claimed “mode indicator”) is High,
indicating the active mode (the claimed “performance oriented mode). See
Pet. 52– 54 (citing Ex. 1104 ¶¶ 16, 18; Ex. 1102 ¶¶ 98–100). Kim’s NAND
gates also identify or pick the output value of some 0s (the claimed “leakage
reduction value of the control signal”) when the following criteria or
conditions are met: (i) Kim’s memory cells C1–CN (the claimed “leakage
indicator”) have the value of some 1s, indicating the leakage of the
functional blocks of processor 502 is above a leakage threshold (ii) the Sleep
signal is High, indicating the active mode (the claimed “performance
oriented mode). See id. at 54–56 (citing Ex. 1104 ¶¶ 16–20, Ex. 1102
¶¶ 101–103). In addition, Kim’s NAND gates identify or pick the output
value of all 1s (the claimed “shut down value of the control signal”) when
the following criterion or condition is met: the Sleep signal (the claimed
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“mode indicator”) is Low, indicating the function blocks of processor 502 is
to be shut down. See id. at 56–57 (citing Ex. 1104 ¶¶ 9, 16; Ex. 1102
¶¶ 104–105).
Based on the foregoing and considering the complete record, we find
that Petitioner has demonstrated sufficiently Kim teaches the additionally
recited limitations of claim 14. Accordingly, based on the complete record,
we determine that Petitioner has demonstrated, by a preponderance of the
evidence, that claim 14 is unpatentable under 35 U.S.C. § 102 as anticipated
by Kim.
D. Obviousness over Kim and Lee
In this asserted ground of obviousness, Petitioner contends that
claims 17, 18, and 20 are unpatentable under 35 U.S.C. § 103(a) over the
combination of Kim and Lee. Pet. 57–79.
1. Relevant Principles of Law
A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
between the claimed subject matter and the prior art are such that the subject
matter, as a whole, would have been obvious at the time the invention was
made to a person having ordinary skill in the art to which the subject matter
pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The
question of obviousness is resolved on the basis of underlying factual
determinations, including: (1) the scope and content of the prior art; (2) any
differences between the claimed subject matter and the prior art; (3) the level
of skill in the art; and (4) where in evidence, so-called secondary
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considerations.15 Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
We analyze the asserted ground based on obviousness with the principles
identified above in mind.
2. Overview of Lee (Ex. 1105)
Lee describes a standby leakage current reduction circuit and a
semiconductor memory device comprising the standby leakage current
reduction circuit. Ex. 1105, code (57).
Figure 4 of Lee is reproduced below.

Figure 4 schematically illustrates an exemplary semiconductor memory
device that comprises an exemplary standby leakage current reduction
circuit. Ex. 1105 ¶ 50.

15 The parties do not address secondary considerations, which therefore do
not constitute part of our analysis.
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As shown in Figure 4, standby leakage current reduction circuit 48
includes deep power down setting unit 45, temperature information
generator 42, bias signal generator 40, and internal voltage regulator 41. Id.
¶ 51. As illustrated in Figure 4, Lee’s Bias signal generator 40 controls the
output supply voltage provided by virtual ground controller VC_1 based on
several inputs, such as input from temperature sensor 42, process
information generator 43, and deep power down (DPD) indicator 45 (blue),
which provides an input that indicates whether the memory cells are in a
deep power down mode. Id. ¶¶ 57, 71, 81, 86, 133, 152.
Lee describes that the bias signal is an analog signal applied to the
NMOS sleep transistors (e.g., NM1 to NMn) that modifies the virtual ground
for the NMOS transistors, which changes the conductivity (or the
operational resistance) of the sleep transistors. See id. ¶¶ 22, 52, 61.
Lee describes that deep power down setting unit 45 may set a deep
power down mode of the semiconductor memory device. Id. ¶ 57. Lee
further describes that when the semiconductor memory device is in an active
mode or a standby mode, deep power down signal DPD has a logic low level
and that when the semiconductor memory device is in the deep power down
mode, deep power down signal DPD has a logic high level. Id. ¶ 71.
3. Dependent Claims 17 and 20
Claims 17 and 20 depend directly or indirectly from claim 14 and
each further recites selecting the leakage reduction value (claim 17) or the
retention value (claim 12) “based on a temperature of the integrated circuit
and on the leakage indicator.” Ex. 1101, 18:5–8 (claim 17), 18:16–19
(claim 20). For both of these claims, Petitioner relies on Lee to teach using
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temperature as a stimulus for selecting the value of a control signal. Pet. 58–
68 (claim 17), 73–79 (claim 20).
Figure 4 of Lee, as annotated by Petitioner in different colors, is
reproduced below.

Pet. 59. Annotated Figure 4 of Lee reproduced above shows Petitioner’s
identification of various circuits or circuit components of Lee’s standby
leakage current reduction circuit. Id. at 58–59 (citing Ex. 1105 ¶ 50, Fig. 4).
Petitioner asserts that Lee uses a virtual ground controller comprising
NMOS transistors NM1 to NMn (annotated in grey) to control the level of a
virtual ground Vgnd1 (annotated in purple) for memory cells (annotated in
yellow). Pet. 59. According to Petitioner, Lee’s bias signal generator
(annotated in red) adjusts the signal BIAS (annotated in magenta) to
determine the conductivity of NMOS transistors NM1–NMn, which in turn
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control the voltage apparent applied to the memory cells. Id. at 59–60
(citing Ex. 1105 ¶¶ 54, 58, 61, 65; Ex. 1102 ¶ 109). Petitioner contends that
Lee’s bias signal generator (red) sets the BIAS signal (and thereby
determines the conductivity of the ground controller, i.e., the NMOS
transistor array) based on multiple information sources including
temperature information generator 42 (annotated in pink). Id. at 60–61
(citing Ex. 1105 ¶¶ 50–57, Fig. 4).
Petitioner asserts that it would have been obvious to a person of
ordinary skill in the art to “use in Kim the technique of Lee of selecting the
control signal based on temperature.” Pet. 63 (citing Ex. 1104, Fig. 4;
Ex. 1105, Fig. 4). According to Petitioner, “Lee . . . uses temperature as a
stimulus to compensate for such temperature induced changes by adjusting
its control signal (BIAS).” Id. (emphasis added) (citing Ex. 1105, Fig. 4,
¶ 54). Petitioner contends that it would have been obvious and beneficial to
use temperature, as taught by Lee, to provide increased control of the level
of Kim’s virtual supply voltage VVCC. Id. at 63–64 (citing Ex. 1104 ¶ 22;
Ex. 1105, Fig. 4, ¶ 54).
Patent Owner contends that, in order to show obviousness, “Petitioner
must point to specific disclosures in prior art for material limitations to avoid
hindsight bias and to ensure that obviousness analysis is specific to the
claims at issue” and argues that Petitioner’s reliance on a broad concept of
“incorporat[ing] a temperature factor” from Lee is insufficient to
demonstrate unpatentability of claim 4. See PO Resp. 55–56 (citing Arendi
S.A.R.L. v. Apple Inc., 832 F.3d 1355, 1365–66 (Fed. Cir. 2016) and
characterizing Arendi’s finding as “while prior art supports the broader
notion of searching for data in a database, [p]etitioner has failed to show
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why it would be common sense for the ‘Add to address book’ function to
operate by search for phone numbers as claimed” (emphasis added) (internal
quotation marks omitted)). Patent Owner further asserts that “obviousness
requires a showing of a specific reason to combine and not what could be
done generally in the abstract.” PO Sur-reply 17 (emphasis added) (citing
ActiveVideo Networks, Inc. v. Verizon Commc’ns, Inc., 694 F.3d 1312, 1328
(Fed. Cir. 2012)). Based on the complete record, we understand Patent
Owner to argue that relying on Lee as the source of what was well-known in
the prior art—the general concept of using temperature to modify a control
signal—is insufficient and that Petitioner instead must identify specific
teachings of Lee it relies on in order to demonstrate obviousness based on
Lee and Kim in this case.
We agree with Patent Owner that relying on Lee only for the generally
well-known concept of using temperature is insufficient to demonstrate
obviousness of claims 17 and 20 under the facts and circumstances of this
case. See Arendi, 832 F.3d at 1363 (“In cases in which ‘common sense’ [or
general knowledge in the art] is used to supply a missing limitation, as
distinct from a motivation to combine . . . our search for a reasoned basis for
resort to common sense must be searching.” (emphases added)). In Arendi,
the Federal Circuit found that a common sense or general knowledge in the
art may not provide a limitation missing from the prior art when the
limitation at issue “plays a major role in the subject matter claimed,” rather
than, “the limitation in question [is] unusually simple and the technology
particularly straightforward.” Id. at 1362. In this case, we find that selecting
the leakage reduction value or the retention value of the control signal
“based on a temperature of the integrated circuit,” as recited in claims 17 or
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20 “plays a major role” in the subject matter claimed by these claims. In
addition, as demonstrated below by Petitioner’s proposed modifications to
Kim to incorporate teachings of Lee, the technology at issue here is far from
“straightforward,” but, rather, highly complex. Under the particular facts
and circumstances of this case, we determine that relying on Lee only for the
generally well-known concept of using temperature is insufficient to
demonstrate obviousness of claims 17 and 20.
Petitioner asserts that it relies on “[i]ncorporating Lee’s teaching of
adjusting a power gate supply” (Pet. 64), i.e., Lee’s teaching of adjusting its
“control signal (BIAS)” to adjust the conductivity of Lee’s sleep transistors
NM1–NMn (id. at 63 (citing Ex. 1105, Fig. 4, ¶ 54)). Petitioner further
contends that “the Petition provides examples of how a combined system of
Lee and Kim would have been designed.” Pet. Reply 22 (citing Pet. 57–68;
Ex. 1102 ¶¶ 106–122). In the cited portion of the Petition, Petitioner relies
on the testimony of Dr. Harris and explains how Petitioner proposes to
combine specific teachings of Lee with Kim. See Pet. 65–66 (citing
Ex. 1102 ¶¶ 116–120). Specifically, Petitioner contends that a person of
ordinary skill in the art would have understood that
to account for temperature in Kim’s system, Kim would have
been modified, for example, to: 1) store values in registers C1
to CN using Kim’s Figure 2 method at various temperatures,
and 2) select from the stored values based on the “stimulus” of
a detected temperature during operation as taught by Lee.
Pet. 65–66 (emphasis added) (citing Ex. 1102 ¶¶ 116–120). In his
Declaration, Dr. Harris illustrates an example of such modification of Kim
using a modified Figure 4 of Kim, which he labels as Figure A. Ex. 1102
¶ 116.
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Figure A presented by Dr. Harris in his Declaration is reproduced
below.

Ex. 1102 ¶ 116. Figure A reproduced above shows Dr. Harris’s proposed
modification to Figure 4 of Kim to incorporate into Kim Lee’s teaching of
altering the control signal based on temperature. Id.
Referencing Figure A, Dr. Harris proposes modifying the circuit of
Kim’s Figure 4 (including an array of sleep transistors P1 to PN, NAND
gates G1–GN, and memory cells C1–CN) by replacing memory cells C1–
CN with cells C1h–C4h (red) and C1c–C4c (blue), adding multiplexors M
between the NAND gates G1–GN and the memory cells, and adding a
temperature indicator line. Ex. 1102 ¶ 117. According to Dr. Harris, this
modification would have allowed changing the output of the NAND gates
G1–GN (i.e., the claimed “control signal”), turning different sleep transistors
P1–PN on or off, based on the temperature indicator. Id.
We are not persuaded by Petitioner’s argument and evidence. First,
although Petitioner proposes “[s]ubstituting Lee’s inputs of leakage current
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and temperature for generating a power gate control signal” (i.e., Lee’s
“control signal (BIAS)”) for “Kim’s inputs of leakage current and other
‘stimuli’ for generating a power gate control signal” (Pet. 64 (citing
Ex. 1102 ¶ 115)), neither Petitioner nor Dr. Harris explains adequately how
they are proposing to “substitute” Kim’s control signal with Lee’s “control
signal (BIAS).”
For example, Figure A reproduced above does not show how
Petitioner or Dr. Harris proposes to use Lee’s “control signal (BIAS)” in the
proposed combination. Petitioner asserts that “[a]lthough Lee’s control
signal is analog and Kim’s control signal is digital, it was well known to
apply teachings in an analog domain to a digital domain, and conversions
between analog and digital domains were easy to implement.” Pet. 66
(emphases added) (citing Ex. 1102 ¶ 121; Ex. 1115). Dr. Harris similarly
states that
Figures A and B show examples of obvious ways to use in Kim’s
system Lee’s teaching of setting conductance of the array based
on temperature. A POSA would have found both of these ways
obvious. That Lee uses an analog control signal and Kim uses a
digital control signal would have presented no obstacle to a
POSA. . . . That is, converting analog circuit elements and
signals to digital was well known long before the ’026 patent.
Ex. 1102 ¶ 121 (emphases added) (citing (Ex. 1115) (“Analog-to-digital
converters (ADC’s) are ubiquitous, critical components of software radio
and other signal processing systems.”)). But Dr. Harris does not explain
adequately how “to use in Kim’s system” the digitized BIAS signal of Lee.
See id. The only additional input signal shown in Figure A compared to
Figure 4 of Kim is the temperature line that has the value of 0 when the
temperature is cold and the value of 1 when the temperature is hot. See
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Ex. 1102 ¶ 116 (Fig. A). There is no explanation of how the modified
teaching of the BIAS signal of Lee (i.e., modified or converted to a digital
signal) would have worked in the proposed combination of Figure A.
Nor does Petitioner explain adequately how the digitized BIAS signal
of Lee would have been applied to the circuit of Kim to arrive at the subject
matter recited in claim 17 and claim 20. See Pet. 63–68; Ex. 1102 ¶ 121.
Cf. Pers. Web Techs., LLC v. Apple, Inc., 848 F.3d 987, 994 (Fed. Cir. 2017)
(“[T]he Board nowhere clearly explained, or cited evidence showing, how
the combination of the two references was supposed to work. At least in this
case, such a clear, evidence-supported account of the contemplated workings
of the combination is a prerequisite to adequately explaining and supporting
a conclusion that a relevant skilled artisan would have been motivated to
make the combination and reasonably expect success in doing so.”
(emphases added)).
According to the Federal Circuit,
The amount of explanation needed to meet the governing
legal standards—to enable judicial review and to avoid judicial
displacement of agency authority—necessarily depends on
context. A brief explanation may do all that is needed if, for
example, the technology is simple and familiar and the prior art
is clear in its language and easily understood. On the other hand,
complexity or obscurity of the technology or prior-art
descriptions may well make more detailed explanations
necessary.
Id. (internal citation omitted). We find that this case falls into the latter
category. Given the level of ordinary skill proposed by Petitioner, the
complexity of the operation and design of the circuits of Kim and Lee, it was
incumbent upon Petitioner to explain sufficiently how Lee’s method of
applying the analog BIAS signal to the NMOS sleep transistors to change
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the conductivity of the sleep transistor array would have been adapted and
combined with Kim’s method of controlling the conductivity of the sleep
transistor array by digitally turning on or off each of the sleep transistor P1
to PN to arrive at the subject matter recited in claims 17 and 20.16 Because
Petitioner has failed to do so, we determine that Petitioner has not
established sufficiently that a person of ordinary skill in the art would have
been motivated to combine the teachings of Kim and Lee to achieve the
claimed invention.
Accordingly, for the foregoing reasons and based on the complete
record, we determine Petitioner does not demonstrate by a preponderance of
the evidence that the subject matter of claim 17 and claim 20 would have
been obvious over the proposed combination of Kim and Lee.
4. Dependent Claim 18
Claim 18 depends from claim 14 and further recites “selecting a
retention value of the control signal when the mode indicator indicates that
the power gated circuit is requested to enter a retention mode.” Ex. 1101,
18:9–12.
Similar to Petitioner’s contentions on claims 17 and 20 discussed
above, Petitioner relies on the combination of Lee and Kim to argue
obviousness of claim 18 (Pet. 68–73) except that, for claim 18, Petitioner
relies on the standby mode of Lee to teach the “retention mode” recited in
claim 18. Id. at 68–69. According to Petitioner, in Lee’s standby mode, the
transistors NM1–NMn operate in the transistor’s active region and the level

16 To be clear, we are not requiring Petitioner to explain a bodily
incorporation of Lee in Kim; rather, our focus is on Petitioner’s lack of
explanation as to how the teachings would have been combined.
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of the BIAS signal determines the level of the virtual ground Vgnd1. Id. at
69 (citing Ex. 1105 ¶¶ 60–61, 65).
Again, in its proposed combination of Lee and Kim, Petitioner
proposes modifying Kim’s circuits driving the NAND gates rather than
applying the BIAS signal directly to Kim’s sleep transistors. Pet. 72–73;
Ex. 1102 ¶ 129 (presenting Fig. C). Neither Petitioner nor Dr. Harris
explains adequately why a person of ordinary skill in the art would have
modified Kim’s circuit as proposed, instead of applying the BIAS signal
directly to Kim’s sleep transistors. Nor do they explain sufficiently how
Lee’s method of applying the analog BIAS signal to the NMOS sleep
transistors to change the conductivity of the sleep transistor array would
have been adapted and combined with Kim’s method of controlling the
conductivity of the sleep transistor array by digitally turning on or off each
of the sleep transistor P1 to PN to arrive at the subject matter recited in
claim 18. Thus, for the same reasons discussed above with respect to
claims 17 and 20, Petitioner does not explain adequately why a person of
ordinary skill in the art would have been motivated to combine Kim and Lee
in the manner proposed by Petitioner to arrive at the subject matter of
claim 18.17
Accordingly, based on the complete record, we determine Petitioner
does not demonstrate by a preponderance of the evidence that the subject
matter of claim 18 would have been obvious over the proposed combination
of Kim and Lee.

17 We do not require Petitioner to explain a bodily incorporation of Lee in
Kim; rather, our focus is on Petitioner’s lack of explanation as to how the
teachings would have been combined.
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IV. CONCLUSION
For the foregoing reasons, we conclude that Petitioner has met its
burden of proof, by a preponderance of the evidence, in showing that
claims 13 and 14 of the ’026 patent are unpatentable.18 For the reasons
discussed above, Petitioner has not demonstrated, by a preponderance of the
evidence, claims 17, 18, and 20 of the ’026 patent are unpatentable. The
chart below summarizes our conclusions.
Claims 35 U.S.C. § References/Basis
Claims
Shown
Unpatentable
Claims
Not Shown
Unpatentable
13, 14 102 Kim 13, 14
17, 18, 20 103(a) Kim, Lee 17, 18, 20
Overall
Outcome 13, 14 17, 18, 20

V. ORDER
In consideration of the foregoing, it is hereby:
ORDERED that claims 13 and 14 of the ’026 patent are determined to
be unpatentable;

18 Should Patent Owner wish to pursue amendment of claims 13 and 14 in a
reissue or reexamination proceeding subsequent to the issuance of this
Decision, we draw Patent Owner’s attention to the April 2019 Notice
Regarding Options for Amendments by Patent Owner Through Reissue or
Reexamination During a Pending AIA Trial Proceeding. See 84 Fed. Reg.
16,654 (Apr. 22, 2019). If Patent Owner chooses to file a reissue application
or a request for reexamination of the challenged patent, we remind Patent
Owner of its continuing obligation to notify the Board of any such related
matters in updated mandatory notices. See 37 C.F.R. § 42.8(a)(3), (b)(2).
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FURTHER ORDERED that claims 17, 18, and 20 of the ’026 patent
are not determined to be unpatentable; and
FURTHER ORDERED that pursuant to 35 U.S.C. § 314(c) and
37 C.F.R. § 42.4, notice is hereby given of the institution of a trial, the trial
commencing on the entry date of this Decision.

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76
PETITIONER:
Richard Goldenberg
Dominic Massa
Yvonne Lee
Dan Williams
WILMER CUTLER PICKERING HALE AND DORR LLP
Richard.goldenberg@wilmerhale.com
Dominic.massa@wilmerhale.com
Yvonne.lee@wilmerhale.com
Daniel.williams@wilmerhale.com

PATENT OWNER:
Hong Zhong
Benjamin Hattenback
IRELL & MANELLA LLP
hzhong@irell.com
bhattenbach@irell.com