Viren Khandekar et al.

Patent Trials and Appeals Board

Aug 2, 2019

14959537 - (D) (P.T.A.B. Aug. 2, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/959,537 12/04/2015 Viren Khandekar 16483.1084USI1/
MAXM1084CP
8199
99900 7590 08/02/2019
Advent/Maxim
The Advent Building
17838 Burke Street
Suite 200
Omaha, NE 68118
EXAMINER
ESKRIDGE, CORY W
ART UNIT PAPER NUMBER
3624
NOTIFICATION DATE DELIVERY MODE
08/02/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
Boumstein@adventip.com
sloma@adventip.com
uspto@adventip.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte VIREN KHANDEKAR, THAMBIDURAI KARTHIK, VIVEK S.
SRIDHARAN, KAYSAR S. RAHIM, and TIAO ZHOU
____________

Appeal 2018-008577
Application 14/959,537
Technology Center 2800
____________

Before ROMULO H. DELMENDO, RAE LYNN P. GUEST, and
MONTÉ T. SQUIRE, Administrative Patent Judges.

DELMENDO, Administrative Patent Judge.

DECISION ON APPEAL
The Applicant1 (“Appellant”) appeals under 35 U.S.C. § 134(a) from
the Primary Examiner’s final decision to reject claims 1–15.2 We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 The Applicant is “Maxim Integrated Products, Inc.” (Application Data
Sheet filed December 4, 2015, 6), which is also identified as the real party in
interest (Appeal Brief filed May 1, 2018 (“Appeal Br.”), 3).
2 Appeal Br. 9–19; Reply Brief filed August 28, 2018 (“Reply Br.”), 3–7;
Final Office Action entered November 1, 2017 (“Final Act.”), 3–9;
Examiner’s Answer entered June 28, 2018 (“Ans.”), 2–5.
Appeal 2018-008577
Application 14/959,537

2
I. BACKGROUND
The current application is a continuation-in-part of copending
Application 13/287,254 (“’254 Application”) filed November 2, 2011
(Specification filed December 4, 2015 (“Spec.”), ¶ 1). In the ’254
Application, a final decision to reject claims 1, 3–8, and 10–14 was affirmed
by the Board in a Decision on Appeal entered March 1, 2018.
The subject matter on appeal relates to wafer-level chip-scale package
semiconductor devices (id. ¶ 4). Figure 1A (partially annotated), which is
illustrative of the claimed subject matter, is reproduced from the Drawings
filed December 4, 2015, as follows:

Figure 1A above depicts a wafer-level chip-scale package device 100 in
accordance with the invention, wherein the device includes, inter alia: a
first integrated circuit chip 102 including a substrate 104 and one or more
integrated circuits 106; a first bump array 116 including at least one solder
bump 108; a second bump array 118 including at least one solder bump 110,
Appeal 2018-008577
Application 14/959,537

3
which includes a core 112; and a second integrated circuit chip 120 with a
third bump array 124 including multiple solder bumps 122 electrically and
mechanically coupled to the first integrated circuit chip 102 in a “kangaroo”
configuration (id. ¶¶ 23–30).
Representative claim 1 is reproduced from the Claims Appendix to the
Appeal Brief, as follows:
1. A wafer-level chip-scale package device comprising:
a first integrated circuit chip, the first integrated circuit chip
including an integrated circuit;
a first bump array disposed directly on the first integrated circuit
chip, the first bump array including at least one solder
bump;
a second bump array disposed directly on the first integrated
circuit chip, the second bump array including at least one
solder bump having a core, where the second bump array
is configured to provide standoff height; and
a second integrated circuit chip mounted directly to the first
integrated [circuit] chip by a third bump array including
at least one solder bump, the third bump array electrically
coupling the second integrated circuit chip to the first
integrated circuit chip.
(Appeal Br. 20 (emphasis added)).
II. REJECTIONS ON APPEAL
The claims on appeal stand rejected under 35 U.S.C. § 103(a) as
follows:
A. Claims 1–3 and 8–10 as unpatentable over Huang3 and Liu;4
B. Claims 4 and 5 as unpatentable over Huang, Liu, and Meyer;5

3 US 2003/0132519 A1, published July 17, 2003.
4 US 2005/0093153 A1, published May 5, 2005.
5 US 2009/0256256 A1, published October 15, 2009.
Appeal 2018-008577
Application 14/959,537

4
C. Claims 6 and 7 as unpatentable over Huang, Liu, and Jeong;6
D. Claims 14 and 157 as unpatentable over Huang, Liu, and Jeong;
and
E. Claims 11–13 as unpatentable over Huang, Liu, and Meyer.
(Ans. 2–5; Final Act. 3–9).
III. DISCUSSION
Although the Appellant provides arguments under separate headings
for dependent claims 2–7, independent claim 8, and dependent claims 9–15,
the arguments are based on the same arguments offered for claim 1 (Appeal
Br. 14–19).8 Therefore, we confine our discussion to representative claim 1.
37 C.F.R. § 41.37(c)(1)(iv).

6 US 2005/0087885A1, published April 28, 2005.
7 The statement of the rejection lists claims 6 and 7 as rejected, but it is clear
from the explanation that the rejection should have been entered against
claims 14 and 15 (Final Act. 7–8).
8 In the Reply Brief, the Appellant argues that Huang does not teach the
limitation “a second integrated circuit chip mounted directly to the first
integrated chip by a third bump array” because Huang “does not describe the
second die 212 as a third bump, nor is the second die 212 being used to
control standoff height” (Reply Br. 4–5). Absent a showing of good cause,
however, new arguments in a Reply Brief that could have been raised in the
Appeal Brief are not permitted. 37 C.F.R. § 41.41(b)(2). Compare with the
argument made in the Appeal Brief, which urged that “Huang and Liu fail to
disclose ‘a second integrated circuit chip mounted directly to the first
integrated chip by a third bump array, as recited in the third clause of claim
1” because Huang discloses an intervening carrier (Appeal Br. 13).
Therefore, we decline to consider the new arguments in the Reply Brief. In
any event, claim 1 does not require the “third bump array” to control
standoff height.
Appeal 2018-008577
Application 14/959,537

5
The Examiner finds that Huang describes a wafer-level chip scale
package satisfying most of the limitations recited in claim 1, including
elements corresponding to the “first integrated circuit chip,” the “first bump
array,” the “second bump array . . . configured to provide standoff height,”
and “a second integrated circuit chip mounted directly to the first integrated
chip by a third bump array including at least one solder bump” (Final Act.
3–4 (relying on Huang, Fig. 2A)). The Examiner finds that Huang “fails to
expressly disclose wherein the first integrated chip is directly mounted to
bump assemblies and a second integrated circuit chip as a chip scale
package, without an intervening carrier” but relied on Liu to account for this
feature (id. at 4). The Examiner then concludes that “[i]t would have been
obvious to one having ordinary skill in the art . . . to modify the structure of
Huang to eliminate the chip carrier as disclosed by Liu while still
maintaining adequate standoff height to protect a bottom mounted device . . .
and reduce solder shorting conditions (id. (internal citation omitted)).
The Appellant’s principal argument is that Huang “fails to teach or
suggest ‘a first bump array disposed directly on the first integrated circuit
chip’ as recited in current claim 1” (emphasis added) because Huang teaches
that solder balls 208, 308 are disposed directly on a surface 201, 301 of a
carrier 206, 306, which, according to the Appellant, is not an “integrated
circuit chip” (id. at 11–12). The Appellant argues further that “Liu fails to
cure the deficiencies of Huang” as Huang also does not disclose this
contested limitation (id. at 12). For the same reasons, the Appellant argues
that Huang and Liu do not disclose “a second bump array disposed directly
on the first integrated circuit chip” as recited in claim 1 (id.). Regarding the
Examiner’s reasoning that a person having ordinary skill in the art would
Appeal 2018-008577
Application 14/959,537

6
have found it obvious to eliminate Huang’s chip carrier in view of Liu, the
Appellant argues that “removal of Huang’s carrier . . . would destroy the
intended use of Huang’s invention” because “Huang’s carrier 306 serves an
essential function” (id. at 13 (citing Huang ¶ 29; bolding added)).
The Appellant’s arguments fail to identify reversible error in the
Examiner’s rejection. In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011).
“During . . . original examination, the PTO must give claims their
broadest reasonable construction consistent with the specification.” In re
ICON Health & Fitness, Inc., 496 F.3d 1374, 1379 (Fed. Cir. 2007). Thus,
“we look to the specification to see if it provides a definition for claim terms,
but otherwise apply a broad interpretation.” Id. “As [our reviewing] court
has discussed, this methodology produces claims with only justifiable
breadth.” Id. In explaining why the PTO uses the broadest reasonable
interpretation standard during (re)examination rather than the “ordinary
meaning” standard used during litigation, the Supreme Court of the United
States observed:
[C]onstruing a patent claim according to its broadest reasonable
construction helps to protect the public. A reasonable, yet
unlawfully broad claim might discourage the use of the invention
by a member of the public. Because an examiner’s (or
reexaminer’s) use of the broadest reasonable construction
standard increases the possibility that the examiner will find the
claim too broad (and deny it), use of that standard encourages
the applicant to draft narrowly. This helps ensure precision
while avoiding overly broad claims, and thereby helps prevent a
patent from tying up too much knowledge, while helping
members of the public draw useful information from the
disclosed invention and better understand the lawful limits of the
claim.
Appeal 2018-008577
Application 14/959,537

7
Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2143, 2144–45
(2016) (emphasis added).
Applying these principles, we are in complete agreement with the
Examiner. As the Examiner points out (Ans. 2), the current Specification
informs one skilled in the relevant art that the term “first integrated circuit
chip” (identified as element 102) may include elements other than the
integrated circuit (identified as elements 106)—e.g., the “first integrated
circuit chip” may include a substrate 104 (Spec. ¶ 23; Fig. 1A). The
Appellant, on the other hand, does not direct us to any description in the
current Specification or Drawings that serves as a scope-limiting definition
for “first integrated circuit chip” such that it must be construed to exclude an
element such as carrier 206 shown in Huang’s Figure 2A. Under the
broadest reasonable interpretation standard of claim construction applicable
during examination, ICON Health, 496 F.3d at 1379, we discern no
reversible error in the Examiner’s claim construction that the term “first
integrated circuit chip” recited in claim 1 reads on a combination that
includes a first die 210 that is electrically connected to a carrier 206 (Huang,
¶ 24; Fig. 2A). Therefore, under the correct claim construction, we find that
Huang’s solder balls 208, 208a, and the solders in the second die 212 are in
fact “disposed directly on the first integrated circuit chip” or “mounted
directly to the first integrated [circuit] chip” as recited in claim 1.
Even if we assume that “first integrated circuit chip” must be
interpreted to exclude Huang’s carrier 206, we agree with the Examiner’s
analysis that a person having ordinary skill in the art would have reasonably
expected substrate 110, as part of Liu’s standoff limiting structure (standoffs
140 and solder balls 120 directly on substrate 110) in a ball grid array
Appeal 2018-008577
Application 14/959,537

8
(BGA) package to control package collapse to protect components from
contacting other components, to be an alternative or interchangeable
configuration suitable for connection to a PCB “without an additional carrier
as they contain integrated redistribution layers identical to the appellants
disclosed device,” to that shown by the combination of Huang’s carrier 206
and first die 210 (Ans. 4-5 (citing Liu ¶¶ 5, 13; Fig. 1)). KSR Int’l Co. v.
Teleflex Inc., 550 U.S. 398, 416–17 (2007).
In Huang, the carrier is merely positioned so that the solder balls
correspond to the pads on the PCB (Huang ¶ 29). But a substrate 110 with
lower surface 111, as shown in Liu, would also appear to be capable of
performing that function. The Appellant offers no evidence or explanation
to the contrary.
For these reasons and those given by the Examiner, we uphold the
Examiner’s rejections.
IV. SUMMARY
The Examiner’s rejections under 35 U.S.C. § 103(a) are sustained.
Therefore, the Examiner’s final decision to reject claims 1–15 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).

AFFIRMED