Victor A. Garibay et al.

Patent Trials and Appeals Board

Aug 30, 2019

14955739 - (D) (P.T.A.B. Aug. 30, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/955,739 12/01/2015 Victor A. Garibay AUS920150288US1 2552
82531 7590 08/30/2019
Lieberman & Brandsdorfer, LLC
802 Still Creek Lane
Gaithersburg, MD 20878
EXAMINER
LEE, CHUN KUAN
ART UNIT PAPER NUMBER
2181
MAIL DATE DELIVERY MODE
08/30/2019 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte VICTOR A. GARIBAY, DANIEL E. HURLIMANN,
CHETAN MEHTA, FERNANDO PIZZANO, and THOMAS R.
SAND1
____________

Appeal 2018-004795
Application 14/955,739
Technology Center 2100
____________

Before JAMES R. HUGHES, JOHN P. PINKERTON, and
JASON M. REPKO, Administrative Patent Judges.

HUGHES, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Appellant seeks our review under 35 U.S.C. § 134(a) of the
Examiner’s decision rejecting claims 1, 2, and 4–17. Claim 3 has been

1 International Business Machines Corp. (“Appellant”) is the applicant as
provided in 37 C.F.R. § 1.46 and is identified as the real party in interest.
Appeal Br. 3.
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canceled. See Final Act. 1; Appeal Br. 5.2 We have jurisdiction under
35 U.S.C. § 6(b).
We affirm.
Appellant’s Invention
The invention “relate[s] generally to allocation of lanes to a computer
bus” and, more specifically, relates “to dynamic allocation of lanes among
adapters received by connectors.” Spec. ¶ 1. In particular, the invention
relates to “a system, a method, and a computer program product for
dynamically allocating lanes among connectors of a computer bus.” Spec.
¶ 5; see Spec. ¶¶ 2–4, 6–8; Abstract.
Representative Claim
Independent claim 1, reproduced below, further illustrates the
invention:
1. A system comprising:
a processor in communication with memory;
a module, the module comprising a multiplexer in
communication with the processor, and two or more host bridges,
wherein each host bridge is in communication with the
multiplexer; and
a plurality of connectors in communication with respective
host bridges, including a first connector in communication with
a first host bridge and a second connector in communication with
a second host bridge, wherein each host bridge is positioned as
an interface between its respective connector and the

2 We refer to Appellant’s Specification (“Spec.”), filed Dec. 1, 2015; Appeal
Brief (“Appeal Br.”), filed Dec. 4, 2017; and Reply Brief (“Reply Br.”),
filed Apr. 4, 2018. We also refer to the Examiner’s Final Office Action
(“Final Act.”), mailed Aug. 2, 2016; and Answer (“Ans.”) mailed Feb. 5,
2018.
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multiplexer, wherein each connector is configured to receive a
respective adapter, and wherein the module is configured to:
at boot-time, detect a presence of each adapter
present, and dynamically control an initial allocation to the
connectors having a detected adapter, wherein the initial lane
allocation is dynamically controlled by the multiplexer, and
wherein the dynamic control of the initial lane allocation
comprises the module to assess a lane property for each detected
adapter, and to allocate lanes to each detected adapter based on
the assessment to maximize lane allocation and functionality for
the detected adapters; and
perform an additional lane allocation in response to
detection of an additional adapter.
Appeal Br. 29 (Claims App.).
Rejections on Appeal 3, 4
1. The Examiner rejects claims 1, 2, and 4–17 under 35 U.S.C.
§ 103 as being unpatentable over Foster Sr. (US 7,711,886 B2, issued May

3 The application on appeal has an effective filing date of Dec. 1, 2015.
Therefore, the Leahy-Smith America Invents Act (AIA) amendments to the
U.S. Code (§ 103) are applicable. See MPEP § 2159.02 (9th ed. 2018) (the
amended sections “apply to any patent application that contains . . . a
claimed invention that has an effective filing date that is on or after
March 16, 2013.”). Because this application has an effective filing date later
than the AIA’s effective date for applications, this decision refers to the AIA
version of § 103.
4 The Examiner has withdrawn the rejection under 35 U.S.C. § 101 (see
Final Act. 5–6). See Ans. 12. The Examiner provisionally rejected claim 1
on the ground of non-statutory obviousness-type double patenting as being
unpatentable over claim 1 of co-pending US Application No. 14/956373
(’373 App.) in view of Foster. The ’373 App. has issued as US Patent No.
10,296,484 (on May 24, 2019). Thus the provisional rejection has matured
into a non-provisional rejection. We reference the ’373 App. in our
discussion for consistency with the Examiner’s rejection and Appellant’s
arguments. We do not address Appellant’s arguments concerning the
withdrawn rejection.
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4, 2010) (“Foster”), Vasudevan et al. (US 2006/0168377 A1, published July
27, 2006) (“Vasudevan”), and Sharma et al. (US 2006/0179195 A1,
published Aug. 10, 2006) (“Sharma”). See Non-Final Act. 9–16.
2. The Examiner rejects claim 1 on the ground of non-statutory
obviousness-type double patenting as being unpatentable over claim 1 of co-
pending US Application No. 14/956373 (“’373 App.”—now US Patent No.
10,296,484) in view of Foster. See Non-Final Act. 6–9.
ISSUES
Based upon our review of the record, Appellant’s contentions, and the
Examiner’s findings and conclusion, the issues before us follow:
1. Did the Examiner provide a proper rationale for combining
Foster, Vasudevan, and Sharma to show that the combination of references
would have collectively taught or suggested “each host bridge [being]
positioned as an interface between its respective connector and the
multiplexer” within the meaning of Appellant’s claim 1 and the
commensurate limitations of claims 6 and 9?
2. Did the Examiner err in determining that claim 1 of the ’373
Application in view of Foster would have taught the disputed limitations of
independent claim 1?
ANALYSIS
Obviousness Rejection of Claims 1, 2, and 4–17
Appellant argues independent claim 1, independent claims 6 and 9,
and dependent claims 2, 4, 5, 7, 8, and 10–17, together as a group with
respect to the 35 U.S.C. § 103 rejection. See Appeal Br. 10–25. We select
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independent claim 1 as representative of Appellant’s arguments with respect
to claims 1, 2, and 4–17. 37 C.F.R. § 41.37(c)(1)(iv).
Appellant contends the Examiner has not presented a proper rationale
for combining Foster, Vasudevan, and Sharma, and the combination does
not teach all the features recited in Appellant’s claim 1. See Appeal Br. 10–
25; Reply Br. 2–9. Specifically, Appellant contends the combination of
Foster, Vasudevan, and Sharma does not “teach a computer system with a
multiplexer positioned ‘above’ two or more host bridges as recited in
Appellant’s pending claims” (Appeal Br. 17). See Appeal Br. 10–20.
Appellant also contends the Examiner does not provide a sufficient rationale
for combining Foster, Vasudevan, and Sharma and, therefore, the
Examiner’s rejection is improper. See Appeal Br. 21–25; Reply Br. 2–9.
The Examiner rejects claims 1, 2, and 4–17 over Foster, Vasudevan,
and Sharma. See Final Act. 9–16. The Examiner finds Sharma describes an
I/O bridge (110) that is equivalent to a multiplexer and connects between
processors (101–104) and multiple PCI host bridges (130, 114, 122, and
140). See Final Act. 11 (citing Sharma ¶¶ 25–28; Fig. 1); Ans. 13–24. The
Examiner also determines that “[i]t would have been obvious . . . to include
Vasudevan’s hot plug event and Sharma’s multiple host bridges architecture
into Foster[‘s] . . . architecture for the benefit of adding device while the
system is running . . . and improving reliability, availability and
serviceability of a data processing system” as detailed in Sharma. Final Act.
11. See Ans. 25–27.
We agree with the Examiner that Foster, Vasudevan, and Sharma
teach or at least suggest a multiplexer connected between processors and
multiple PCI host bridges as recited in Appellant’s claim 1. We also
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determine that the Examiner has provided a proper rationale for combining
the features of Foster, Vasudevan, and Sharma. See Final Act. 9–11; Ans.
12–27.
With respect to Appellant’s multiplexer feature, the Examiner finds
that Sharma describes the multiplexer architecture and one of ordinary skill
in the art could combine Sharma’s multiplexer architecture with Foster’s
dynamic lane allocation system—“incorporating Sharma’s bus architecture .
. . into Foster’s Expansion Subsystem Switch (102)” (Ans. 16 (emphases
omitted). See Final Act. 9–11; Ans. 12–24. As the Examiner shows in the
Examiner’s Answer (Ans. 13–16), the resulting combination includes a
“multiplexer in communication with the processor, and two or more host
bridges” and “wherein each host bridge is positioned as an interface between
its respective connector and the multiplexer” (claim 1 (Appeal Br. 29 (Claim
App.)))—that is, the combination at least suggests the physical structure
(architecture) recited in Appellant’s claim 1. Appellant contends that the
Examiner disregards the “the intents and purposes of both Foster . . . and
Sharma” (Reply Br. 4). We disagree. All three cited prior art references
describe PCI device interfaces. The protocol for interfacing PCI devices is
known in the art. Appellant’s argument conflates the prior art’s teachings
concerning physical architecture and the purpose for the architecture, which
we address with respect to Appellant’s combinability arguments, infra).
Appellant does not directly (and persuasively) address how the suggested
physical architecture differs from the recited architecture of claim 1.
With respect to Appellant’s combinability arguments, Appellant does
not persuasively explain why the references are incompatible (not analogous
or not in the same field of endeavor), nor does Appellant argue that the
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references teach away from one another. In contrast to Appellant’s
arguments (see Appeal Br. 21–25; Reply Br. 2–9) the Examiner need not
explain how to bodily combine the features of the prior art references—
“[t]he test for obviousness is not whether the features of a secondary
reference may be bodily incorporated into the structure of the primary
reference . . . . Rather, the test is what the combined teachings of the
references would have suggested to those of ordinary skill in the art.” In re
Keller, 642 F.2d 413, 425 (CCPA 1981) (emphasis added). See In re
Mouttet, 686 F.3d 1322, 1332–33 (Fed. Cir. 2012). Here, Appellant argues
the references individually and does not address the specific arguments set
out by the Examiner. The references cited by the Examiner must be read,
not in isolation, but for what each fairly teaches in combination with the
prior art as a whole. See In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir.
1986) (one cannot show non-obviousness by attacking references
individually where the rejections are based on combinations of references).
As we explain supra, all three cited prior art references describe PCI device
interfaces utilizing known protocols and standards for interoperability of PCI
devices.
Additionally, the Supreme Court has held that in analyzing an
obviousness rationale, the Examiner “need not seek out precise teachings
directed to the specific subject matter of the challenged claim . . . [and may]
take account of the inferences and creative steps that a person of ordinary
skill in the art would employ.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398,
418 (2007). Also, the Examiner may consider “the background knowledge
possessed by a person having ordinary skill in the art.” KSR, 550 U.S. at
418 (quoting In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)). Further, an
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artisan is presumed to possess both skill and common sense. See KSR, 550
U.S. at 421 (“A person of ordinary skill is also a person of ordinary
creativity, not an automaton.”).
With respect to Appellant’s argument concerning Nuvasive (In re
Nuvasive, 842 F.3d 1376, 1384 (Fed. Cir. 2016)) (see Appeal Br. 24–25;
Reply Br. 7–8), we disagree that the Examiner’s rationale is merely
conclusory (see Appeal Br. 24). The Examiner provides a detailed
explanation of the combination (of Foster with Sharma and Vasudevan) to
provide the recited structural features and explains why one would make the
combination—to allow hot-swapping of PCI devices (as taught by
Vasudevan), and increase reliability and efficiency (as explicitly taught in
Sharma). This is not the case (as in Nuvasive) where disparate technologies
were combined with only a perfunctory conclusory rationale. Here, as we
explain supra, all three cited prior art references (Foster, Vasudevan, and
Sharma) describe PCI device interfaces utilizing known protocols and
standards for interoperability of PCI devices. For the all the reasons set
forth above, we find the Examiner provided a legally cognizable rationale
for the combination of Foster, Vasudevan, and Sharma, in that the Examiner
“articulated reasoning with some rational underpinning to support the legal
conclusion of obviousness.” KSR, 550 U.S. at 418 (quoting In re Kahn, 441
F.3d at 988).
We further find that it would have been within the skill of an
ordinarily skilled artisan to combine Foster’s dynamic lane allocation system
with Sharma’s I/O bridge and bus architecture. See KSR, 550 U.S. at 417
(“[I]f a technique has been used to improve one device, and a person of
ordinary skill in the art would recognize that it would improve similar
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devices in the same way, using the technique is obvious unless its actual
application is beyond his or her skill.”). We are not persuaded that
combining the respective familiar elements of the cited references in the
manner proffered by the Examiner would have been “uniquely challenging
or difficult for one of ordinary skill in the art” at the time of Appellant’s
invention. Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162
(Fed. Cir. 2007) (citing KSR, 550 U.S. at 418).
Accordingly, Appellant’s contentions do not persuade us of error in
the Examiner’s obviousness rejection of representative independent claim 1.
Therefore, we affirm the Examiner’s rejection of representative claim 1,
independent claims 6 and 9, and dependent claims 2, 4, 5, 7, 8, and 10–17,
not separately argued with particularity (supra).
The Double Patenting Rejection of Claim 1
The Examiner rejects independent claim 1 on the ground of non-
statutory obviousness-type double patenting over claim 1 of the ’373 App. in
view of Foster. See Final Act. 6–9; Ans. 28–29. Appellant contends that the
’373 App. does not teach functionality at boot-time, but instead teaches
functionality occurring after boot-time, and Foster do not teach the same
architecture. See Appeal Br. 26–27; Reply Br. 9.
We agree with Examiner, for the same reasons as claim 1 (supra), that
Appellant has not persuasively explained why the functionality of Foster
could not be combined with the architecture of the’373 App. The
architecture described in the ’373 App. is identical to the architecture of the
instant invention (Appellant’s claim 1). See Fig. 1 of the ’373 App. See
Final Act. 6–9; Ans. 28–29.
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We further find that it would have been within the skill of an
ordinarily skilled artisan to combine the ’373 Application’s architecture with
Foster’s teaching of a dynamic lane allocation system. See KSR, 550 U.S. at
417–18. Accordingly, Appellant’s contentions do not persuade us of error in
the Examiner’s double patenting rejection of claim 1. Therefore, we affirm
the Examiner’s rejection of claim 1.
CONCLUSION
Appellant has not shown that the Examiner erred in rejecting claims 1,
2, and 4–17 under 35 U.S.C. § 103.
Appellant has not shown that the Examiner erred in rejecting claim 1
on the ground of non-statutory obviousness-type double patenting.
DECISION
We affirm the Examiner’s rejections of claims 1, 2, and 4–17.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See
37 C.F.R. § 41.50(f).
AFFIRMED