Toshiba Memory Corporation

Patent Trials and Appeals Board

May 3, 2021

2020005879 (P.T.A.B. May. 3, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/456,033 03/10/2017 Akira TAKASHIMA 14293.0035 8774
22852 7590 05/03/2021
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
LIU, MIKKA H
ART UNIT PAPER NUMBER
2895
NOTIFICATION DATE DELIVERY MODE
05/03/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
regional-desk@finnegan.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte AKIRA TAKASHIMA, KENICHIRO TORATANI, and
MASAYUKI TANAKA
Appeal 2020-005879
Application 15/456,033
Technology Center 2800
Before CAROLYN D. THOMAS, MICHAEL J. STRAUSS, and
PHILLIP A. BENNETT, Administrative Patent Judges.
BENNETT, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–10. Claims 11–17 are withdrawn.
We heard argument in this case on April 14, 2021, and a transcript will be
placed in the record in due course. We have jurisdiction under
35 U.S.C. § 6(b).

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42(a).
Appellant identifies the real party in interest as Toshiba Memory
Corporation. Appeal Br. 1.
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Application 15/456,033

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We affirm.
CLAIMED SUBJECT MATTER
The claims are directed to a nonvolatile semiconductor memory
device. Claim 1, reproduced below with key limitations in italics, is
illustrative of the claimed subject matter:
1. A nonvolatile semiconductor memory device, comprising:
a semiconductor layer;
a first electrode;
a first layer provided between the semiconductor layer and
the first electrode;
a second layer provided between the first layer and the first
electrode, a second energy of a conduction band edge of the
second layer being lower than a first energy of a conduction band
edge of the first layer, the second layer including a first region
and a second region, the first region being provided between the
first layer and the second region;
a third layer provided between the second layer and the
first electrode, a third energy of a conduction band edge of the
third layer being higher than the second energy;
a plurality of nitride portions of nitride molecules, the
plurality of nitride portions being provided in the first layer, or
between the second layer and the third layer;
a second electrode arranged with the first electrode in a
second direction, the second direction crossing a first direction,
the first direction being from the semiconductor layer toward the
first electrode; and
an insulating film provided between the first electrode and
the second electrode,
the first layer being a tunneling insulating layer,
the second layer being a charge storage layer,
the third layer being a blocking insulating layer,
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the nitride molecule including at least one of TiN, ZrN,
HfN, VN, NbN, TaN, CrN, MoN, WN, BN, AIN, GaN, or lnN,
a length in the first direction of the plurality of nitride
portions being not more than a maximum value of a size of the
nitride molecule,
the first layer being further provided between the second
electrode and the semiconductor layer,
the second layer being further provided between the
second electrode and the first layer,
the first layer and the second layer being provided between
the insulating film and the semiconductor layer, and
at least one of the nitride portions being further provided
between the insulating film and the semiconductor layer.
Appeal Br. 12–13 (Claims Appendix).
REFERENCES2
The prior art relied upon by the Examiner is:
Name Reference Date
Huo US 2008/0246078 A1 Oct. 9, 2008
Jung US 2016/0240550 A1 Aug. 18, 2016

REJECTION
Claims 1–10 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Huo and Jung. Final Act. 4–14.
ISSUES
First Issue: Has the Examiner erred in determining that Huo’s lower
trap layer is a “charge storage layer” within the meaning of claim 1?

2 All citations herein to the references are by reference to the first named
inventor/author only.
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Application 15/456,033

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Second Issue: Has the Examiner erred in determining the nanodots in
Huo’s lower trap layer are “between the second layer and the third layer,” as
recited in claim 1?
ANALYSIS
First Issue
The Examiner rejects the claims as obvious over Jung and Huo. The
Examiner finds that Jung teaches many of the limitations of claim 1, but
deficient in certain respects:
However, Jung does not explicitly disclose a plurality of nitride
portions of nitride molecules, the plurality of nitride portions
being provided in the first layer, or between the second layer and
the third layer; the nitride molecule including at least one of TiN,
ZrN, HfN, VN, NbN, TaN, CrN, MoN, WN, BN, AIN, GaN, or
lnN, a length in the first direction of the plurality of nitride
portions being not more than a maximum value of a size of the
nitride molecule, and at least one of the nitride portions being
provided between the insulating film and the semiconductor
layer.
Final Act. 6. To address this deficiency, the Examiner introduces Huo. The
Examiner finds that Huo “recognizes a need to prevent loss of charge[] from
the charge trap layer and improves charge storage capacity in a memory
device.” Final Act. 6 (citing Huo Abst. and ¶ 18). The Examiner further
determines that “Huo satisfies the need by adding a plurality of nanodots
142a that are provided between a charge trap layer 144 (i.e., second layer)
and a block insulating layer 150 (i.e., third layer).” Final Act. 6 (citing Huo
¶¶ 46, 60, 62, 64–66, 71, 73; Fig. 4B). The Examiner finds the nanodots
142a satisfy the “nitride molecule” recited in claim 1 because “the nitride
material of nanodots 142a must be formed of nitride molecules, [and] any
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nitride molecule must be smaller than the nanodot 142a in any direction.”
Final Act. 6.
Appellant challenges the Examiner’s findings with respect to the
recited “second layer.” Specifically, Appellant contends the Examiner erred
in finding “Huo’s lower trap layer 144 (FIG. 4B) corresponds to the ‘second
layer being a charge storage layer’ recited in claim 1.” Appeal Br. 9.
Appellant asserts the Examiner’s characterization of layer 144 as a charge
storage layer is flawed because “the lower trap layers 144 and 144a are only
part of the charge trap layer 140a” and “Huo does not teach or suggest that
the lower trap layers 144 and 144a alone can function as a charge trap
layer.” Appeal Br. 9. According to Appellant, “the nano dots 142a only
exist within the charge trap layer 140a” and “Huo does not teach or suggest
that the nanodots 142a exist between the charge trap layer 140a (asserted by
the Examiner as the claimed ‘second layer’) and the block insulating layer
150 (asserted by the Examiner as constituting the claimed ‘third layer’).”
Appeal Br. 9; see also Reply Br. 8 (“In other words, in the absence of
nanodots 142, electrons will not be trapped in the lower trap layer 144.”).
We are not persuaded of error. We reproduce the Huo’s Figure 4B
with annotations illustrating the Examiner’s findings:
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As shown, the Examiner determines that the charge trap layer 144, of which
nanodots 142 are a part, teaches the recited “second layer being a charge
storage layer,” because “Huo’s lower charge trap 144, which stores electrical
charge, is a ‘charge storage layer.’” Ans. 4.
As the Examiner notes, Appellant does not contest the finding that the
Huo’s charge trap layer 144 stores charge. Rather, Appellant argues that the
layer 144 only is able to store charge with the assistance of the nanodots 142
which are formed within the layer. We agree with the Examiner, however,
that “[t]he breadth of claim 1 does not preclude the claimed ‘charge storage
layer’ from reading on Huo’s lower charge trap layer 144.” Ans. 4. That is,
claim 1 does not exclude the presence of nanodots as part of the charge
storage layer. In Huo, layer 144 incorporates nanodots 142 which allow the
layer 144 to store charge. Although incorporated into a larger charge trap
layer 140a which encompasses several sub-layers, we discern nothing in the
claim that precludes interpreting each of those individual layers as a layer in
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and of itself. As such, we agree with the Examiner that Huo’s charge trap
layer 144 is a “charge storage layer” within the meaning of claim 1.
Second Issue
The Examiner further determines that the nanodots 142a formed in the
additional lower trap layer 144a correspond to the recited “nitride portions.”
Final Act. 6–7. Appellant does not contest that the nanodots teach or
suggest “nitride portions,” but rather assert that their location in Huo’s
structure is different than what is claimed. Specifically, Appellant argues
Huo’s nitride portions 142a are not between the second layer and the third
layer. Appeal Br. 9, 10 (“[T]he nanodots 142a are completely surrounded by
the lower trap layers 144 and 144a, which are parts of the charge trap layer
140a.”).
We are not persuaded of error. As noted above, Appellant contends
that Huo’s charge trap layer 140a is the only structure that can correspond to
the recited “charge storage layer.” As we explained above, we do not agree
with this contention because the individual layers within Huo’s charge trap
layer 140a are capable of storing charge of themselves. Appellant’s
argument in this regard is premised on the assumption that Huo’s charge trap
layer 140a corresponds to the claimed charge storage layer. But that is not
the finding made by the Examiner here. The Examiner finds the lower trap
layer 144 along with its incorporated nanodots 142 meets the “second layer”
limitation, and the nanodots 142a incorporated into layer 144 are “between
the second layer and the third layer.” We agree with this finding because
nanodots 142a are positioned between layer 142 and insulator 150. As such,
we are not persuaded the Examiner erred, and we sustain the rejection of
claim 1 under § 103.
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Remaining Claims
Appellant presents no separate arguments for patentability of any
other claims. Accordingly, we sustain the Examiner’s rejections of these
claims for the reasons stated with respect to the independent claims from
which they depend. See 37 C.F.R. § 41.37(c)(1)(iv).
CONCLUSION
We affirm the Examiner’s decision to reject the claims.
DECISION SUMMARY
Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1–10 103 Jung, Huo 1–10

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED