Tongbi Jiang et al.

Patent Trials and Appeals Board

Aug 16, 2019

14802941 - (D) (P.T.A.B. Aug. 16, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/802,941 07/17/2015 Tongbi Jiang 010829-8948.US03 2545
46844 7590 08/16/2019
PERKINS COIE LLP - Micron
PATENT-SEA
PO BOX 1247
SEATTLE, WA 98111-1247
EXAMINER
WRIGHT, TUCKER J
ART UNIT PAPER NUMBER
2891
NOTIFICATION DATE DELIVERY MODE
08/16/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patentprocurement@perkinscoie.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE
THE PATENT TRIAL AND APPEAL BOARD
________________

Ex parte TONGBI JIANG1
and YONG POO CHIA
________________

Appeal 2018-008165
Application 14/802,941
Technology Center 2800
________________

Before BRADLEY R. GARRIS, MARK NAGUMO, and
KAREN M. HASTINGS, Administrative Patent Judges.

NAGUMO, Administrative Patent Judge.

DECISION ON APPEAL
Micron Technology, Inc. (“Jiang”) timely appeals
under 35 U.S.C. § 134(a) from the Final Rejection2 of claims 1–7 and 9.3
We have jurisdiction. 35 U.S.C. § 6. We reverse.

1 The applicant under 37 C.F.R. § 1.46, and hence the appellant under
35 U.S.C. § 134, is the real party in interest, identified as Micron
Technology, Inc. (Appeal Brief, filed 19 March 2018 (“Br.”), 2.)
2 Office Action mailed 23 October 2017 (“Final Rejection”; cited as “FR”).
3 Remaining copending claims 23–27 have been withdrawn from
consideration by the Examiner (FR 1, § 5a), and are not before us.
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Application 14/802,941

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OPINION
A. Introduction4
The subject matter on appeal relates to stacked packages of
conductively coupled integrated circuit devices.
An embodiment of the invention is illustrated in Figure 4, below.

{Figure 4 shows device 400 comprising stacked packaged sets (10E, 10F) of
individual die (10A, 10B, 10C, and 10D)}

4 Application 14/802,941, Packaged integrated circuit devices with
through-body conductive vias, and methods of making same,
filed 17 July 2015 as a division of 14/273,138, filed 8 May 2014, now U.S.
Patent No. 9,099,571, which is a continuation of 12/852,925, filed 9 August
2010, now U.S. Patent No. 8,723,307, which is a division of 11/834,765,
filed 7 August 2007, now U.S. Patent No. 7,781,877. We refer to the
“′941 Specification,” which we cite as “Spec.”
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Device 400 comprises illustrative individual embedded die 10A–10D,
which are assembled first as group 10E and group 10F. (Spec. 6, ll. 13–15.)
A plurality of conductive structures 22 provide an electrically conductive
path between groups 10E and 10F. (Id. at ll. 20–21.) Conductive vias 32,
and 34, through the bodies (of encapsulant material) 20 of dies 10, provide
interconnections between individual embedded die 10A and 10B, in
Group 10E, and between individual embedded die 10C and 10D in
Group 10F. (Id. at ll. 16–19.) Each embedded die comprises integrated
circuit die 12, a plurality of bond pads 14, conductive wiring lines 16
(sometimes referred to as a redistribution layer (RDL)). In this embodiment,
the backside 15 of adjacent embedded die 10 are positioned facing one
another (id. at 6, l. 23) and are secured to one another with adhesive 28
(id. at 9, ll. 3–4).
Sole independent claim 1 is representative and reads:
A device [400], comprising:
a first group [10E] of embedded die [10A, 10B] and
a second group [10F] of embedded die [10C, 10D]
vertically aligned with the first group [10E], wherein
each of the first and second groups of embedded die
comprise a vertically-aligned plurality of individual
embedded die,
each of the individual embedded die comprise
an integrated circuit die [12] and
a body of encapsulant material [20], and
each integrated circuit die [12] has
a back side that is embedded in the body of
encapsulant material [30] and
a front side [13] that is generally flush with an
outermost surface of the first group [10E] or the
second group [10F] of embedded die;
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at least one first conductive via [34] that extends through
the first group [10E] of embedded die;
at least one second conductive via [32] that extends
through the second group [10F] of embedded die; and
at least one conductive structure [22] positioned between
the first [10E] and second groups [10F] of embedded die
that provides an electrically conductive flow path
between the first [34] and second [32] conductive vias.
(Claims App., Br. 7; some formatting, emphasis, and bracketed bold labels
to elements shown in Figure 4 added.)
The Examiner maintains the following ground of rejection:5, 6, 7
Claims 1–7 and 9 stand rejected under 35 U.S.C. § 102(e) in view
of Gomyo.8

5 Examiner’s Answer mailed 17 May 2018 (“Ans.”).
6 Because this application claims the benefit of applications filed
before 16 March 2013, the effective date of the America Invents Act, we
refer to the pre-AIA version of the statute.
7 A rejection under 35 U.S.C. § 112, second paragraph, was withdrawn
following the entry of amendments filed under 37 C.F.R. § 1.116
on 22 January 2018. (Advisory Action, entered 6 February 2018.)
8 Toshio Gomyo et al., Electronic parts packaging structure and method of
manufacturing the same, U.S. Patent Application Publication
2007/0018313 A1 (25 January 2007), based on an application
filed 14 July 2006.
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B. Discussion
The Board’s findings of fact throughout this Opinion are supported by
a preponderance of the evidence of record.
The Examiner finds that Gomyo discloses, in Figure 1, reproduced
below, as annotated by the Examiner in the Examiner’s Answer (Ans. 4), an
embodiment within the scope of claim 1.

{Gomyo Figure 1, annotated by the Examiner, shows an electronic parts
packaging structure of a plurality of sheet-like units}
The backslash-shaded line surrounding portions of the top two sheet-
like units 10 highlights, in the Examiner’s words, “part of an outermost
surface (or perimeter) of the first group or the second group of embedded
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die.” (Ans. 3, ll. 8–10.) The Examiner “interprets the claimed outermost
surface as the perimeter of a body of encapsulant material and a front side of
an integrated circuit die (see reproduced FIG. 1 of Gomyo above).” (Ans. 4,
ll. 4–6.) This interpretation is, in the Examiner’s view, “the only reasonable
interpretation in light of FIG. 4 of the present application and the lack of any
disclosed reference point.” (Id. at 5, ll. 4–6 (emphasis added).)
Jiang urges the Examiner errs harmfully in the finding of anticipation
(Br. 5–6), because Gomyo does not describe integrated circuits having
“a front side that is generally flush with an outermost surface of the first
group or the second group of embedded die” as required by claim 1. (Br. 5,
ll. 3–4.) Rather, according to Jiang, “Gomyo discloses semiconductor chips
recessed within a unit, such that the front side thereof is not generally flush
with an outermost surface thereof.” (Id. at ll. 5–6.)
The weight of the evidence supports Jiang.
The Examiner provides no citations to the record that indicate that the
term “outermost surface of the first group . . . of embedded die” would be
read by an ordinary designer of packaged integrated circuit devices as
excluding layers or partial layers of the die package like “underfill
(protection film) 29” (Gomyo 3, para. 42, last sentence.) While it is true that
claim 1 recites that “each of the individual embedded die comprise an
integrated circuit die and a body of encapsulant material,” and does not
recite the presence of an underfill layer, the transitional phrase “comprises”
is “open” to additional, non-recited materials. A group of embedded die
would ordinarily include at least everything in (or on) each constituent
embedded die, and the outermost surface of that group would be no
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different, absent express definition in the art or in the Specification. Indeed,
although not an exclusive definition, the Specification describes a die 12 in
the embodiment of the invention shown in Figure 2 (not reproduced here), as
having “plurality of bond pads 14, conductive wiring lines 16 (sometimes
referred to as a redistribution layer (RDL)), and at least one conductive
interconnection 18 (sometimes referred to as conductive vias) that extend
through the body 20 of encapsulant material.” (Spec. 4, ll. 21–24 (emphasis
added).) The Examiner’s definition excludes not only underfill layer 29,
which is not mentioned in the ’941 Specification, but also portions of
“wirings 26” (corresponding to wireline 16), “bumps 28” (corresponding
roughly to bond pads 14), and arguably terminals 24 and solder resist
layer 22, which are a part of each embedded die.
Put another way, the Examiner has not shown that a person having
ordinary skill in the art would have concluded that the ’941 Specification
lacks a “reference point” from which the “outermost surface of a group of
embedded die” is to be defined, such that that outermost surface would
exclude the underfill layer 29, as indicated in the Examiner’s annotated
Figure 1 of Gomyo. Although apparently not defined expressly in
the ’941 Specification, the front of the integrated circuit die refers
consistently to the side to which electrical connections are made via bonding
pads and wiring lines, while the backside refers to the side having no
electrical connections that is embedded in encapsulating body 20. Gomyo
appears to use the same convention, defining the “back surface” as the
“surface opposite to the semiconductor chip mounting surface[] of the
substrate.” (Gomyo 6 [0079], first sentence.) The appealed claims require
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that the front side 13 of integrated circuit 12 be “generally flush” with the
outermost surface of one of the groups of embedded die.
Because an erroneous interpretation of the claims is required to
establish anticipation by Gomyo, we reverse the appealed rejection.
C. Order
It is ORDERED that the rejection of claims 1–7 and 9 is reversed.
REVERSED