THE BOEING COMPANY

Patent Trials and Appeals Board

Feb 19, 2020

14459234 - (D) (P.T.A.B. Feb. 19, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/459,234 08/13/2014 Laszlo Hars 14-0054-US-NP 5852
122219 7590 02/19/2020
Miller, Matthias & Hull LLP/ The Boeing Company
One North Franklin Street
Suite 2350
Chicago, IL 60606
EXAMINER
THOMAS, JAMES JORDAN
ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
02/19/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
bmatthias@millermatthiashull.com
patentadmin@boeing.com
ynunez@millermatthiashull.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte LASZLO HARS

Appeal 2019-001005
Application 14/459,234
Technology Center 2100
Before, KARL D. EASTHOM, KALYAN K. DESHPANDE, and
NABEEL U. KHAN, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON APPEAL
I. STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant appeals from the
Examiner’s Final Action rejecting claims 1–20.1 Final Act. 1. We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 “Appellant” here connotes an “applicant” as defined in 37 C.F.R.
§ 1.42(a). Appellant identifies the real party in interest as “The Boeing
Co[.]” Appeal Br. 2.
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II. DISCLOSED AND CLAIMED SUBJECT MATTER
The Specification discloses memory control systems having a logical
address space accessed by a processor for referencing memory locations, and
a memory controller that maps logical address spaces to physical address
spaces in an external memory system. Spec. Abstract, ¶¶ 5–7, 22, Fig. 1.
Figure 1 follows:

Figure 1 above shows a logical address space accessed by processor
120 and a physical address space associated with physical memory in
external memory system 130. Spec. ¶¶ 20–21. Memory controller 150
translates logical addresses from processor 120 to physical addresses for
memory in protected windows 132 of external memory system 130. Id.
¶¶ 19–22. Memory controller 150 manages data flow on line 140 by
dynamically remapping a map between logical addresses and physical
addresses. Id. ¶ 22. Traffic on data path 140 “includes but is not limited to
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read/write signals, memory addresses, timing information, and data that is
read from and written to the external system memory 130.” Id. ¶ 18.
Memory controller 150 also thwarts nefarious traffic analysis of
unprotected data path 140 that might otherwise reveal memory access
patterns. Id. ¶¶ 24–25. It thwarts the nefarious analysis by “dynamically
remapping the logical address space of the processor 120 to the physical
address space of the external system memory 130.” Id. ¶ 25. This
remapping “hides” the access patterns. Id. ¶ 6. “For maximum protection
against traffic analysis, the remapping may be performed at each and every
data access to the logical address space. However, the remapping may be
performed less frequently.” Id. ¶ 27.
After remapping a logical address from a first physical address to a
second physical address, in some embodiments, memory controller also
sends data to a second physical address. Id. ¶ 7. This relocation of physical
data further obfuscates access patterns, because the logical memory address
does not change as its corresponding physical data locations do. Id. ¶ 39.
Independent claim 1, reproduced below, illustrates the claimed subject
matter on appeal:
1. A method of providing security in a computing system
including a processor having a logical address space and external
system memory having physical address space, the method
comprising:

hiding memory access patterns by altering a logical-to-
physical address space map each time the logical memory is
accessed including detecting a data access via the logical address
space, to a first physical address in the physical address space
containing protected data, and based on the detected data access,
remapping the protected data in the logical address space to
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instead map to a second physical address in the physical address
space, and storing the protected data at the second physical
address while leaving the logical address space unchanged.
III. REFERENCES
The Examiner relies upon the following references:
Name Reference Date
Mather US 8,819,386 Bl Aug. 26, 2014
Hasbun US 2006/0129753 Al June 15, 2006
Avudaiyappan US 2010/0262751 Al Oct. 14, 2010
Chou US 2011/0191562 Al Aug. 4, 2011
Uner US 2013/0081103 A1 Mar. 28, 2013
Hars US 2013/0117577 Al May 9, 2013
Stefanov US 2014/0007250 Al Jan. 2, 2014
Manoharan US 2015/0277775 Al Oct. 1, 2015
IV. REJECTIONS
Claims
Rejected
35 U.S.C. § References
1–6, 12, 17, 18, 20 103 Uner, Hasbun
7 103 Uner, Hasbun, Stefanov
8–11, 19 103 Uner, Hasbun, Mather
13 103 Uner, Hasbun, Avudaiyappan
14 103 Uner, Hasbun, Manoharan
15 103 Uner, Hasbun, Chou
16 103 Uner, Hasbun, Chou, Hars
V. OPINION
The Examiner rejects claims 1–20 as obvious over the combined
teachings as set forth in the table above. See Final Act. 8–23. Appellant
treats independent claims 1, 12, and 20 as a group and relies on arguments it
presents for claim 1. See Appeal Br. 23 (“Applicant respectfully submits
that claims 12 and 20 are in condition for allowance for essentially the same
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reasons set forth above in the discussion of claim 1. Claims 13–19 depend
from claim 12, which has been demonstrated to be allowable.”). Therefore,
claim 1 represents the claims on appeal.
The Examiner relies on Uner’s teachings as disclosing most of the
claim 1 limitations, relies on Uner to suggest “altering a space map each
time the logical memory is accessed,” and relies on the combined teachings
of Uner and Hasbun to suggest “storing the protected data at the second
physical address while leaving the logical address space unchanged.” See
Final Act. 3–4. The Examiner supports the obviousness determination with
a factual underpinning and supported reasons for the combination. See Final
Act. 3–7.
Specifically, the Examiner’s finds Uner discloses most of the claim 1
limitations, including hiding memory access patterns, as follows:
Uner discloses a method of/(a computing system comprising)
providing security in a/the computing system including a
processor having a logical address space and external system
memory having physical address space, the method comprising
[Fig. 1, [0018], [0026], Fig. 4A, 4B, & [0065]–[0066], where
virtual memory is a logical address space]:
hiding memory access patterns by altering a logical-to-
physical address space map including detecting a data access via
(an address in) the logical address space, to a first physical
address in the physical address space containing protected data,
and based on the detected data access, remapping the protected
data/address in the logical address space to instead map to a
second physical address in the physical address space [Fig. 1, 4A,
4B, [0028], & [0065]–[0066], where a command or any directive
are data accesses; since dynamic remapping occurs, access
patterns are hidden (also see [0006], where taking gradual action
is hiding access patterns); Fig. 4A shows an access to a first
physical memory and Fig. 4B shows a remapping of protected
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data to a second physical memory (or a second physical address);
since a protection core 114 is performing the remapping, the data
in a physical address space being remapped is protected].
Final Act. 3 (information supplied by the Examiner).
Figures 4A and 4B of Uner, upon which the Examiner relies as
quoted above, follow:

As the Examiner finds, Figures 4A and 4B represent remapping
of a logical map wherein a logical address points to a first physical
address at Figure 4A and a second physical address at Figure 4B after
such remapping. Final Act. 4, Uner ¶¶ 65, 66.
Appellant does not dispute these findings by the Examiner. The
Examiner also finds “Uner does not disclose altering a space map
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each time the logical memory is accessed; and storing the protected
data at the second physical address while leaving the logical address
space unchanged.” Final Act. 3–4 (emphasis added).
The Examiner finds that although Uner does not “explicitly
disclose altering a space map each time the logical memory is
accessed,” “Uner does disclose remapping upon a command or any
directive.” Id. at 4 (citing ¶ 66) (emphasis added). Given these
teachings about a “command” or “any directive” dictating the
frequency of altering a space map, the Examiner finds “[i]t would
have been obvious . . . to have the remapping of Uner take place for
each access,” because “remapping is occurring for some number of
data accesses, choosing remapping for each time a logical memory is
accessed is choosing from a finite number of identified, predictable
solutions, with a reasonable expectation of success.” Id.
For the final claim step, the Examiner contends “Hasbun discloses
storing the protected data at the second physical address while leaving the
logical address space unchanged.” Final Act. 4 (explaining “where
rearranging content is storing data at a second physical address” (citing
Hasbun claim 2, ¶¶ 10, 14–18)). According to the Examiner, “[t]he
motivation for [the] combination is to assure that power consumption of the
system is reduced in that keeping a persistent logical address space allows
the physical address space to be rearranged into a more energy efficient
configuration while still being accessible via the logical address space.” Id.
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Hasbun’s Figure 2 follows:

Figure 2 above shows the mapping and shifting of physical memory at
(b) to a new location at (c) using the same logical pointers from virtual
memory (a). See Hasbun ¶¶ 3, 6, 14, 15. Figure 2 of Hasbun represents a
structurally and functionally similar virtual memory system to that of Uner.
Compare Hasbun, Fig. 2, with Uner, Figs. 4A and B.
Hasbun describes “dynamic packing of the memory,” using “a number
of metrics.” Id. ¶ 9. Hasbun explains “the term ‘packing’ is broadly used
herein to mean that content may be initially placed or rearranged in the
physical memory to minimize the footprint in the physical memory.” Id.
¶ 15. Hasbun also describes using “processor activity” “or other event[s]
which may affect memory as encountered 225,” as criteria for packing
memory. Id. ¶ 21; see id. Fig. 2 (step 225 (“Additional Packing Criteria”)).
As the Examiner finds, Hasbun performs packing, i.e., physical memory
rearrangements, to create a more efficient storage system. See Final Act. 4;
Hasbun ¶ 15, code (57) (the system minimizes memory footprint, frees
memory for power down, and frees areas requiring refresh).
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Appellant agrees “Hasbun contemplates the concept of a mapping.”
Appeal Br. 22. Apart from arguing that Hasbun does not constitute
analogous art (addressed below), Appellant does not challenge the
Examiner’s findings about the stated reason for combining Hasbun’s system
with Uner.
Rather, Appellant first focuses on Uner and argues “claim 1 recites
‘hiding memory access patterns by altering a logical-to physical address
space map each time the logical memory is accessed.’ There does not
appear to be anything in Uner that discloses, teaches, or suggests this
limitation.” Appeal Br. 22. This argument does not address the Examiner’s
finding that it would have been obvious to modify the frequency of altering
Uner’s address state map so that it occurs at each memory access event. As
indicated above, the Examiner finds that such a frequency modification
would have been predictable and obvious to try, because Uner discloses
altering the space map upon any command or directive, thereby suggesting
altering the space map for each memory access. See Final Act. 4 (citing
Uner ¶ 66).
The Examiner also shows persuasively that Uner’s system naturally
performs the hiding function by altering the logical-to physical address
space map when the system accesses the logical memory. See id. at 3; Ans.
14–15. Appellant’s mere denial about hiding does not explain why Uner’s
materially similar memory address mapping system fails to hide memory
access patterns. See, e.g., In re Best, 562 F.2d 1252, 1255 (CCPA 1977)
(“Whether the rejection is based on ‘inherency’ . . . [or] on ‘prima facie
obviousness,’” if “the claimed and prior art products are identical or
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substantially identical, or are produced by identical or substantially identical
processes, the PTO can require an applicant to prove that the prior art
products do not necessarily or inherently possess the characteristics of his
claimed product.”); In re Schreiber, 128 F.3d 1473 (Fed. Cir. 1997) (similar
holding, finding that a reference to an oil can funnel anticipates a claim
reciting a “dispensing top for passing only several kernels of a popped
popcorn at a time from an open-ended container filled with popped popcorn
. . . the taper of the top being uniform and such as to by itself jam up the
popped popcorn before the end of the cone and permit the dispensing of only
a few kernels at a shake of a package when the top is mounted on the
container”).
Appellant disputes that in Uner, “a command or any directive are data
accesses.” Appeal Br. 22. Appellant contends “a data access [in Uner] is
not a memory access, nor does a data access teach or suggest that a memory
access may have taken place.” Id. According to Appellant, Uner’s
Supervisory Control and Data Acquisition (“SCADA”) system, which issues
directives and commands, fails to suggest accessing memory, because
[t]ypically [in a SCADA system], a command may require that a
controller set point be changed, but this activity does not imply
any type of memory access. As to the “directive” terminology,
it is not a SCADA term of art, and appears in the Uner reference
only twice, with insufficient context for the reader to determine
exactly what “directive” might encompass. There is certainly no
hint that a memory access might be involved. In any event, a
data access is not a memory access, nor does a data access teach
or suggest that a memory access may have taken place.
Id.
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These arguments do not undermine the Examiner’s showing. Uner’s
system specifically discusses directives and commands in context with its
logical and physical memory map system. Uner ¶ 66 (“In one embodiment,
the protection core 114 may reprogram the MMU [(Memory Management
Unit)] from the initial state illustrated in FIG. 4A, and then remap the
memory upon a command, policy violation, random interval, or any
directive to the state shown in FIG. 4B.” (Emphasis added)). As the
Examiner finds, Uner’s system contemplates accessing data when it accesses
memory and alters Uner’s space map via a command or directive. See Final.
Act. 3; Ans. 14–16 (citing Uner, Fig. 4A, Fig. 4B, ¶¶ 28, 65, 66). The
Examiner also persuasively finds that Uner discloses that “an SSE [(Secure
SCADA element)] may read or re-store on a command, which are reads or
writes and thus accesses.” Ans. 15 (citing Uner ¶ 64). SSEs include various
types of memory and processors. See, e.g., Uner ¶¶ 44–47.
Uner specifically teaches “on command . . . the SSE may read the
data, re-encrypt, and re-store . . . with a new key.” Uner ¶ 64 (emphasis
added). Uner also discloses “[w]hen remapping occurs, the original memory
can be left intact, allowing multiple processes to appear to share memory, or
the SSE can randomize, zeroize, or encrypt the memory for later decryption
when the memory is remapped.” Id. ¶ 66. Such reads, randomizing,
zeroing, and encrypting of data necessarily involve memory data accesses in
order to read or manipulate the data, as the Examiner finds. See Ans. 14–16.
In other words, as the Examiner persuasively finds, Uner’s remapping
commands involve “some number of data accesses” and “choosing
remapping for each time a logical memory is accessed is choosing from a
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finite number of identified, predictable solutions, with a reasonable
expectation of success.” Id. at 15.
Appellant does not address with specificity the Examiner’s finding
that Uner’s remapping commands involve “some number of data accesses.”
See Reply Br. 22 (discussing SCADA from “[a]n article in Wikipedia,”
repeating arguments related to a “directive” and other arguments).2 And
Appellant does not challenge the Examiner’s stated motivation for altering
the frequency of remapping as tied to each data access command. See Ans.
14–15; Appeal Br. 20–23; Reply Br. 22–23.
Immediately after Appellant argues “Applicant’s claim 1 recites
‘hiding memory access patterns by altering a logical-to-physical address
space map each time the logical memory is accessed,’” Appellant contends
“Hasbun is really no help insofar as the alteration of the physical address
space each time a logical memory access occurs (‘altering a logical-to-
physical address space map each time the logical memory is accessed’).”
Appeal Br. 22–23. This argument fails to address the Examiner’s finding
that Uner suggests “altering a logical-to-physical address space map each
time the logical memory is accessed,” as discussed above. See Ans. 16
(arguing “such an argument is not relevant because Hasbun is not relied
upon to teach the limitation in the rejection”).

2 Appellant does not provide a citation to the Wikipedia article upon which it
relies and raises it for the first time in the Reply Brief. Accordingly, we do
not consider it. See 37 C.F.R. § 41.41 (b) (1) (“A reply brief shall not
include any new or non-admitted amendment, or any new or non-admitted
affidavit or other Evidence.”).
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Appellant also quotes Hasbun, and argues “packing could be
performed periodically or upon occurrence of an event such as initiation of a
low power mode or completion of an application.” Appeal Br. 22
(Appellant’s emphasis omitted, quoting Hasbun ¶ 14). This argument does
not refer to an explicit limitation in claim 1 and does not point to error in the
Examiner’s rejection. Also, it does not address the Examiner’s finding
based on Uner’s disclosures that suggest altering the address space map at
each command as required by claim 1.
Appellant raises other issues with Hasbun. For example, Appellant
argues in Hasbun’s system,
there is a strong likelihood that at least some physical addresses
may be eliminated entirely, for failure to meet a persistence
threshold, for example. Of course, reducing the amount of
physical memory in use is precisely what Hasbun strives for, in
order to power down unused memory devices and conserve
power in the system under consideration.
Appeal Br. 22. Appellant does not explain how this characterization of
Hasbun relates to the Examiner’s obviousness showing. Appellant does not
explain how claim 1 precludes eliminating some physical addresses or
reducing the size of physical memory. Nothing in claim 1 indicates it does,
as the Examiner argues. See Ans. 17 (“There is nothing in the claims that
exclude the powering down of memory and in fact, such a feature may
benefit the invention in terms of power savings. Indeed, the fact that a
memory is powered down would prevent the allocation of data to said
memory and thereby prevent nefarious actors discerning memory access
patterns to said memory.”).
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Also, claim 1 refers to a “physical address space containing protected
data,” but it does not require protection of data located at all physical
address spaces. See also Spec. ¶ 19 (“In some instances, the protected data
may be stored in a single protected window 132, which may cover a portion
of the external system memory 130 or all of the external system memory
130.” (Emphasis added)).
Setting aside the analogous art arguments discussed below, Appellant
concludes as follows:
None of the cited references disclose or suggest the salient
features of Applicant’s claims 1, 12, or 20. Specifically, whether
considered alone or in combination, Uner and Hasbun do not
disclose, teach, or suggest ‘hiding memory access patterns by
altering a logical-to-physical address space map each time the
logical memory is accessed.’”
Appeal Br. 23.
Contrary to this conclusion, as discussed above, the Examiner finds
persuasively that Uner suggests the “altering” limitation, which defines the
“hiding” limitation. Appellant does not show error in the Examiner’s
findings, which include the predictability of altering the frequency of space
map alterations based on data access commands. Moreover, the
Specification reveals that altering the map dynamically as Uner teaches,
regardless of frequency, hides the pattern, implying no difficulty or
patentable distinction founded upon any difference between frequencies of
alteration:
For maximum protection against traffic analysis, the
remapping may be performed at each and every data access to
the logical address space. However, the remapping may be
performed less frequently. In any event, the remapping is
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dynamic. For instance, the remapping is performed repeatedly
while a program is running.
Spec. ¶ 27.
Appellant also contends “the Hasbun reference simply does not
qualify as prior art under 35 U.S.C. § 103, because it is not analogous to the
invention set forth in claims 1, 12, and 20 in particular.” Appeal Br. 17.3
Appellant contends a reference may be used in an obviousness determination
“only when it is analogous to the claimed invention.” Id. (citing In re Bigio,
381 F.3d 1320, 1325–26 (Fed. Cir. 2004); In re Wood, 599 F.2d 1032, 1036
(CCPA 1979)).
According to Bigio,
[t]wo separate tests define the scope of analogous prior art: (1)
whether the art is from the same field of endeavor, regardless of
the problem addressed and, (2) if the reference is not within the
field of the inventor’s endeavor, whether the reference still is
reasonably pertinent to the particular problem with which the
inventor is involved.
Bigio, 381 F.3d at 1325.
Under Bigio’s first prong, Appellant contends Applicant’s field of
endeavor encompasses the field of “computer security protocol.” Appeal Br.
21. Appellant also argues “the Hasbun reference is directed toward a system
and method for managing volatile memory,” and “[t]his is simply not in the
same field of endeavor as Applicant’s computer system security protocol,
which acts to eliminate viewing of usable patterns during memory access

3 Notwithstanding the order of discussion presented in this Decision, the
panel analyzed the analogous art tests prior to forming the conclusion of
obviousness to avoid repeating unnecessarily what the prior art teaches and
the Specification discloses.
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that might provide sensitive information to an observer upon analysis.”
Reply Br. 20–21.4
The Examiner contends “Applicant’s invention deals with controlling
memory in a computer system and likewise, Hasbun deals with controlling
memory in a computer system. As such, Hasbun is in the same field of
endeavor as Applicant’s invention.” Ans. 14.
The record supports the Examiner. Appellant argues “Applicant’s
invention is directed toward dynamically remapping the logical address
space to the physical address space in response to data accesses to the
logical address space so that useful information can no longer be derived
through analyzing memory access patterns.” Reply Br. 20. So Appellant
agrees that the field of endeavor at least involves “dynamically remapping
the logical address space to the physical address space.” See id. Appellant
also agrees “that the Hasbun reference is directed toward a system and
method for managing volatile memory,” but contends “this is simply not in
the same field of endeavor as Applicant’s computer system security
protocol.” Id. at 20–21.
No reasonable dispute exists here that Hasbun falls in the field of
controlling memory in computers, and more particularly, within that field,
Hasbun involves memory systems that remap address spaces. See Hasbun,
Fig. 1; Reply Br. 20; Ans. 14. As noted above, Appellant agrees “Hasbun
contemplates the concept of a mapping,” Reply Br. 23, and agrees the

4 Appellant acknowledges “[i]t is clear that in rejecting claims 1, 12, and 20
in particular, based upon the selected combination of references, it is the
Examiner’s position that Uner and Hasbun are analogous art.” Appeal Br.
16.
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invention “is directed toward” the field of “dynamically remapping the
logical address space to the physical address space,” id. at 20.
The Specification supports the finding that the field of endeavor
constitutes controlling memory access by remapping. The title of the
invention follows: “DYNAMIC MEMORY ADDRESS REMAPPING IN
COMPUTING SYSTEMS.” Spec. 1. Contrary to Appellant’s position, the
title of the invention does not mention security.
The Specification states “[i]n a computing system, traffic to system
memory may be analyzed to observe memory access patterns. Sensitive
information from these memory access patterns may be deduced.” Spec.
¶ 1. Although this paragraph implicitly raises security issues, in conjunction
with the title, the passage indicates the invention falls more generally into
the field of controlling “traffic to system memory,” as the title indicates and
as the Examiner essentially finds. See Ans. 13. And the Specification states
“[a]s part of managing the data flow, the memory controller 150 is
configured to map and dynamically remap the logical address space to the
physical address space of the external system memory 130.” Spec. ¶ 22. So
the Specification specifically describes “managing data flow” by remapping
logical address spaces in memory, as the Examiner generally finds.
In summarizing the invention, the Specification describes
embodiments that all control traffic to system memory by hiding “memory
access patterns.” Spec. ¶¶ 5–7. All of the embodiments “hid[e] memory
access patterns” by at least “dynamically remapping the logical address
space to the physical address space.” See id. ¶¶ 5–6, see also id. ¶ 7
(“remapping a logical address from a first physical address . . . to a second
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physical address”). This remapping of logical address space involved in all
of the disclosed embodiments further supports the Examiner’s finding that
the field of endeavor includes the field of controlling traffic to memory in
computers in general, and more specifically, controlling the traffic by
remapping memory.
Hasbun falls into this field of endeavor because it also involves
controlling memory by remapping it. In addition, the structure and function
of the invention, namely a logical address memory space, physical memory
space, and logical remapping functionality, reveals that Hasbun’s
structurally and functionally similar logical address memory mapping
system falls into Appellant’s field of endeavor. Compare Hasbun, Figs. 1–3,
with Spec. Fig. 1. As the Examiner shows, Uner’s and Hasbun’s systems
separately, and as combined, implicitly hide memory access patterns. See
Final Act. 4–5; Ans. 14–16, 22; Bigio, 381 F.3d at 1326 (“[T]he Board
concluded that Flemming’s toothbrush was in Bigio’s field of endeavor
because ‘the structural similarities between toothbrushes and small brushes
for hair would have led one of ordinary skill in the art working in the
specific field of hairbrushes to consider all similar brushes including
toothbrushes.’ The Board thus correctly set the field of the invention by
consulting the structure and function of the claimed invention as perceived
by one of ordinary skill in the art.”).
Accordingly, and as described above in analyzing the rejection to
claim 1, the Examiner shows persuasively that Hasbun (and Uner) fall into
Applicant’s field of endeavor. See also Appeal Br. 22 (“Hasbun
contemplates the concept of a mapping.”); supra note 3 (acknowledging the
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Examiner’s implied position that both Uner and Hasbun fall in Appellant’s
field of endeavor). Appellant does not show error in the Examiner’s finding
for the reasons discussed above.
Appellant also raises Bigio’s second prong under the assumption that
Hasbun does not fall in Applicant’s field of endeavor. Appeal Br. 21
(arguing Hasbun “is not” “reasonably pertinent to the problem addressed by
the Applicant”). Appellant explains “Applicant’s invention is directed
toward obviating stealth analysis of traffic to system memory that could lead
to deduction of sensitive information. This is accomplished by remapping
logical addresses to new physical addresses so that a stealth observer can no
longer derive useful information through analyzing memory access patterns”
Id. at 20. In response, “the Examiner has taken the problem to be the more
specific issue of storing protected data at a second physical address while
leaving a logical address space unchanged, which is a specific issue within
the invention to solve.” Ans. 14. The Examiner also contends “Hasbun . . .
was relied upon to solve the specific problem noted above that would have
been faced by the inventor.” Id.
A reference outside an inventor’s field of endeavor is “reasonably
pertinent” only if its subject matter “logically would have commended itself
to an inventor’s attention in considering his problem.” In re Clay, 966 F.2d
656, 659 (Fed. Cir. 1992). Under Clay and In re Ellis, 476 F.2d 1370, 1372
(CCPA 1973), “structural similarities” may provide a useful metric for
determining “reasonably pertinent” prior art:
Here the structural similarities and the functional overlap
between pedestrian gratings and shoe scrapers of type shown by
Trixner are readily apparent. We conclude that, at the very least,
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the arts to which the Schulz and Trixner patents belong are
reasonably pertinent to the art with which appellant’s invention
deals.
Ellis, 476 F.2d at 1372 (1973); see Clay, 966 F.2d at 659 (citing and quoting
Ellis’s structural and functional overlap inquiry with approval in support of
finding a reference “not reasonably pertinent to the particular problem with
which Clay was involved”).5
Recently, our reviewing court held the Board erred by refusing to
consider references of record that “establish the necessary link” in “the
reasonably pertinent test.” Airbus S.A.S. v. Firepass Corp., 941 F.3d 1374,
1382–83 (Fed. Cir. 2019). The court first found substantial evidence to
support the Board’s finding that “a reference [to Kotliar]. . . expressly
directed to exercise equipment [that] fails to mention the word
‘fire’” . . . does not “fall[] within the field of fire prevention and
suppression.” Id. at 1381.
Then, however, the court remanded for the Board to determine if
Kotliar qualifies as analogous art under “the reasonably pertinent test.” Id.
at 1382. The court found that Kotliar discloses “hypoxic atmospheres” and
“enclosed hypoxic environments” and determined that the Board erred by
not considering other references that allegedly “establish[ed] that the use of
normbaric hypoxic atmospheres in enclosed environments was well-known
in the art of fire prevention and suppression at the time of the invention.” Id.

5 Precedent cited here indicates that structural and functional similarities
play a role in both prongs of the analogous art test. See also Deminski, 796
F.2d 436, 442 (Fed. Cir. 1986) (determining that the cited references were
within the same field of endeavor where they “have essentially the same
function and structure”).
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at 1382, 1383 (“These references could lead a reasonable factfinder to
conclude that an ordinarily skilled artisan in the field of fire prevention and
suppression would have looked to Kotliar for its disclosure of a hypoxic
room, even though Kotliar itself is outside the field of endeavor.”). The
court reasoned that “the reasonably pertinent inquiry is inextricably tied to
the knowledge and perspective of a person of ordinary skill in the art at the
time of the invention.” See id. at 1382.
Here, Uner shows that an artisan of ordinary skill would have
understood and been aware of memory remapping systems and their
usefulness in computer security systems. Like the references in Airbus
alleged to establish a link between fire prevention and enclosed hypoxic
atmospheres, Uner establishes a link between computer security and
memory remapping systems. In other words, Uner shows that an artisan of
ordinary skill interested in computer security would have known that
altering logical memory systems relates to the computer security arts and its
problems. See Uner code (57) (“ENHANCED SECURITY SCADA
SYSTEMS AND METHODS”), Fig. 2 (flow diagram including security
policies), Fig. 4 (virtual memory remapping system), ¶¶ 64–66 (same). So
an artisan of ordinary skill, aware of Uner’s memory remapping system as
useful for security in computer systems, reasonably would have consulted
the similar memory mapping system of Hasbun. Compare Uner Fig. 4A and
Fig. 4B and Spec. Fig. 1, with Hasbun, Fig. 1; see Ellis, 476 F.2d at 1372;
Clay, 966 F.2d at 659.
The Examiner persuasively shows that an artisan of ordinary skill
would have consulted Hasbun, because Hasbun relates to a physical
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remapping problem addressed by Applicant, and Hasbun discloses a
structurally and functionally similar logical memory system to the
Specification’s and Uner’s logical memory system. See Final Act. 4 (citing
Hasbun Figs. 1–2, ¶¶ 10, 16–18); Ans. 14 (describing Hasbun’s system as
“storing protected data at a second physical address while leaving a logical
address space unchanged”).
Under analogous circumstances, our reviewing court in ICON
characterized its prior reasoning and holding in Paulsen as follows:
We therefore have concluded, for example [in Paulsen], that an
inventor considering a hinge and latch mechanism for portable
computers would naturally look to references employing other
“housings, hinges, latches, springs, etc.,” which in that case came
from areas such as “a desktop telephone directory, a piano lid, a
kitchen cabinet, a washing machine cabinet, a wooden furniture
cabinet, or a two-part housing for storing audio cassettes.”
In re ICON Health & Fitness, Inc., 496 F.3d 1374, 1382 (Fed. Cir. 2007)
(quoting Paulsen, 30 F.3d 1475, 1481–82 (Fed. Cir. 1994)).
The stated problem facing Applicant here relates to nefarious viewing
of memory access patterns in generic memory systems. See Spec. ¶¶ 1–4;
Appeal Br. 17. The Specification describes the nefarious viewing problem
as arising from memory access and traffic control in generic memory
systems. See id. One disclosed solution involves using a logical memory
system and “altering a logical-to-physical address space map” (as claim 1
specifies). See id. ¶¶ 5–7. The Specification also reveals a narrower
solution that employs both 1) logical address remapping and 2) moving of
data from one physical memory to another while keeping the logical address
unchanged. See Spec. ¶ 7; Appeal Br. App’x (claim 1).
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But as discussed above, the Specification generally describes
embodiments that control traffic with logical memory address systems, as
the title of the Specification further indicates. In ICON, the court reasoned
that even though “Icon’s invention provides a treadmill,” “nothing about
Icon’s folding mechanism requires any particular focus on treadmills”:
Nothing about Icon’s folding mechanism requires any particular
focus on treadmills; it generally addresses problems of
supporting the weight of such a mechanism and providing a
stable resting position. Analogous art to Icon’s application, when
considering the folding mechanism and gas spring limitation,
may come from any area describing hinges, springs, latches,
counterweights, or other similar mechanisms—such as the
folding bed in Teague.
ICON, 496 F.3d at 1380 (noting that “Icon’s invention provides a treadmill
with a folding mechanism and a means for retaining that mechanism in the
folded position”) (emphasis added). Similarly, nothing here about the
Specification requires any “particular focus” on computer security even
though the invention provides computer security.
Even if the rationale of ICON does not apply here, under Airbus, Uner
provides the link to computer security, as discussed above. Also, the stated
nefarious viewing problem leads to underlying problems involved in the
solution, even if the Specification does not explicitly describe all of the
problems facing the Applicant. See Ans. 14 (describing a problem in
memory access systems as addressed by Hasbun); KSR Int’l Co. v. Teleflex
Inc., 550 U.S. 398, 420, 420 (2007) (“[T]he problem motivating the patentee
may be only one of many addressed by the patent’s subject matter” and
“familiar items may have obvious uses beyond their primary purposes.”).
Like the solution to problems with generic memory systems identified in the
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Specification, Hasbun’s system employs, and alters the maps of, logical
memory systems, and in addition, “stor[es] protected data at [a] second
physical address while leaving a logical address space unchanged,” as claim
1 requires. See Final Act. 4; Ans. 14; Hasbun, Fig. 1.
The Specification indicates that “sending data to the external system
memory for storage at the second physical address,” Spec. ¶ 7, and changing
the physical address when the logical address does not change, “cause[s]
data to be written to different physical addresses in the external system
memory 130,” id. ¶ 39. This further “obfuscate[s] memory access patterns,”
providing a more specific solution added to the general solution of mere
remapping as outlined above. Id. Hasbun’s system, therefore, also
obfuscates memory access patterns, because as the Examiner finds, Hasbun
“discloses storing the protected data at the second physical address while
leaving the logical address space unchanged.” Final Act. 4 (citing Hasbun,
claim 2, ¶¶ 10, 14–18, Figs. 1–2). Given Uner’s link between memory
remapping systems and computer security, Hasbun “logically would have
commended itself to an inventor’s attention in considering his problem.”
See In re Clay, 966 F.2d 659.
Moreover, Uner does not describe explicitly how to access physical
data at a first physical data location after remapping a logical memory
address from the first physical data location at Figure 4A to a second
location at Figure 4B. See Final Act. 3–4; Ans. 14; Uner ¶¶ 64–66, Fig. 4A,
Fig. 4B. Accordingly, an artisan of ordinary skill would have turned to
Hasbun to solve a physical data access problem that implicitly faced the
inventors after arriving at its general solution, with motivation to employ
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Hasbun’s similar logical address remapping scheme in Uner’s remapping
system involving an efficient mechanism to access and store data in physical
memory storage. See Final Act. 4.
In summary, a “familiar item[]” like Hasbun’s logical memory system
“ha[s] obvious uses [e.g., in computer security] beyond [its] primary
purposes,” see KSR, 550 U.S. at 420, and also, Hasbun “logically would
have commended itself to an inventor’s attention in considering his
problem,” see Clay, 966 F.2d at 659.
Based on the foregoing discussion, Appellant does not show error in
the Examiner’s findings and determination of the obviousness of claim 1.
As noted above, Appellant does not challenge claims 2–20 independently
from claim 1. Accordingly, claims 2–20 fall with claim 1.
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VI. CONCLUSION
Claims
Rejected
35 U.S.C. § References/Basis  Affirmed Reversed
1–6, 12,
17, 18, 20
103 Uner, Hasbun 1–6, 12, 17,
18, 20

7 103 Uner, Hasbun,
Stefanov
7
8–11, 19 103 Uner, Hasbun,
Mather
8–11, 19
13 103 Uner, Hasbun,
Avudaiyappan
13
14 103 Uner, Hasbun,
Manoharan
14
15 103 Uner, Hasbun,
Chou
15
16 103 Uner, Hasbun,
Chou, Hars
16
Overall
Outcome
1–20
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED