Texas Instruments Incorporated

Patent Trials and Appeals Board

Aug 14, 2020

2019003499 (P.T.A.B. Aug. 14, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/294,711 06/03/2014 Mihir Narendra Mody TI-73828 3522
23494 7590 08/14/2020
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, MS 3999
DALLAS, TX 75265
EXAMINER
MUNG, ON S
ART UNIT PAPER NUMBER
2486
NOTIFICATION DATE DELIVERY MODE
08/14/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MIHIR NARENDRA MODY
Appeal 2019-003499
Application 14/294,711
Technology Center 2400
Before ELENI MANTIS-MERCADER, JOYCE CRAIG, and
MATTHEW J. McNEILL, Administrative Patent Judges.
CRAIG, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject independent claims 1, 17, 23, and 25.2 See
Final Act. 1. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42. Appellant identifies the real party in interest as Texas Instruments
Incorporated of Dallas, Texas, United States of America. Appeal Br. 2.
2 Appellant withdrew claims 2–16, 18–22, 24, and 26. See Amendment dated
July 27, 2018.
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Application 14/294,711

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CLAIMED SUBJECT MATTER
The claims are directed to multi-threading in a video hardware engine.
Claim 1, reproduced below, is illustrative of the claimed subject matter:
1. A video hardware engine comprising:
a video hardware accelerator unit; and
a controller coupled to the video hardware accelerator unit
and configured to operate in an encode mode to:
receive a plurality of frames and encode attributes
associated with each frame of the plurality of frames, each frame
divided in a plurality of slices;
execute a first thread to process the encode attributes
associated with a frame of the plurality of frames to generate
encode parameters associated with the frame;
execute a second thread to configure the video hardware
accelerator unit to process the frame based on the encode
parameters to generate an output; and
execute the first thread to process the output of the video
hardware accelerator unit to generate a compressed bit-stream
and an encode status.

Appeal Br. 10.
REJECTION
Claims 1, 17, 23, and 25 stand rejected under 35 U.S.C. § 103 as
unpatentable over the combination of Xi et al. (US 2013/0223532 A1,
published Aug. 29, 2013) (“Xi”) and Parameswaran et al. (US 2005/0262510
A1, published Nov. 24, 2005) (“Parameswaran”). Final Act. 4.
ANALYSIS
We have reviewed the rejections of claims 1, 17, 23, and 25 in light of
Appellant’s arguments that the Examiner erred. We have considered in this
decision only those arguments Appellant actually raised in the Briefs. Any
other arguments Appellant could have made, but chose not to make, in the
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Application 14/294,711

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Briefs are waived. See 37 C.F.R. § 41.37(c)(1)(iv). Appellant’s arguments
are not persuasive of error. We agree with and adopt as our own the
Examiner’s findings of facts and conclusions as set forth in the Answer and
in the Action from which this appeal was taken. We provide the following
explanation for emphasis.
With respect to independent claim 1, Appellant contends the cited
portions of Xi and Parameswaran fail to teach or suggest,
a controller coupled to the video hardware accelerator
unit and configured to operate in an encode mode to[]
receive a plurality of frames and encode attributes
associated with each frame of the plurality of frames, each
frame divided in a plurality of slices;
execute a first thread to process the encode attributes
associated with a frame of the plurality of frames to generate
encode parameters associated with the frame;
execute a second thread to configure the video hardware
accelerator unit to process the frame based on the encode
parameters to generate an output; and
execute the first thread to process the output of the video
hardware accelerator unit to generate a compressed bit-stream
and an encode status,
as recited in claim 1. Appeal Br. 6. Appellant argues that the proposed
modification of Xi’s video engine with the threads of Parameswaran “does
not necessarily result in the particular configuration of threads recited in
claim 1.” Id.
We are not persuaded that the Examiner erred. Rule 41.37 “require[s]
more substantive arguments in an appeal brief than a mere recitation of the
claim elements and a naked assertion that the corresponding elements were
not found in the prior art.” In re Lovin, 652 F.3d 1349, 1357 (Fed. Cir.
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Application 14/294,711

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2011). Appellant’s arguments are largely conclusory and fail to address the
Examiner’s factual findings.
With regard to the recited “first thread,” the Examiner finds that Xi
teaches that processing unit 110 executes instructions (i.e., the claimed
thread) to read encoding parameters and RLL codes from external storage
unit 130 to perform entropy encoding and output a video bitstream of an
image. Ans. 4 (Mar. 19, 2019). The Examiner finds that a bit rate control
program may indicate that processing unit 110 may calculate quantization
parameters of the next frame according to encoding results of the current
frame, the total bit rate, and the frame rate. Id. (citing Xi Fig. 1, ¶ 35). The
Examiner further finds that Xi’s disclosed bite rate, RLL codes and
quantization parameters are the same as the claimed encode parameters
because they are used to encode a frame. Id. The Examiner also finds that,
after encoding, processing unit 110 further executes an encoding post
processing program, which outputs a current frame bit stream to the
encoding post-processing program, as illustrated in Figure 1 of Xi. Ans. 4–5.
The Examiner finds that the output includes results of the current frame,
total bit rate, frame rate, results from boundary extension etc., which may
indicate the coding status. Id. (citing Xi ¶ 35).
Appellant has not persuasively rebutted the Examiner’s factual
findings with regard to Xi’s teaching the “first thread” limitations,
summarized above.
With regard to the recited “second thread,” the Examiner finds that
controller 110 of Xi sends instructions to activate the hardware accelerator.
Ans. 4 (citing ¶ 31). The Examiner further finds that Xi’s acceleration
hardware performs coding using the macroblock encoding information
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including quantization parameters written to the accelerator by the
processing unit. Id. (citing Xi Fig. 1, ¶ 36).
Appellant has not persuasively rebutted the Examiner’s factual
findings with regard to Xi’s teaching the “second thread” limitation,
summarized above.
The Examiner further finds that, although Xi does not explicitly use
the terms “first thread” and “second thread,” Xi teaches a processing unit for
executing predefined tasks similar to the thread processes recited in the
claim. Ans. 5. According to the Examiner, an artisan of ordinary skill would
have recognized that the multiple instructions executed by Xi’s processor
110 are threads. Id. In addition, the Examiner finds that Parameswaran
explicitly discloses a multi-thread process for encoding video, wherein the
accelerator hardware is configured to process parameters in a separate
pipelined threads. Id. (citing Parameswaran Fig. 6).
Appellant has not persuasively rebutted the Examiner’s factual
findings with regard to knowledge in the art or Parameswaran’s teachings,
summarized above.
For these reasons, we are not persuaded that the Examiner errs in
finding the combination of Xi and Parameswaran teaches or suggests the
disputed limitations of claim 1.
Appellant next argues that the Examiner erred in combining the
teachings of Xi and Parameswaran. Appeal Br. 7. Appellant argues that “the
Examiner’s purported reason for modification describes a reason for arriving
at using multiple threads with an accelerator, but does not support a
modification that would arrive at the specific thread configuration described
in claim 1.” Id.
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We are not persuaded that the Examiner errs in combining the
references. The Examiner finds that one of ordinary skill in the art would
have modified Xi “to include multiple threads with the accelerator, as
disclosed by Parameswaran, for the purpose of minimiz[ing] the idle time of
coprocessors and efficient allocating hardware resources during video
encoding.” Ans. 5 (citing Parameswaran ¶ 75). Thus, the Examiner provides
“articulated reasoning with some rational underpinning to support the legal
conclusion of obviousness.” In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006).
Appellant does not persuasively rebut the Examiner’s reasoning. Rather,
Appellant argues that the Examiner’s characterization of Xi as teaching
“predefined tasks” is in error because Xi does not use the term “predefined
tasks.” Reply Br. 3–4. Appellant also argues that the Examiner’s
characterization of Parameswaran as teaching an accelerometer is in error
because Parameswaran describes no such device. Reply Br. 4.
Appellant’s arguments do not persuade us that the Examiner errs in
combining Xi and Parameswaran. Appellant presents no legal authority that
requires the Examiner’s description of the prior art in ipsis verbis (i.e., “in
the same words”) as used in the prior art. Moreover, the Examiner identified
an “accelerator” in Parameswaran (Ans. 5), not an “accelerometer,” as
Appellant contends (Reply Br. 4).
For these reasons, we are not persuaded that the Examiner errs in
combining the Xi’s processing unit with Parameswaran’s threads.
Accordingly, we sustain the Examiner’s § 103 rejection of
independent claim 1, as well as the Examiner’s § 103 rejection of
independent claims 17, 23, and 25, not argued separately with particularity.
See Appeal Br. 7–9; Reply Br. 4.
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DECISION
We affirm the decision of the Examiner rejecting claims 1, 17, 23, and
25.
DECISION SUMMARY
Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1, 17, 23, 25 103 Xi, Parameswaran 1, 17, 23, 25

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED