TEXAS INSTRUMENTS INCORPORATED

Patent Trials and Appeals Board

May 6, 2021

2020000185 (P.T.A.B. May. 6, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/873,758 01/17/2018 Ankur CHAUHAN TI-78301 7442
23494 7590 05/06/2021
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, MS 3999
DALLAS, TX 75265
EXAMINER
DONOVAN, LINCOLN D
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
05/06/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ANKUR CHAUHAN and
ABHRARUP BARMAN ROY
Appeal 2020-000185
Application 15/873,758
Technology Center 2800

Before BEVERLY A. FRANKLIN, LINDA M. GAUDETTE, and
RAE LYNN P. GUEST, Administrative Patent Judges.

GUEST, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–4, 8–10, 13–15, 21, 22, and 24.2 We
have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.3

1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42(a). Appellant identifies the real party in interest as Texas Instruments
Incorporated. Appeal Br. 2.
2 The Examiner determined that claims 16–20 are allowable, and indicated
that dependent claims 5–7, 11, 12, and 23, which depend from rejected
claims, would be allowable if rewritten in independent form. Final Act. 1.
3 In our decision, we refer to the Specification filed Jan. 17, 2018 (“Spec.”);
the Final Office Action dated Feb. 15, 2019 (“Final Act.”); the Appeal Brief
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CLAIMED SUBJECT MATTER
The invention is directed to a device which generates reference signals
using internal loads. See Spec. ¶ 3. According to the Specification, the
invention is an integrated circuit (“IC”) device that detects and alerts to
insufficiently resistive external loads or “pin shorts” that can damage the IC.
Spec. ¶ 11. The detection occurs by comparing the voltage of an external
load with that of a known reference voltage of an internal load and sending a
signal if the voltages differ outside of a predetermined range (generally plus
or minus 15%). Spec. ¶¶ 12, 16.
Claims 1 and 9, reproduced below, are illustrative of the claimed
subject matter:
1. A device comprising:
a first driver coupled to a first node, the first node to
couple to a first load external to the device;
a second driver coupled to a second node, the second
node coupled to a second load internal to the device; and
a comparison circuit having an inverting input coupled to
the first node and a noninverting input coupled to the second
node,
wherein sizes of the second driver and the second load
are configured proportionately to sizes of the first driver and the
first load, respectively.

9. A device comprising:
a first transistor having a terminal coupled to a first node,
the first node to couple to
a first load external to the device;
a second transistor having a terminal coupled to a second
node, the second node coupled to a second load internal to the

filed July 3, 2019 (“Appeal Br.”); the Examiner’s Answer dated Aug. 6,
2019 (“Ans.”); and the Reply Brief filed Oct. 4, 2019 (“Reply Br.”).
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device, wherein gates of the first and second transistors couple
to each other;
a voltage offset circuit coupled to at least one of the first
and second nodes;
a comparison circuit coupled to the voltage offset circuit
and to one of the first and second nodes; and
a de-glitch circuit coupled to an output of the comparison
circuit.

Appeal Br. 16–18 (Claims App.).
REFERENCE
The Examiner relies upon the following prior art:
Name Reference Date
Abouda US 2011/0001486 A1 Jan. 6, 2011
REJECTION
1. Claims 1–4, 8–10, 13–15, 21, 22, and 24 are rejected under 35
U.S.C. § 103 as being unpatentable over Abouda.
OPINION
We review the appealed rejections for error based upon the issues
identified by Appellant and in light of the arguments and evidence produced
thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential),
cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011)
(“[I]t has long been the Board’s practice to require an applicant to identify
the alleged error in the [E]xaminer’s rejections.”). After considering the
evidence presented in this Appeal and each of Appellant’s arguments, we
affirm the Examiner’s decision to reject the claims on appeal.
Appellant presents arguments only for independent claims 1, 9, and
21. See Appeal Br. 5. Accordingly, we limit our discussion below to the
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rejection of claims 1, 9, and 21, and the dependent claims on appeal stand or
fall with their respective independent claim.
Claims 1 and 21
The Examiner finds that Abouda teaches the structural elements
recited as comprising the device in independent claim 1; however, Abouda
fails to teach that the “sizes of the second driver and the second load are
configured proportionately to sizes of the first driver and the first load,
respectively,” as recited in claim 1. See Final Act. 8. The Examiner finds this
limitation not expressly disclosed in Abouda, but that it would have been
obvious, as a matter of design choice, to size the drivers and loads as
claimed since “[a] change in size is generally recognized as being within the
level of ordinary skill in the art.” Id. (citing In re Rose, 220 F.2d 459 (CCPA
1955)); Ans. 3.
The Examiner further points out that Abouda (¶ 13) teaches that “the
switches 107, 109, 111 and 113 may for example be transistor switches such
as switches capable of being incorporated in a semiconductor integrated
circuit, e.g. power MOSFET (metal-oxide-semiconductor field effect
transistor) switches” and that the “loads 123 to 129 may for example be
electrical lights such as light bulbs or light emitting diodes, or other
electrically driven components such as in a motor vehicle or other
application host.” Final Act. 2; Ans. 8. Therefore, the Examiner concludes
that any person having ordinary skill in the art would have easily recognized
that “any well-known switch and load circuitry would have been obvious”
because “drivers and loads of various sizes are not considered beyond the
scope of Abouda” and “[t]he selection of a particular value or values within
a broad range of acceptable values relates only to a specific-for-broad
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substitution.” Id.; Ans. 8. Moreover, the Examiner finds that “when the first
and second switches are identical and the first and second loads are identical,
the sizes of the second driver and second load have a 1:1 proportion to the
sizes of the first driver and first load, respectively.” Ans. 9.
Appellant contends that the Examiner fails to provide any factual or
rational underpinning for finding the limitation “would have been an
obvious matter of design choice” and that the proportionality feature is not a
mere change in size of the components as it is based on the sizes of the first
driver and the first load. Appeal Br. 5–6. Specifically, Appellant argues the
Examiner never found a reason “to resize any of the Abouda transistors.”
Appeal Br. 8.
Appellant’s arguments are not persuasive of error in the Examiner’s
rejection of claim 1. “[A]s an initial matter, the PTO applies to the verbiage
of the proposed claims the broadest reasonable meaning of the words in their
ordinary usage as they would be understood by one of ordinary skill in the
art, taking into account whatever enlightenment by way of definitions or
otherwise that may be afforded by the written description contained in the
applicant’s specification.” In re Morris, 127 F.3d 1048, 1054 (Fed. Cir.
1997). We, as did the Examiner, apply the broadest ordinary meaning of the
phrase “configured proportionately” as the Appellant has not directed us to
language in the Specification that would inform us as to another specific
meaning.4

4 We note that the Specification describes that the second driver and second
load are either “replicas” or “scaled-down versions” of the first driver and a
first expected load but “are scaled proportionately so that . . . the voltages at
the nodes . . . are approximately equal,” where “approximate” is “plus or
minus 15%.” Spec. ¶¶ 16–17 and 19. However, our reviewing court has
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As such, the Examiner found that in choosing drivers and loads based
on the teachings of Abouda, the skilled artisan would employ identical first
and second drivers and loads (i.e., configured with 1:1 proportionality) or
different first and second drivers and loads (i.e., configured with some other
nonspecific “proportionality”). See Ans. 9. Therefore, we agree with the
Examiner that Abouda does not need to be modified in order to teach the
limitation of claim 1. Final Act. 4.
Thus, Appellant has not shown that the Examiner misinterpreted the
term “configured proportionately,” that the Examiner erred in finding that
one of ordinary skill in the art would have been motivated to modify the
explicit teachings of Abouda by choosing the size of the first and second
drivers and first and second loads so they are “configured proportionately,”
and that Examiner otherwise erred in rejecting claim 1 as obvious and
unpatentable over the teachings of Abouda.
The arguments discussed above regarding independent claim 1, were
also applied to independent claim 21 by both Appellant and the Examiner.
See Final Act. 10; Appeal Br. 10; Ans. 7–9. Appellant’s arguments are also
not persuasive of the error in the Examiner’s rejection of claim 21.

counseled that, absent claim language carrying a narrow meaning, the
USPTO should only limit broad claim terms based on the specification when
those sources expressly disclaim the broader definition. In re Bigio, 381 F.3d
1320, 1324–25 (Fed. Cir. 2004). See also In re Van Geuns, 988 F.2d 1181,
1184 (Fed. Cir. 1993) (“[L]imitations are not to be read into the claims from
the specification.”); Phillips v. AWH Corp., 415 F.3d 1303, 1323 (Fed. Cir.
2005) (en banc) (“[A]lthough the specification often describes very specific
embodiments of the invention, we have repeatedly warned against confining
the claims to those embodiments.”). As pointed out by the Examiner, the
recitations of claim 1 do not require either direct 1:1 proportionality or
voltages to be within any particular range, e.g., plus or minus 15%.
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Claim 9
The Examiner finds that Abouda teaches the structural elements
recited as comprising the device in independent claim 9 with respect to
reference numerals of Figure 1 of Abouda, reproduced below, with our
annotations.

Figure 1 of Abouda depicts a block schematic diagram of an
illustrative apparatus 100 for electrical power delivery and fault diagnosis,
with annotations showing our understanding of the Examiner’s findings.
Abouda ¶¶ 7, 13.
The Examiner explains that a “node which receives Vpwr” is a first
node, switch 107 is a first transistor coupled to the Vpwr-receiving first
node, and load 123 is a first load. Final Act. 9; Ans. 4–5. The Examiner has
also interpreted switch 109 as a second transistor coupled to a second node
117 and a second load 125. Id.; Ans. 4–5. The Examiner further finds the
gates of the first and second transistors (switches 107 and 109) are coupled
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to each other via controller 103 and control logic 101 and that switch 111 is
a voltage offset circuit coupled, at least, to the Vpwr-receiving first node.
Id.; Ans. 4–5. Abouda also teaches a comparison circuit 301, including
detectors 131, 133, 135, 137, controller 103, and control logic 101, coupled
to the voltage offset circuit 111 and to one of the Vpwr-receiving first node
and second node 117. Id.; Ans. 4–5.
Appellant contends the Examiner erred in finding that the claim term
“internal load” reads on Abouda’s load 125, and the claim term “external
load” reads on Abouda’s load 123, because Abouda has not identified any of
the loads 123–129 as internal to the apparatus 100. Final Act. 5; Appeal Br.
11. Appellant also contends the control terminals of switch 107 and switch
109 are not “gates . . . couple[d] to each other,” as recited in the claim, but
instead are coupled to the control logic 101, which provides individual and
separate controls to switches 107 and 109 and to couple these control
terminals together would render the control logic 101 inoperable or
unsatisfactory for its intended purpose. Id.; Appeal Br. 11. Citing In re
Power Integrations, Inc., 884 F.3d 1370 (Fed. Cir. 2018), Appellant argued
the Examiner used an unreasonably broad interpretation of “couple.” Id.;
Appeal Br. 11–12. Appellant further contends the Examiner has not
provided any explanation on how switch 111 might offset any voltage, as
Abouda does not explicitly describe switch 111 as a voltage offset circuit or
as having any such function. Final Act. 6; Appeal Br. 13.
Appellant’s arguments are not persuasive of error in the Examiner’s
rejection of claim 9. Appellant has not pointed to any disclosures in the
Specification nor do the claims give any reference by which “internal load”
and “external load” are designated or distinguished in the device recited in
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claim 9. Without such limitations in the claims or further guidance provided
by the Specification, the Appellant has shown no structural distinction
between a load that is “internal” or “external.” Indeed, the Specification
describes both the external and internal load as having the exact same
structure, namely that either “may be any suitable type of load, including a
resistor, a capacitor, an inductor, or any other load.” Spec. ¶¶ 14, 15.5 Thus,
we agree with the Examiner’s application of Abouda’s load 123 as “internal”
and load 125 as “external,” since the same structural type of load may be
either without any clear structural distinction.
The Examiner explains that coupled in claim 1 is not identical in
scope to “directly coupled” or “directly connected” in that, under the
broadest reasonable interpretation of “coupled,” circuit elements A and B are
coupled if a change in the output of A cause a change in the output of B.
Final Act. 6; Ans. 11–12.
Appellant's reliance on Power Integrations, supra, is misplaced.
Contrary to Appellant’s position, Power Integrations did not lay down a
hard and fast rule that electronically “coupled” must always be construed
such that components are immediately adjacent to each other without any
intermediate components whatsoever. Indeed, in Power Integrations, the
claim recited not only that a digital to analog converter was coupled to a

5 We note the Specification and the claims are entirely silent, and Appellant
has not explained, how the loads are “internal” or “external” and in what
aspect, e.g., to a housing, a specific feature or structure, a device, etc., in
order to clearly distinguish a load as either “external” or “internal.”
Moreover, should Appellant contend that a load is external to the claimed
device, by definition, the device cannot comprise the external load, as is
recited in claim 9. Such an interpretation would render the claim indefinite.
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counter, but also that “the counter caus[ed] the digital to analog converter to
adjust the control input and to vary the switching frequency of the power
supply.” Power Integrations, 884 F.3d at 1375. The Court held that the
Board’s interpretation of the term “coupled” in that case rendered the
recitation that all the components were in a “circuit” superfluous and ignored
the functional requirements and benefits specifically described in the
Specification. Id. at 1376. Here, however, claim 9 recites only the first and
second transistors independently are present in “a device” and the only
structural way they are present are via “coupling” (i.e., in the broadest sense,
in a circuit) to each other and to first and second nodes, respectively.
Appellant has not shown that the broadest meaning of the term “couple”
renders any other claim term superfluous or is not supported by the
Specification.6
Further, the Examiner explains that Abouda does teach a functional
coupling of the first and second transistors in that control logic 101 requires
a power supply to generate the plurality of output signals to each switch,
including 107 and 109. Final Act. 6. The gates of both switches 107 and 109
are provided with an output signal from control logic 101 generated using
the power supply voltage of the control logic and a node (not shown), at
which the control logic 101 receives the voltage, is coupled to the gates of

6 While the Specification may depict first and second transistors coupled
directly (or “tied together”) to each other, as shown in Figures 2 and 3 (see
also Spec. ¶¶ 18, 22), Figure 1 shows no such arrangement, indicating all
embodiments do not encompass that arrangement, and the claim recites no
particular structure or function that would require this type of tying together
of the first and second transistors. We decline to read into the claims the
particular “tied together” structure of Figures 2 and 3, without a basis to do
so.
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switches 107 and 109, as well as switches 111 and 113. Id. Therefore, the
gates of switches 107 and 109 are coupled by that node. Id. Alternatively,
the Examiner explains that Abouda teaches the gates of switches 107 and
109 are coupled via the use of a feedback loop, such that “the state of the
signals at [nodes] 115 and 117 determine the values of the control signals
output [via controller 103 and control logic 101] to [switches] 107 and 109.”
Ans. 11. Appellant has shown no error in the Examiner’s findings.
We find it of no moment that Abouda does not describe switch 111 as
a “voltage offset circuit.” The Examiner determined the broadest reasonable
interpretation of the claim language to be “any circuit which provides an
offset to a voltage input thereto and would not include any circuit that fails
to offset a voltage input thereto (such as a unity gain amplifier or any type of
phase shifting circuit).” Ans. 13. The Examiner points out a transistor such
as switch 111 has an inherent voltage drop when in a conducting state. Final
Act. 7; Ans. 13. In addition, the Examiner explains the voltage input to load
127 is offset from the Vpwr voltage input to switch 111. Final Act. 6. Thus,
the claim term “voltage offset circuit” reads on Abouda’s switch 111.
The Appellant has failed to provide any definition in the claims or in
the Specification which distinguishes the recited “voltage offset circuit”
from the interpretation and findings set forth by the Examiner. See Appeal
Br. 13; Reply Br. 5–6. Accordingly, the Appellant’s arguments show no
error in the Examiner’s rejection.
CONCLUSION
The Examiner’s rejection is affirmed.
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DECISION SUMMARY
In summary:
Claim(s)
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1–4, 8–10,
13–15, 21,
22, 24
103 Abouda 1–4, 8–10,
13–15, 21,
22, 24

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv) (2018).
AFFIRMED