STMICROELECTRONICS (ROUSSET) SAS

Patent Trials and Appeals Board

Oct 20, 2020

2019003675 (P.T.A.B. Oct. 20, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/423,479 02/02/2017 Gilles Bas 10RO084US02/813063.416D1 4315
38106 7590 10/20/2020
Seed IP Law Group LLP/ST (EP ORIGINATING)
701 FIFTH AVENUE, SUITE 5400
SEATTLE, WA 98104-7092
EXAMINER
YU, LIHONG
ART UNIT PAPER NUMBER
2631
NOTIFICATION DATE DELIVERY MODE
10/20/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
USPTOeAction@SeedIP.com
pairlinkdktg@seedip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte GILLES BAS, HERVÉ CHALOPIN, and FRANÇOIS TAILLIET
____________

Appeal 2019-003675
Application 15/423,479
Technology Center 2600
____________

Before KEVIN F. TURNER, BETH Z. SHAW, and
STEPHEN E. BELISLE, Administrative Patent Judges.

BELISLE, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1–20. Appeal Br. 10. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

1 Throughout this Decision, we use the word “Appellant” to refer to
“applicant” as defined in 37 C.F.R. § 1.42 (2018). Appellant identifies the
real party in interest as STMICROELECTRONICS (ROUSSET) SAS.
Appeal Br. 2.
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Application 15/423,479

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STATEMENT OF THE CASE
The Claimed Invention
Appellant’s invention generally relates to “[a] method to transmit data
over a single-wire bus wherein a first communication channel is defined by
pulses of different durations according to the state of the transmitted bit and
depending on a reference duration, and a second communication channel is
defined by the reference duration.” Spec., Abstract.
Claim 1, reproduced below, is illustrative of the subject matter on
appeal:
1. A method to transmit data on a single-wire bus,
comprising:
transmitting first channel data on the single-wire bus by
transmitting data pulses having data pulse durations based on
first channel data values and on reference pulse durations; and
transmitting second channel data on the single-wire bus by
transmitting reference pulses having the reference pulse
durations, wherein the reference pulse durations are based on
second channel data values, and wherein various ones of said
reference pulse durations are variable during transmission of the
first and second channel data values.
Appeal Br. 25 (Claims App.).
The Applied References
The Examiner relies on the following references as evidence of
unpatentability of the claims on appeal:
Dunstan US 6,532,506 B1 Mar. 11, 2003
Wada US 2006/0239693 A1 Oct. 26, 2006
Lee US 2010/0308838 A1 Dec. 9, 2010
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The Examiner’s Rejections
The Examiner made the following rejections of the claims on appeal:
Claims 1–9 and 11–20 stand rejected under pre-AIA 35 U.S.C.
§ 103(a) as being unpatentable over the combination of Dunstan and Wada.
Final Act. 4–9.
Claim 10 stands rejected under pre-AIA 35 U.S.C. § 103(a) as being
unpatentable over the combination of Dunstan, Wada, and Lee. Final Act. 9.
We note that the Examiner also objected to claims 2–8, 10–12, and
14–20 due to certain “informalities.” Objections or other requirements
imposed by an Examiner are reviewed by way of a petition to the Director
under Rule 181. 37 C.F.R. §§ 1.113, 1.181. As such, we do not address
these objections herein.
ANALYSIS2
Appellant disputes the Examiner’s findings that the various
combinations of Dunstan, Wada, and Lee render obvious claims 1–20.
Appeal Br. 12–23; Reply Br. 2–7.
Appellant argues, inter alia, that the cited art, particularly Dunstan,
does not teach “transmitting second channel data on the single-wire bus by
transmitting reference pulses having the reference pulse durations, wherein
the reference pulse durations are based on second channel data values,” as

2 Throughout this Decision, we have considered Appellant’s Appeal Brief
filed October 15, 2018 (“Appeal Br.”); Appellant’s Amended Appeal Brief
filed November 21, 2018 (“Amended Appeal Br.”); Appellant’s Reply Brief
filed April 5, 2019 (“Reply Br.”); the Examiner’s Answer mailed
February 7, 2019 (“Ans.”); the Final Office Action mailed May 11, 2018
(“Final Act.”); and Appellant’s Specification filed February 2, 2017
(“Spec.”).
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recited, for example, in independent claim 1. Appeal Br. 20–21; Reply
Br. 4–5. On the present record, we find Appellant’s argument persuasive, as
discussed below. We turn first to the teachings of Dunstan.
Dunstan generally relates “to the use of a positive logic single wire
bus for communication between devices (e.g., a host and a battery) and to
bus speed negotiation schemes usable with one-wire or multi-wire buses.”
Dunstan, 1:7–13. Exemplary activity or communication on the single wire
bus between a master and a slave device is represented in Figure 2,
reproduced below. Dunstan, 2:25–26, Fig. 2.

Figure 2 illustrates a timing diagram for activity on
the single wire bus.
Dunstan, 4:18–19, Fig. 2. Dunstan discloses “[t]he timing of activity on the
bus typically includes a start period, a message transfer period, and a stop
period,” and “if a device (e.g., a master) wishes to use the bus after the bus
has been idle, the device drives the bus high [as shown by 4 clock cycles of
wakeup pulse 101A] followed by a series of short [N synchronization
pulses 101B] on the bus as shown in start period 101.” Id., 4:19–45. Start
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period 101 ends with the device pulling the bus low for 2 clock cycles. Id.,
4:45–48. Dunstan further discloses:
After start period 101, when the devices on the bus are powered
up (e.g., after start period 101), a master on the bus drives the bus
high for a period of time. In one embodiment, this period of time
is 1 clock phase and is equal to one-third of a clock cycle. In one
embodiment, this first time period may be five microseconds. As
described above, the rising edge of the pulse signals the start of
a bit. Following this first time period, either the master (or
another master) or a slave will pull the bus down or maintain the
bus high for a time period to signal a logic zero or a logic one,
respectively.
Id., 4:55–64.
The Examiner finds that Dunstan’s setting of a reference pulse
duration teaches the second channel data limitation at issue. In particular,
the Examiner finds:
[Dunstan’s] master device transmits second channel signal as
“a master on the bus drives the bus high for a period of time. In
one embodiment, this period of time is 1 clock phase and is equal
to one-third of a clock cycle” (see Dunstan at col. 4, lines 55-59).
Dunstan teaches that the “clock cycle” is a pulse with a rising
edge, and the clock cycle is used to determine whether a
transmission signal is a “1” bit or a “0” bit (see Dunstan at Fig. 1
and col. 3, lines 28-50). Therefore, Dunstan’s “clock cycle”
reads on the Applicant’s “a common reference pulse”.
Ans. 3; see Ans. 5 (“[T]he second channel signal is ‘a master on the bus
drives the bus high for a period of time.’”); Ans. 6 (“Dunstan discloses
‘l clock phase’ is transmitted by the master device, and ‘the clock phases
need not be equal in size’. The clock phases are not static and have values.
Therefore, it is reasonable to read Dunstan’s clock phases on the Applicant’s
‘second channel data’.”) (citations omitted); see also Final Act. 4–5.
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Appellant argues that “the Examiner is either taking an unreasonably
broad view of the term, channel data, which is unsupported in the present
specification or anywhere else, or the Examiner is ignoring the term
altogether.” Reply Br. 3. Appellant argues that “[w]hile the Examiner
accurately describes how Dunstan sets the duration of his reference pulse
with respect to a clock cycle, there is no teaching found whatsoever in
Dunstan that this information is a second channel of data.” Reply Br. 3; see
Reply Br. 4 (“[N]egotiation of a reference pulse duration does not teach the
claimed second channel data.”); see Appeal Br. 12–18, 20–21. Appellant
also argues that the Examiner’s reading of Dunstan’s clock phases on
Appellant’s second channel data is “nothing more than an unsupported
conclusion.” Reply Br. 5.
We find Appellant’s argument persuasive, and agree that the
Examiner has not provided sufficient evidence or technical reasoning to
show how Dunstan teaches transmitting second channel data on a single-
wire bus by transmitting reference pulses having reference pulse durations,
wherein the reference pulse durations are based on second channel data
values. For example, although Dunstan describes use of a clock cycle and
selection of clock phases (see Dunstan col. 3:36–65), the rejection lacks
sufficient explanation of how the clock cycle or selection between clock
phases, i.e., reference pulse duration, is based on the rising edge of the clock
pulse, i.e., second channel data value. We also note that although Dunstan’s
Figure 2 (reproduced above) shows a “message [or data] transfer period” for
transmitting an “example byte of data” and “n-bytes of add[itional] data”
(e.g., first channel data), the Examiner does not sufficiently demonstrate
how Figure 2 or its related description likewise teaches transmitting the
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claimed second channel data, particularly where Figure 2 only denotes, at
least on its face, transmitting a single form of channel data. See Dunstan,
col. 4:18–48, Figs. 1–2. The Examiner also has not shown how the other
cited art, namely Wada and Lee, remedies this deficiency. Because we find
this issue dispositive here, we do not address Appellant’s other arguments.
Accordingly, we do not sustain the Examiner’s rejection under pre-
AIA 35 U.S.C. § 103(a) of independent claim 1. We also do not sustain the
Examiner’s rejection under pre-AIA 35 U.S.C. § 103(a) of independent
claims 9 and 13, which recite commensurate limitations. Additionally, we
do not sustain the Examiner’s rejection under pre-AIA 35 U.S.C. § 103(a) of
claims 2–8, 10–12, and 14–20, which depend therefrom.
DECISION SUMMARY
In summary:
Claims
Rejected
pre-AIA
35 U.S.C. §
Reference(s)/
Basis Affirmed Reversed
1–9, 11–20 103(a) Dunstan, Wada 1–9, 11–20
10 103(a) Dunstan, Wada,
Lee
10
Overall
Outcome
1–20

REVERSED