Smart Modular Technologies Inc.v.Netlist, Inc.

Patent Trial and Appeal Board

Mar 13, 2015

13183253 (P.T.A.B. Mar. 13, 2015)

Trials@uspto.gov Paper 12
Tel: 571-272-7822 Entered: March 13, 2015

UNITED STATES PATENT AND TRADEMARK OFFICE
_______________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
_______________

SMART MODULAR TECHNOLOGIES INC.,
Petitioner,
v.
NETLIST, INC.,
Patent Owner.
_______________

Case IPR2014-01375
Patent 8,359,501 B1
_______________

Before LINDA M. GAUDETTE, BRYAN F. MOORE, and
MATTHEW R. CLEMENTS, Administrative Patent Judges.

MOORE, Administrative Patent Judge.

DECISION
Denying Institution of Inter Partes Review
37 C.F.R. § 42.108

IPR2014-01375
Patent 8, 359,501 B1

2

I. INTRODUCTION
Smart Modular Technologies Inc. (“Petitioner”) filed a Petition
(Paper 7, Corrected Petition (“Pet.”)) to institute an inter partes review of
claims 1–20 (the “challenged claims”) of U.S. Patent No. 8,359,501 B1 (Ex.
1008, “the ’501 patent”). See 35 U.S.C. §§ 311–319. Netlist, Inc. (“Patent
Owner”) filed a Preliminary Response (Paper 10, “Prelim. Resp.”). We have
jurisdiction under 35 U.S.C. § 314, which provides that an inter
partes review may not be instituted “unless . . . there is a reasonable
likelihood that the petitioner would prevail with respect to at least 1 of the
claims challenged in the petition.” Upon consideration of the Petition and
Patent Owner’s Preliminary Response, we determine Petitioner has not
established a reasonable likelihood that it would prevail in showing the
unpatentability of at least one of the challenged claims. We therefore
decline to institute an inter partes review as to claims 1–20.
II. BACKGROUND
A. Related Matters
The ’501 patent is also the subject of Sandisk Corp. v. Netlist, Inc.,
Case IPR2014-00971 (PTAB), wherein trial was instituted on claims 1–
20. IPR2014-00971, Paper 12. Contemporaneous with the instant Petition,
Petitioner also filed a second petition for inter partes review of the ’501
patent: Smart Modular Technologies Inc. v. Netlist, Inc., Case IPR2014-
01374 (PTAB). Also contemporaneous with the instant Petition, Petitioner
filed two petitions for inter partes review of U.S. Patent No. 8,001,434 (“the
’434 patent”), to which the ’501 patent claims priority: Smart Modular
IPR2014-01375
Patent 8, 359,501 B1

3

Technologies Inc. v. Netlist, Inc., Cases IPR2014-01372 and IPR2014-01373
(PTAB).
B. The ’501 Patent (Ex. 1008)
The ’501 patent relates to self-testing electronic memory modules.
Ex. 1008, 1:26–27. A block diagram of an exemplary self-testing memory
module is shown in Figure 3 of the ’501 patent, reproduced below.
As illustrated in Figure 3, above, “memory module 10 includes a
printed circuit board 12 configured to be operatively coupled to a memory
controller 14 of a computer system 16.” Id. at 5:6–8. Memory module 10
includes a plurality of memory devices 18, each memory device 20 of the
plurality of memory devices 18 comprising data, address, and control ports.
Id. at 5:10–14. Memory module 10 further includes control module 22 and
data module 28 comprising a plurality of independently operable data
IPR2014-01375
Patent 8, 359,501 B1

4

handlers 30. Id. at 5:14–18. Control module 22 includes memory device
controller 34 which receives address and control signals 38 from system
memory controller 14 and address and control signals 42 from test controller
36. Id. at 9:40–45. Similarly, data module 28 includes switch 44, which
selectively inputs to memory devices 18 either data signals 48 from memory
controller 14 or data signals 50 from data handler logic element 46. Id. at
10:7–11.
During test mode, memory device controller 34 sends address and
control signals 38 from test controller 36 to register 40 for input to address
and control ports of memory devices 18. Id. at 9:40–50. “[T]est controller
36 updates each of [] data handlers 30 (e.g., with new data patterns, write
signal characteristics, etc.)” Id. at 14:7–9. Data generation element 54 of
data handler logic element 46 is configured to generate data signals and/or
patterns of data signals based on the information received from test
controller 36, for writing to memory devices 18. Id. at 10:28–37, 15:25–27.
C. Illustrative Claim
Of the challenged claims, claims 1, 20, and 29 are independent.
Claim 1, reproduced below, is illustrative of the claimed subject matter:
1. A memory system configured to be operatively coupled to a
memory controller of a computer system, the memory
system comprising:
a plurality of memory chips;
a plurality of data handlers configured to be operated
independently from one other, wherein one or more data
handlers of the plurality of data handlers are configured
to generate data for writing to a corresponding one or
more memory chips of the plurality of memory chips;
and
IPR2014-01375
Patent 8, 359,501 B1

5

a control circuit configured to generate address and control
signals, wherein the memory system is configured to test
the one or more memory chips using the address and
control signals generated by the control circuit and using
the data generated by the one or more data handlers.

D. Evidence Relied Upon
Petitioner’s patentability challenges are based on the following
references:
Reference Patent/Printed Publication Exhibit
Fleischman ’320 US 6,321,320 B1 1011
JTAG 2001 IEEE JTAG Standard No. 1149.1-2001 1012
Adams ’873 US 7,203,873 B1 1013
Huang An Efficient Parallel Transparent BIST
Method for Multiple Embedded Memory
Buffers, VLSI Design 2001, Fourteenth
International Conference on VLSI Design
(pp. 379–384), IEEE (2000)
1014

In addition to these references, Petitioner relies on the Declaration of
Dr. Nader Bagherzadeh (Ex. 1009) under 37 C.F.R. § 1.68. Pet. 6.
IPR2014-01375
Patent 8, 359,501 B1

6

E. Asserted Grounds of Unpatentability
Petitioner challenges the patentability of the ’501 patent claims based
on the following grounds:
References Basis Claims Challenged
Fleischman ’320 and JTAG 2001 § 103(a) 1–20
Adams ’873 and JTAG 2001 § 103(a) 1–6, 9–11, 14–15, 16–17,
and 20
Adams ’873, JTAG 2001, and
Huang
§ 103(a) 7–8, 12–13, and 18–19

III. CLAIM CONSTRUCTION
Claims of an unexpired patent are interpreted using the broadest
reasonable construction in light of the specification of the patent. See 37
C.F.R. § 42.100(b); see also In re Cuozzo Speed Techs. LLC, No. 2014–
1301, 2015 WL 448667 , at *6 (Fed. Cir. Feb. 04, 2015). Petitioner and
Patent Owner offer respective constructions for seven different claim terms.
See Pet. 18–21; Prelim. Resp. 26–32. For purposes of this decision, we
determine the only claim language requiring express construction is the term
“generate,” recited in each of independent claims 1 and 16.
Petitioner contends the term “generate” should be interpreted as
meaning “cause” or “initiate.” Pet. 20. In support of its proposed
interpretation of “generate,” Petitioner relies on a description in the ’501
patent that states the data signals generated by data generation element 54 of
data module 28 are programmable based on information received from
memory controller 14 (Ex. 1008, 10:67–11:2), and on IEEE 100 - STANDARD
DICTIONARY OF ELECTRICAL AND ELECTRONIC TERMS, (4th ed. 1988) (Ex.
IPR2014-01375
Patent 8, 359,501 B1

7

1016), which defines “generate (computing systems)” as: “[t]o produce a
program by selection of subsets from a set of skeletal coding under the
control of parameters” (id. at 411). Pet 20. Petitioner’s proposed
interpretation is consistent with our prior interpretation of the ’501 patent
claim term “generate” (for purposes of instituting trial) as meaning
“produce” or “cause.” See IPR2014-00971, Paper 12, slip op. at 9.
Patent Owner contends Petitioner’s proposed definition of “generate”
is based on an erroneous contention that programming and generating are
synonymous. See Prelim. Resp. 28. Patent Owner argues, more specifically,
that a programmable command transmitted to a generator “to cause [data]
generation” does not itself comprise the particular data sought to be
produced, and, therefore, does not “generate” the data. Id. As in IPR2014-
00971, (Paper 10, 24), Patent Owner contends the claim term “generate”
should be interpreted as meaning only “produce.” Id. at 28. In support of its
proposed interpretation of “generate,” Patent Owner relies on column 6,
lines 6–9 of the ’501 patent, which read: “In some embodiments, the control
module 22 and the data module 28 produce memory addresses, control
and/or data signals according to the JEDEC standard memory protocol.” Id.
at 28 (quoting Ex. 1008, 6:6–9) (emphasis added). Patent Owner also relies
on Merriam-Webster’s Collegiate Dictionary (Ex. 2008) and The New
American Webster Handy College Dictionary (Ex. 2009), each of which lists
“produce” as one definition among several of “generate” (Ex. 2008, 484; Ex.
2009, 230). Prelim. Resp. 29.
As explained in our Decision to Institute in IPR2014-00971 (Paper 12,
8), the description in the ’501 patent relied upon by Patent Owner relates to
only “some embodiments,” and the claims do not recite that the data and
IPR2014-01375
Patent 8, 359,501 B1

8

control modules are configured to generate signals “according to the JEDEC
standard memory protocol” (Prelim. Resp. 28). As further explained in that
prior decision, Merriam-Webster’s Collegiate Dictionary also defines
generate as “to be the cause of” (IPR2014-00971, Paper 12, slip op. at 9).
Ex. 2008, 484. Patent Owner argues the definition “to be the cause of”
applies only in the context of “a situation, action, or state of mind.” Prelim.
Resp. 29. Patent Owner contends “the context of the ’501 Patent is the
physical process of generating electrical signals. Accordingly, the definition
of ‘generate’ should be taken as ‘PRODUCE,’ since this is the ordinary
meaning within the context of ‘a vital, chemical, or physical process.’” Id.
at 29.
We agree with Patent Owner that the intrinsic evidence, as well as the
dictionary definitions on this record, support an interpretation of the claim
term “generate” as meaning, inter alia, “produce,” and, that a module
“configured to generate” address and control signals or data, as claimed,
encompasses a component which produces the exact signals or data used by
the memory devices. On the record before us, and for purposes of this
decision, however, we are persuaded that one of ordinary skill in the art
would also understand the term “generate,” as used in the claims, to mean
“cause.” Thus, for example, one of ordinary skill in the art would
understand that a module “configured to generate” signals or data
encompasses both a component that produces the exact signal or data used
by a memory device and a component which transmits a programmable
command to that generator to cause production of the signal or data. Our
interpretation of the term “generate” as including “cause” is supported by the
’501 patent (see id. at 9 (citing Ex. 1008, 10:49–50, 10:67–11:4)) and the
IPR2014-01375
Patent 8, 359,501 B1

9

dictionary definitions of record, including the additional definition of
“generate” in Merriam-Webster’s Collegiate Dictionary as, in the context of
a mathematical set or structure, “to define or originate . . . by the application
of one or more rules or operations” (Ex. 2008, 484). Accordingly, for
purposes of this decision, we interpret the claim term “generate” as meaning
“produce” or “cause.”
IV. ANALYSIS
A. Obviousness of Claims 1–20 over Fleischman ’320 and JTAG
2001
1. Fleischman ’320 (Ex. 1011)
Fleischman ’320 describes BIST architecture including multiple BIST
engines. Ex. 1011, 3:29–31, 3:18–20, Figs. 3, 8. Fleischman ’320 also
discloses that the BIST architecture includes BIST main control 110 and
address generation unit 72 (together constituting a “control module”) and
multiple data generation (DDG) units 94 (“plurality of data handlers”), each
for testing the memory arrays. Id. at 6:5–8, 4:8–11. Further, the BIST
architecture of Fleischman ’320 is configured to test memory arrays 1–N
using address and control information issued by primary BIST main control
110 and address generator 72. Id. at 1:25-30, 8:1–4, 8:10–11.
2. JTAG 2001 (Ex. 1012)
JTAG 2001 discloses a general BIST architecture that is applicable to
JTAG compliant circuitry, including printed circuit boards with memory
devices for testing. Ex. 1012, 68, 128. JTAG 2001 also discloses the use of
cyclic data, e.g., 1111X, 0XXX0, and other cyclic patterns for testing
memory devices. Id. at 159.
IPR2014-01375
Patent 8, 359,501 B1

10

3. Analysis
Petitioner contends claims 1–20 would have been obvious over
Fleischman ’320 in view of JTAG 2001. Pet. 21–36.
With respect to the motivation to combine the two references,
Petitioner contends:
A POSITA would have been motivated to combine Fleischman
‘320 and JTAG 2001, because Fleischman ‘320 expressly
discloses compliance with the JTAG standard. JTAG 2001
defines JTAG compliance, including the application of self-test
to devices on a printed circuit board, and therefore defines an
environment that is suitable for Fleischman ‘320. Accordingly,
a POSITA would be motivated to adapt the BIST architecture
and operations disclosed in Fleischman ‘320 to a PCB in
accordance with the compliance requirements disclosed in
JTAG 2001.
Id. at 36 (citations omitted). In support of these contentions, Petitioner cites
paragraph 33 and Appendix B of the Declaration of Dr. Nader Bagherzadeh
(Ex. 1009). Id. Petitioner notes: “The combination of familiar elements
according to known methods is likely to be obvious when it does no more
than yield predictable results.” Id. (citations omitted).
As explained by the Federal Circuit, “[a]lthough predictability is a
touchstone of obviousness, the ‘predictable result’ discussed in KSR refers
not only to the expectation that prior art elements are capable of being
physically combined, but also that the combination would have worked for
its intended purpose.” DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc.,
567 F.3d 1314, 1326 (Fed. Cir. 2009) (citing KSR Int'l Co. v. Teleflex Inc.,
550 U.S. 398 (2007)).
We acknowledge Petitioner relies on Dr. Bagherzadeh’s testimony
that is identical in substance to the text from the Petition reproduced above.
IPR2014-01375
Patent 8, 359,501 B1

11

The specification of Fleischman ’320 states, “BIST operation and extraction
of test results are typically accomplished through IEEE Standard 1149.1
Joint Test Action Group (JTAG) boundary scan Test Access Port (TAP).”
Ex. 1011, 2:61–63. However, this statement is a general description of the
prior art, not the invention. Fleischman ’320 describes embodiments using a
JTAG TAP interface 122. Ex. 1011, 5:10–13, 9:47–55. In the ’501 patent
specification, the JTAG TAP interface is always connected to the BIST
Main Control (BMC) 110.
Nonetheless, for the combination of Fleischman ’320 and JTAG 2001,
Petitioner proposes a different BIST architecture where the JTAG interface
connects directly to the Memory Arrays in Fleischman ’320. Pet. 26;
Prelim. Resp. 38. Petitioner contends the proposed combination of
Fleischman ’320 and JTAG 2001 would have been nothing more than the
combination of familiar elements, but has not identified persuasive evidence
that supports these contentions. Pet. 26. Dr. Bagherzadeh also has not
identified sufficient support for this combination. For example, Dr.
Bagherzadeh has not explained clearly why, or identified evidence that
shows that the invention described in the ’501 patent falls into a very
predictable field, or one of ordinary skill in the art would have possessed the
requisite skills to make the proposed combination, or that one of ordinary
skill in the art reasonably would have anticipated the combination to
function in an ordinary and expected way. See Rothman v. Target Corp.,
556 F.3d 1310, 1319–20 (Fed. Cir. 2009). Given that the ’501 specification
teaches a different configuration of the JTAG TAP, Petitioner needed to
explain why one of ordinary skill would have known to replace the existing
configuration with the new configuration. Compare Abbott Labs. v. Sandoz,
IPR2014-01375
Patent 8, 359,501 B1

12

Inc., 544 F.3d 1341, 1352 (Fed. Cir. 2008) (“[K]nowledge of the goal [such
as meeting an FDA requirement] does not render its achievement obvious.”)
with Erico Int’ Corp. v. Vutec Corp., 516 F.3d 1350, 1356 (Fed. Cir. 2008)
(a regulation that directs designers to a particular solution may render that
solution obvious).
Dr. Bagherzadeh contends that the absence of a teaching away in
Fleischman ’320 and JTAG 2001 is evidence that the combination would be
operative. Ex. 1009 ¶ 35. Although a teaching away supports a conclusion
that a prior art combination would have produced an inoperative result, see
DePuy, 567 F.3d at 1326, Petitioner has not identified case law to support
Dr. Bagherzadeh’s contention.
Accordingly, we are not persuaded that Petitioner has shown
sufficiently a motivation to combine Fleischman ’320 and JTAG, and for the
above-stated reasons, on this record, we determine Petitioner has not
demonstrated a reasonable likelihood it would prevail on the ground that
claims 1–20 would have been obvious over Fleischman ’320 and JTAG
2001.
B. Obviousness of Claims 1–6, 9–11, 14–15, 16–17, and 20 over
Adams and JTAG 2001
1. Adams (Ex. 1013)
Adams ’873 discloses a BIST architecture that is applicable to any
BIST environment, including environments compliant with the JTAG
standard, and that is applicable for testing memory devices. Ex. 1013, 3:34–
37, Fig. 2. Adams ’873 also discloses that the BIST architecture includes
MBIST controller 210 (“control module”) and multiple collar circuitry
220a–c (“plurality of data handlers”), each for testing the corresponding
IPR2014-01375
Patent 8, 359,501 B1

13

memory devices 225a-c. Id. at 2:6–12, 5:7–14, 5:58–6:5. Further, the BIST
architecture of Adams ’873 is configured to test the memory devices 225a–c
after being enabled by MBIST controller 210 and using data generated by
collar circuitry 220a–c. Id. at 5:40–46, 5:58–6:5.
2. Analysis
Patent Owner argues Petitioner has not identified sufficient support
for its contention that Adams ’873’s MBIST controller generates address
and control signals for testing memory devices as recited in the claims. See
Prelim. Resp. 43–46. Patent Owner argues the signals that enter Adams
’873’s memory 325 are instead all generated by the corresponding collars.
Id. at 48.
Patent Owner’s arguments are based on a narrow construction of the
term “generate” as requiring a control module configured to produce directly
the actual address and control signals used to test the memory devices. As
explained in Section III, above, for purposes of this decision, we interpret
the claim term “generate” more broadly than proposed by Patent Owner as
meaning “produce” or “cause.”
Adams ’873 discloses that the MBIST controller includes an “enable
module 310a [that] is configured to provide enable signals for use in
selecting, scheduling, and controlling BIST of collars 320 (and, therefore,
the memory 325 in each collar).” Ex. 1013, 5:58–6:5; Pet. 37–38. In other
words, MBIST controller 210 issues enable signals that communicate to an
“enable element [that] is configured to selectively enable a collared memory
for testing, e.g., one at a time.” Ex. 1013, 2:21–22; Pet. 37.
Although the commands are not sent directly to memory 325, but
instead enable the collars (id.), the above description in Adams ’873
IPR2014-01375
Patent 8, 359,501 B1

14

supports Petitioner’s contention that the enable signals issued by MBIST
controller 210 cause the issuance of, i.e., “generate,” address and control
signals. Nonetheless, Petitioner’s ground fails—MBIST controller 210 is
not “configured to generate” because, as set forth in Section III, above, we
construe “configured to generate” signals or data as encompassing a
component which transmits a programmable command to that generator to
cause production of the signal or data. The enable signal in Adams pointed
to by Petitioner is not programmable, i.e., it is not used by the collar to
generate or program any specific signal. The enable signal simply “enables”
the collar to enter test mode. Ex. 1013, 5:7–15.
For the above-stated reasons, on this record, we determine Petitioner
has not demonstrated a reasonable likelihood it would prevail on the ground
that claims 1–6, 9–11, 14–15, 16–17, and 20 would have been obvious over
Adams ’873 and JTAG 2001.
C. Obviousness of Claims 7–8, 12–13, and 18–19 over Adams,
JTAG 2001, and Huang
Petitioner argues that claims 7–8, 12–13, and 18–19 would have been
obvious over Adams ’873, JTAG 2001, and Huang under 35 U.S.C.
§ 103(a). Pet. 48-53. Claims 7–8, 12–13, and 18–19 depend from
independent claims 1 and 16, respectively. As discussed above, the
combination of Adams ’873 and JTAG 2001 fails to teach or suggest all of
the elements of independent claims 1 and 16. Petitioner does not assert that
Huang overcomes the aforementioned deficiency in Adams ’873 and JTAG
2001. Thus, upon review of Petitioner’s analysis and supporting evidence,
we determine that Petitioner has not demonstrated that there is a reasonable
likelihood it would prevail with respect to claims 7–8, 12–13, and 18–19, on
IPR2014-01375
Patent 8, 359,501 B1

15

the ground that these claims would have been obvious over Adams ’873,
JTAG 2001, and Huang.

V. CONCLUSION
The information presented does not show that there is a reasonable
likelihood that Petitioner would prevail at trial with respect to at least one
claim of the ’501 patent, based on any grounds presented in the Petition. On
this record, we deny the petition for inter partes review of claims 1–20.
VI. ORDER
Accordingly, it is
ORDERED that that the petition is DENIED as to all challenged
claims, and no trial is instituted.

IPR2014-01375
Patent 8, 359,501 B1

16

PETITIONER:

Michael F. Heafey
Sanjiva K. Reddy
King & Spalding LLP
mheafey@kslaw.com
sreddy@kslaw.com
patentmailnyc@kslaw.com

PATENT OWNER:

Thomas J. Wimbiscus
Gregory C. Schodde
Scott P. McBride
Ronald H. Spuhler
Wayne H. Bradley
McAndrews, Held & Malloy, Ltd.
twimbiscus@mcandrews-ip.com
gschodde@mcandrews-ip.com
smcbride@mcandrews-ip.com
rspuhler@mcandrews-ip.com
wbradley@mcandrews-ip.com