SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Patent Trials and Appeals Board

May 10, 2021

2020003421 (P.T.A.B. May. 10, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/871,586 01/15/2018 Michael J. SEDDON ONS02289C01US 2740
132194 7590 05/10/2021
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (AS)
5005 E. McDowell Road
Maildrop A700
Phoenix, AZ 85008
EXAMINER
JOY, JEREMY J
ART UNIT PAPER NUMBER
2816
NOTIFICATION DATE DELIVERY MODE
05/10/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ipdocket@iptech.law
patents@onsemi.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL J. SEDDON, TAKASHI NOMA, and
KAZUHIRO SAITO

Appeal 2020-003421
Application 15/871,586
Technology Center 2800
Before CATHERINE Q. TIMM, BRIAN D. RANGE, and
MERRELL C. CASHION, JR., Administrative Patent Judges.
RANGE, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–5, 7–11, and 14–18. We have
jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant
identifies the real party in interest as SEMICONDUCTOR COMPONENTS
INDUSTRIES, LLC. Appeal Br. 3.
Appeal 2020-003421
Application 15/871,586
2
CLAIMED SUBJECT MATTER2
Appellant describes the invention as relating to “a semiconductor
wafer and method of ball drop on a thin wafer with an edge support ring.”
Spec. ¶ 2. In particular, the Specification refers to Figure 1c to explain that,
as part of a prior art technique, conductive balls or bumps 34 need to be
formed on a conductive layer 30 for electrical interconnect. Spec. ¶¶ 3–7.
The Specification explains that if a stencil is disposed over an edge support
ring with a gap between the stencil and the conductive layer as Figure 1c
illustrates, bumps will be randomly dispersed over surface 32 in an
ineffective manner. Id. ¶ 6. Similarly, the Specification explains that if the
semiconductor is warped, as Figure 1d illustrates, a stencil having a gap
between it and the conductive layer will not effectively form bumps. Id. ¶ 7.
The Specification addresses this problem with a stencil that “comes in
contact with or is immediately adjacent to conductive layer 160” as Figure
4b illustrates. Id. at 23.
Claims 1, 7, and 14 are independent. Claim 1 is illustrative, and we
reproduce it below while adding emphasis to key recitations:
1. A method of making a semiconductor device,
comprising:
providing a semiconductor wafer including an edge
support ring around a perimeter of the semiconductor wafer;
forming a conductive layer over a surface of the
semiconductor wafer;

2 In this Decision, we refer to the Final Office Action dated June 17, 2019
(“Final Act.”), the Appeal Brief filed October 15, 2019 (“Appeal Br.”), the
Examiner’s Answer dated February 3, 2020 (“Ans.”), and the Reply Brief
filed March 31, 2020 (“Reply Br.”).
Appeal 2020-003421
Application 15/871,586
3
providing a first stencil including a plurality of first
openings; and
disposing the first stencil over the edge support ring
with the first openings extending below a top surface of the
edge support ring to contact the conductive layer;
wherein the first stencil is unitary.
Appeal Br. 23 (Claim App. (emphasis added)). Claims 7 and 14 similarly
recite that the stencil extends “to the conductive layer.” Id. at 25, 27.
REFERENCES
The Examiner relies upon the prior art below in rejecting the claims
on appeal:
Name Reference Date
Applicant’s Admitted
Prior Art (AAPA)
Application Figures 1a–
1d and associated
disclosure
N/A
Gruber et al. (“Gruber”) US 8,523, 046 B1 Sept. 3, 2013
Ishikawa et al.
(“Ishikawa”)
US 2010/0127049 A1 May 27, 2010
Lee et al. (“Lee”) US 2015/001278 A1 Jan. 1, 2015

REJECTIONS
The Examiner maintains (Ans. 3) the following rejections on appeal:
A. Claims 1–5, 7–11, and 14–17 under 35 U.S.C. § 103 as obvious over
Applicant’s Admitted Prior Art (“AAPA”) in view of Lee and Gruber.
Final Act. 6.
Appeal 2020-003421
Application 15/871,586
4
B. Claim 18 under 35 U.S.C. § 103 as obvious over Applicant’s
Admitted Prior Art (“AAPA”) in view of Lee, Gruber, and Ishikawa.
Id. at 20.3
OPINION
The Examiner has the initial burden of establishing a prima facie case
of obviousness under 35 U.S.C. § 103. In re Oetiker, 977 F.2d 1443, 1445
(Fed. Cir. 1992) (“[T]he examiner bears the initial burden, on review of the
prior art or on any other ground, of presenting a prima facie case of
unpatentability.”). To establish a prima facie case of obviousness, the
Examiner must show that each and every limitation of the claim is described
or suggested by the prior art or would have been obvious based on the
knowledge of those of ordinary skill in the art or the inferences and creative
steps a person of ordinary skill in the art would have employed. KSR Int’l
Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007); In re Fine, 837 F.2d 1071,
1074 (Fed. Cir. 1988). To resolve the issues before us on appeal, we focus
on the Examiner’s findings and determinations that relate to the error
Appellant identifies.
We direct attention to the Examiner’s Final Office Action for a
complete statement of the rejection of claim 1. Final Act. 6–8. We focus our
attention on the reference to Lee, which the Examiner relies upon to address
the above highlighted claim 1 limitation and the similar recitations of claims
7 and 14.

3 The Examiner does not explicitly reference Gruber when rejecting claim
18, but we understand that the Examiner still relies upon Gruber for
recitations appearing in claim 1 because the claim 18 rejection is based upon
the AAPA as modified above in further view of Ishikawa. Final Act. 20.
Appeal 2020-003421
Application 15/871,586
5
The Examiner finds that stencil (50) of Lee does not extend to or
contact the conductive layer and that the stencil support structure (14/54)
between the openings (56) do not extend to the semiconductor wafer. Ans.
4–5; see also Lee Fig. 1 (illustrating a gap between mask 50 and the
semiconductor wafer). The Examiner nonetheless finds that Lee teaches
“openings” as recited by claim 1 that extend to the conductive layer as
claimed. Ans. 5. The Examiner explains that “while the stencil may not
contact the conductive layers the openings do in fact contact the conductive
layers and therefore satisfy the claim limitation as currently written.” Id. The
Examiner reaches this determination by construing an “opening” as “an
empty space or void formed between the stencil boundaries (14/54),
contacting the conductive layer.” Id.
Appellant argues that the Examiner errs by construing the claims too
broadly. Reply Br. 4–5. We agree. Claims must be construed in view of the
context provided by the Specification. See, e.g., In re Morris, 127 F.3d 1048,
1054 (Fed. Cir. 1997) (holding that ignoring the specification in claim
construction is unreasonable). Here, the Specification explains, for example,
that narrow portion 180 of openings 176 “comes in contact with or is
immediately adjacent to conductive layer 160.” Spec. ¶ 23; see also, e.g.,
Fig. 4b (illustrating stencil physically contacting conductive layer). The
Specification, therefore, distinguishes a scenario where openings physically
contact the conductive layer from a scenario where openings are merely near
the conductive layer. Under the Examiner’s broad interpretation of the
claims, however, this distinction would vanish.
The language of the claims themselves also indicates that the stencil
must physically contact the conductive layer. Claim 1 requires “contact,”
and we agree with Appellant that an empty space or void cannot reasonably
Appeal 2020-003421
Application 15/871,586
6
cause contact in the context of claim 1. Reply Br. 4. Claims 7 and 14 require
stencil openings extending to the conductive layer. Construing the opening
as a void would, in essence, negate these recitations because any void would
extend everywhere including to the conductive layer. Cf. Application of
Miller, 441 F.2d 689, 694 (C.C.P.A. 1971) (“All words in a claim must be
considered in judging the patentability of that claim against the prior art.”)
(internal quotes and citation omitted). Thus, in view of the claims’ language
and the Specification, the broadest reasonable interpretation of claims 1, 7,
and 14 requires, among other things, that the stencil physically contact the
conductive layer.
The Examiner finds that Lee does not teach or suggest a stencil
physically contacting the conductive layer, and the Examiner does not find
that the other cited references teach such contact. We, thus, do not sustain
the Examiner’s rejections.
DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1–5, 7–11,
14–17
103 AAPA, Lee, Gruber 1–5, 7–11,
14–17
18 103 AAPA, Lee, Gruber,
Ishikawa
18
Overall
Outcome
1–5, 7–11,
14–18

REVERSED