2020004023 (P.T.A.B. May. 14, 2021)

SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Patent Trials and Appeals BoardMay 14, 2021

2020004023 (P.T.A.B. May. 14, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/986,460 05/22/2018 Michael J. SEDDON ONS02894US 7128 132194 7590 05/14/2021 SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (AS) 5005 E. McDowell Road Maildrop A700 Phoenix, AZ 85008 EXAMINER AHMAD, KHAJA ART UNIT PAPER NUMBER 2813 NOTIFICATION DATE DELIVERY MODE 05/14/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ipdocket@iptech.law patents@onsemi.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte MICHAEL J. SEDDON Appeal 2020-004023 Application 15/986,460 Technology Center 2800 Before TERRY J. OWENS, DEBRA L. DENNETT, and LILAN REN, Administrative Patent Judges. OWENS, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1–20. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 We use the term “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies the real party in interest as Semiconductor Components Industries, LLC (Appeal Br. 3). Appeal 2020-004023 Application 15/986,460 2 CLAIMED SUBJECT MATTER The claims are directed to a method of forming a plurality of semiconductor devices on as semiconductor substrate. Claim 1, reproduced below, is illustrative of the claimed subject matter: 1. A method of forming a plurality of semiconductor devices on a semiconductor substrate, the method comprising: providing a semiconductor substrate comprising a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface; and processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface; wherein the thickness is between 70 microns and 500 microns and the size is 100 millimeters; and wherein the semiconductor substrate is not coupled with one of a carrier and a support. REFERENCES The prior art relied upon by the Examiner is: Name Reference Date Bayan US 2008/0290482 A1 Nov. 27, 2008 Morikazu US 2009/0203193 A1 Aug. 13, 2009 Faurie US 2014/0065801 A1 Mar. 6, 2014 Lin US 2015/0364394 A1 Dec. 17, 2015 REJECTIONS Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis 1–3, 7–10, 14–17, 20 103 Lin, Morikazu 4, 11, 18 103 Lin, Morikazu, Bayan 5, 6, 12, 13, 19 103 Lin, Morikazu, Faurie Appeal 2020-004023 Application 15/986,460 3 OPINION We need address only the independent claims (1, 8, and 15). Those claims require forming a plurality of semiconductor devices on a semiconductor substrate that has a thickness between 70 and 500 microns (claim 1), 100 and 575 microns (claim 8), or 120 and 600 microns (claim 15), and is not coupled with one of a carrier and a support. Lin forms semiconductor die (124) on an unsupported semiconductor wafer (120)’s active surface and then grinds the semiconductor wafer (120)’s back side inactive surface (128) to thin the semiconductor wafer (120) to an undisclosed thickness (¶¶ 41, 48; Figs. 2b, 2e). Morikazu forms an electronic circuit on a semiconductor chip (3)’s front side and then grinds the back side to a thickness of about 200 µm (¶¶ 27, 29; Fig. 2). The Examiner finds that “the claim does not recite the stage (such as before back grinding or after back grinding) when the semiconductor substrate is having the thickness between 70 microns and 500 microns” (Final 15), and concludes (Final 4): [I]t would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use semiconductor wafer wherein the thickness of the semiconductor substrate is between 70 microns and 500 microns in the method of Lin according to the teaching of Morikazu with routine experiment and optimization since the thickness of the semiconductor substrate is a result effective variable in order to control device parameters of semiconductor devices formed with the semiconductor substrate (120, Figure 2 of Lin). The Appellant’s claim 1 requires “providing a semiconductor substrate comprising . . . a thickness . . . processing the semiconductor Appeal 2020-004023 Application 15/986,460 4 substrate . . . to form a plurality of semiconductor devices on the [semiconductor substrate’s] first surface . . . wherein the thickness is between 70 microns and 500 microns.” The cited portion of claim 8 is the same except the thickness range is “between 100 microns and 575 microns,” and the cited portion of claim 15 is the same except the thickness range is “between 120 microns and 600 microns.” Those claims, therefore, require that the semiconductor substrate processed to form a plurality of semiconductor devices on its first surface is the previously-recited provided semiconductor substrate having the recited thickness. That claim interpretation is consistent with the Appellant’s Specification’s statements that “[p]roviding the semiconductor substrate may further include forming the semiconductor substrate from a boule and grinding or polishing the first surface or the second surface of the semiconductor substrate to thin the thickness to between 70 microns and 500 microns” (¶ 8) and “the term ‘thickness’ refers to the thickness of the material of semiconductor substrate itself rather than the distance between the first and second surfaces of the substrate observed after completion of or during device fabrication processing” (¶ 42).2 As pointed out above, however, both Lin and Morikazu form semiconductor devices on a wafer before the wafer is thinned. Morikazu’s 2 Claims 2, 9, and 16 which depend, respectively, from claims 1, 8, and 15, require “backgrinding the second surface of the semiconductor substrate to reduce the thickness to a desired value.” Because claims 2, 9, and 16 must further limit the claim from which they depend (37 C.F.R. § 1.75(c) (2009)), the backgrinding must occur after processing the semiconductor substrate having the thickness recited in those claims’ respective independent claim such that the desired value in claims 2, 9, and 16 is a thickness less than a thickness recited in the respective independent claim. Appeal 2020-004023 Application 15/986,460 5 200 micron chip thickness relied upon by the Examiner as being within the Appellant’s recited thickness range (Final 4) is not achieved until after semiconductor devices have been formed on the chip (3) (¶ 29).3 Thus, the Examiner has not set forth a factual basis that is sufficient to support a conclusion of obviousness of the Appellant’s claimed method. See In re Warner, 379 F.2d 1011, 1017 (CCPA 1967) (“A rejection based on section 103 clearly must rest on a factual basis, and these facts must be interpreted without hindsight reconstruction of the invention from the prior art”). Accordingly, we reverse the rejections. CONCLUSION The Examiner’s decision to reject claims 1–20 is REVERSED. DECISION SUMMARY Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1–3, 7–10, 14–17, 20 103 Lin, Morikazu 1–3, 7–10, 14–17, 20 4, 11, 18 103 Lin, Morikazu, Bayan 4, 11, 18 5, 6, 12, 13, 19 103 Lin, Morikazu, Faurie 5, 6, 12, 13, 19 Overall Outcome 1–20 REVERSED 3 In the Examiner’s Answer, the Examiner does not address Appellant’s argument regarding this point (Appeal Br. 17).