Sangram ALAPATI et al.

Patent Trials and Appeals Board

Jan 26, 2021

2019005719 (P.T.A.B. Jan. 26, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/645,836 12/23/2009 Sangram ALAPATI AUS920090181US1 9024
77351 7590 01/26/2021
IBM CORP.
C/O THE LAW OFFICE OF JAMES BAUDINO, PLLC
2313 ROOSEVELT DRIVE
SUITE A
ARLINGTON, TX 76016
EXAMINER
BROCK, ROBERT S
ART UNIT PAPER NUMBER
2128
MAIL DATE DELIVERY MODE
01/26/2021 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte SANGRAM ALAPATI,
SATISH KURMAR SADASIVAM,
MADHAVAN SRINIVASAN,
JUBILEE BHAVAM PONNA, and
HARISH P. OMKAR
____________

Appeal 2019-005719
Application 12/645,836
Technology Center 2100
____________

Before ELENI MANTIS MERCADER, JOHNNY A. KUMAR, and
MATTHEW J. McNEILL, Administrative Patent Judges.

KUMAR, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF THE CASE
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1, 3–8, 10–15, 17–22, and 25–28, which constitute
all the claims pending in this application. We have jurisdiction under
35 U.S.C. § 6(b).
We affirm.
THE INVENTION
Appellant’s claimed invention is directed to “simulation based
verification” in which “a test case is built and executed by the hardware” so
that the “results of the hardware execution are compared to the software
simulation to verify the hardware operation.” (Spec. ¶ 1).
Independent claim 1, reproduced below, is representative of the
subject matter on appeal:
1. A method comprising:
building, via an abstract test case builder running on a
processor unit, an abstract test case for processor architecture
functional verification, the abstract test case including a stream
of instructions, the instructions each having a particular
instruction format corresponding to a processor architecture;
receiving, via an execution manager, the abstract test
case;
selecting, by the execution manager, a particular
instruction of the abstract test case;
determining, by the execution manager, whether the
selected instruction is an abstract instruction or a non-abstract
instruction;

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies International Business Machines
Corporation as the real party in interest. Appeal Br. 2.
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in response to determining that the selected instruction is
an abstract instruction, determining the instruction format of the
abstract instruction;
based on the determined instruction format of the abstract
instruction, selecting a non-abstract instruction from an
instruction pool, the instruction pool having a number of
different, predefined non-abstract instructions corresponding to
different instruction formats available for the processor
architecture;
generating a real test case for processor verification by
the execution manager by modifying the abstract instruction
based on the non-abstract instruction selected from the
instruction pool; and
executing the real test case in connection with the
processor architecture and verifying the functionality of the
processor architecture based on a result of the executed real test
case.
Appeal Br. 59 (Claims Appendix).

REFERENCE
The prior art relied upon by the Examiner in rejecting the claims on
appeal is the following:
YINGBIAO YAO ET AL., A PSEUDO-RANDOM PROGRAM GENERATOR FOR
PROCESSOR FUNCTIONAL VERIFICATION, INT’L SYMPOSIUM ON INTEGRATED
CIRCUITS, SINGAPORE, pp. 441–444 (2007) (“YAO”).
REJECTION 2
The Examiner made the following rejection:
Claims 1, 3–8, 10–15, 17–22, and 25–28 stand rejected under 35
U.S.C. § 102(b) as being anticipated by Yao. Final Act. 6.

2 The Examiner has withdrawn the 35 U.S.C. § 101 rejection of claims 1, 3–
8, 10–15, 17–22, and 25–28. Ans. 3.
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ISSUE
The pivotal issue is whether the Examiner erred in finding that Yao
discloses the limitations of
“building, via an abstract test case builder running on a
processor unit, an abstract test case for processor architecture
functional verification, the abstract test case including a stream
of instructions, the instructions each having a particular
instruction format corresponding to a processor architecture,”
“receiving, via an execution manager, the abstract test case,”
“selecting, by the execution manager, a particular
instruction of the abstract test case,” and “determining, by the
execution manager, whether the selected instruction is an
abstract instruction or a non-abstract instruction.”
as recited in independent claim 1, and similarly recited in independent
claims 8, 15, and 21. See Appeal Br. 38; Reply Br. 2.
ANALYSIS
We adopt the Examiner’s findings in the Answer, and Final Office
Action, and we add the following primarily for emphasis. We note that if
Appellant failed to present arguments on a particular rejection, we will not
unilaterally review those uncontested aspects of the rejection. See Ex parte
Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential); Hyatt v. Dudas,
551 F.3d 1307, 1313–14 (Fed. Cir. 2008) (The Board may treat arguments
Appellant failed to make for a given ground of rejection as waived.).
Appellant argues that Yao fails to anticipate Appellant’s claim 1
because
In figure 7 of Yao, there appears to be a list of statements, such
as “Type 3 Generating_ Model (1, 0, 0, 1, Oxbfc 10000, 0)” and
“Type9_Generating_ Model (0, 0, Current_rd, 0, 0, 0, 0).”…
[T]he template in Yao is used to create test instructions.
However, the above-referenced phrase of the template appears
to refer to a particular instruction generating model (e.g., Type
3 or Type 9). If the above-referenced phrase in figure 7 of Yao
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is considered to be an abstract instruction (as asserted by the
Examiner), it does not appear to have an instruction format.
Although the Type 3 or Type 9 generating model does generate
instructions of a particular instruction format, the reference as
to which generator to use to create an instruction does not,
itself, have an instruction format.
(Appeal Br. 40, 41).
Appellant contends that “Yao does not appear to disclose that one of
the ‘instructions’ from the Yao ‘test template’ is selected and than [sic]
analyzed to determine whether the selected instruction is an abstract
instruction or a non-abstract instruction.” (Appeal Br. 41).
We are not persuaded by Appellant’s arguments. Initially, we agree
with the Examiner that Yao’s Figure 7 at page 444 discloses Yao’s
“template”, which corresponds to the claimed “abstract test case”; and
invocations of the models that correspond to the claimed “instructions.”
(Ans. 4, citing Yao, Figure 7, page 444).
The Examiner has identified the relevant portions of Yao and has
provided sufficient explanation with corresponding citations to various parts
of the reference for disclosing the disputed limitations. Ans. 4–7. For
example, the Examiner finds, and we agree, Yao discloses:
p441:abstract: “This paper presents an ISA model-based
pseudo-random program generator, called as VirgoASM, for
functional verification of RISC3200 processor.”; p441:§I:¶1:
“In the simulation environment, the processor executes test
programs as a real chip and the simulation outputs and signal
traces are recorded and compared with expected outputs and
traces.”; p441:Abstract: “various types of test templates are
created to guarantee the quality requirement of generated
instruction sequences.”; p441:§II:¶1: “verification engineers
can develop all kinds of test templates .... At last, VirgoASM
generates the high quality test programs.”; p444:§V:¶1: “test
templates are used to generate complex instruction sequences.”;
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p442:fig 1. Examiner’s Note (EN): “test templates” are abstract
test cases which are built using VirgoASM.), the abstract test
case including a stream of instructions (p444:§V:¶1: “test
templates are used to generate complex instruction
sequences.”), the instructions each having a particular
instruction format (p442:§III.A:¶5, “At last, these seventeen
instruction opcode sets include all legal opcode of instr_user.”;
p443:§III.C:¶1: “According to syntax format of instruction
opcode sets, the instruction generating models, Cartesian
product set of instruction opcode and operand sets, are built for
every instruction opcode set, which have the constraint
conditions specified by semantic requirements of instruction
opcode sets as shown in the 3rd column of table I.” (see also
p442:Table I and p443:figs 3 and 4)). . . .
. . . .
. . . (p444:§V:¶1: “Instruction generating models are used
to generate single legal and valid instruction and test templates
are used to generate complex instruction sequences.” EN: The
test templates include the models and when generating the
sequences, the single instruction must be selected for translation
via the models.);
. . .
. . . (p443:§C:¶3: “From fig.3 and fig.4, we can find that
the major features of instruction generating models are
convenient and flexible. For example, they support not only
random instruction generating but also user specific instruction
generating. Based on these instruction generating models, the
test program for single instruction verification of instr_user set
can be generated conveniently. ... For example, fig.5 describes a
specific template for generating single instruction test program
of Type9.”; EN: “Random instruction” is an abstract instruction
and “user specific is non-abstract. As can be seen in figs 3 and
4, a determination is made via the conditionals determining
whether or not to include randomly generated values. As can be
seen in fig 5, a determination is made via the type of function
call, e.g. using “0” to indicate random selection (for an abstract
instruction), all non-zeros for a user specific instruction (non-
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abstract), and also an “insert_NOP” as a specific instruction, i.e.
a “no op”.);
Final Act. 6–8. (original emphases omitted).
We also agree with the Examiner that in Yao (Figures 3, 4):
each model has a particular format, i.e. a model name followed
by arguments/parameters in parentheses, while fig 7 shows that
invocation of the model follows the format, i.e. the reference
“as to which generator to use” has a format which follows that
of the definition. Also as regards “instruction” and “format”,
the examiner submits that by its very nature, any instruction
will have a format; i.e. without a “format” of some sort, the
notion of “instruction” would have little meaning in general
[and particularly so for computer instructions such as the
template instruction of Yao].
Ans. 5, 6.
Regarding Appellant’s argument about “instruction format,” we agree
with the Examiner that:
Appellant’s specification does not appear to provide a
definition which confines “instruction format” to a specific
representation (see for example Appellant’s figures 4-5 and the
associated description at [0036]-[0037] of Appellant’s
specification), so it does not provide for an exclusion of Yao’ s
particular format. Further as regards a description of
“instruction format”, claim 5 (depending from claim 1) recites
“abstract instruction including an opcode identifier and the at
least one register”; however, this too provides no requirement
as to its manner of representation; i.e. this specifies that the
“instruction” have an “opcode identifier” and “the at least one
register”, but no requirement as to a specific manner in which
the opcode identifier and register must be expressed (no
“format”). Claim 6 (depending from claim 5) is similar to
claim 5 in these regards. More briefly, the examiner can find
no description of “instruction format” in the Appellant’s
specification and claims which excludes the format of the
model generators of Yao.
Ans. 7.
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“During examination, ‘claims . . . are to be given their broadest
reasonable interpretation consistent with the specification, and . . . claim
language should be read in light of the specification as it would be
interpreted by one of ordinary skill in the art.’” In re Am. Acad. of Sci. Tech
Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004) (citation omitted); In re Morris,
127 F.3d 1048, 1053–54 (Fed. Cir. 1997). Where no explicit definition for a
term is given in the specification, the term should be given its ordinary
meaning and broadest reasonable interpretation. E-Pass Techs., Inc. v.
3Com Corp., 343 F.3d 1364, 1368 (Fed. Cir. 2003). The ordinary and
customary meaning of a claim term is the meaning that the term would have
to a person of ordinary skill in the art in question at the time of the invention.
Phillips v. AWH Corp., 415 F.3d 1303, 1319 (Fed. Cir. 2005) (en banc).
Thus, the Examiner’s claim interpretation of “instruction format”
consistent with Appellant’s Specification and claims does not exclude the
format of the model generators of Yao.
Appellant provided additional arguments that Yao does not disclose
the features recited in dependent claims 7 (Appeal Br. 56) and claim 25
(Appeal Br. 57). We have considered these arguments and find them
unpersuasive. In addition, we note the Examiner has rebutted these
arguments in the Answer by a preponderance of the evidence (Ans. 31–34).
We agree with the Examiner’s findings and underlying reasoning and adopt
them as our own.
We have considered Appellant’s Reply Brief but find it unpersuasive
in rebutting the Examiner’s responses.
Thus, we affirm the Examiner’s anticipation rejection of independent
claim 1, and independent claims 8, 15, and 21 commensurate in scope, as
well as the dependent claims not separately argued. See Appeal Br. 44–57.
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Thus, we sustain the rejection of claims 1, 3–8, 10–15, 17–22, and
25–28 under 35 U.S.C. § 102.

Appeal 2019-005719
Application 12/645,836
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DECISION
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1, 3–8,
10–15,
17–22,
25–28
102 Yao 1, 3–8,
10–15,
17–22,
25–28

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED