Samsung Electronics Co., Ltd.

Patent Trials and Appeals Board

Aug 24, 2021

2020005920 (P.T.A.B. Aug. 24, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
16/107,942 08/21/2018 Nuo Xu 146114/414467-00010 6924
129498 7590 08/24/2021
Lewis Roca Rothgerber Christie LLP
P.O. Box 29001
Glendale, CA 91209-9001
EXAMINER
CHIN, EDWARD
ART UNIT PAPER NUMBER
2813
NOTIFICATION DATE DELIVERY MODE
08/24/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PLPrivatePair@lrrc.com
pto@lewisroca.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NUO XU, FAN CHEN, WEIYI QI, JONGCHOL KIM,
JING WANG, YANG LU, and WOOSUNG CHOI
Appeal 2020-005920
Application 16/107,942
Technology Center 2800
Before JEFFREY B. ROBERTSON, JAMES C. HOUSEL, and
CHRISTOPHER C. KENNEDY, Administrative Patent Judges.
HOUSEL, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 11, 12, 14–18, and 20. Pending claims
1–10, 13, and 19 are not before us on appeal.2 We have jurisdiction under
35 U.S.C. § 6(b).

1 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42. Appellant identifies Samsung Electronics Co., Ltd. as the real
party in interest. Appeal Brief (“Appeal Br.”) filed March 23, 2020, 1.
2 The Examiner has withdrawn pending claims 1–10 from consideration as
directed to a non-elected invention, and has objected to pending claims 13
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Application 16/107,942

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We REVERSE.
CLAIMED SUBJECT MATTER
The invention recited in the claims on appeal relates to methods for
wafer map analysis, in particular for defect detection and analysis in the field
of semiconductor device fabrication. Specification (“Spec.”) filed August
21, 2018, Title and ¶ 2.3 Appellant discloses that the integrated circuits
(“ICs”) of the dies formed on a semiconductor wafer are typically tested
after fabrication. Id. ¶ 4. In such testing, Appellant discloses that a wafer
prober may be used to test the functionality and performance of each die on
the wafer, whereby the dies are classified based on performance. Id.
Appellant discloses “methods for generating full wafer maps showing
predicted classifications of dies of a wafer without testing all of the dies on
the wafer.” Id. ¶ 5.
Claim 11, reproduced below from the Claims Appendix to the Appeal
Brief, is illustrative of the claimed subject matter:
11. A method for reconstructing wafer maps of
semiconductor wafers comprising a plurality of dies,
comprising:
receiving, by a processor, test data of characteristics of
dies at sparse sampling locations of a semiconductor wafer, the
sparse sampling locations being selected based on a probing
mask; and

and 19 as reciting allowable subject matter, but depending from rejected
claims. Final Office Action (“Final Act.”) dated December 12, 2019, 1, 2,
and 6.
3 This Decision also cites to the Examiner’s Answer (“Ans.”) dated July 7,
2020, and the Reply Brief (“Reply Br.”) filed August 13, 2020.
Appeal 2020-005920
Application 16/107,942

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computing, by the processor, a reconstructed wafer map
comprising reconstructed characteristics of all of the dies of the
semiconductor wafer by performing compressed sensing with
Zernike polynomials on the test data of the dies at the sparse
locations of the semiconductor wafer.
REFERENCES
The Examiner relies on the following prior art:
Name Reference Date
Neureuther et al.
(“Neureuther”)
US 2003/0103189 A1 June 5, 2003
Burch et al. (“Burch”) US 2007/0288185 A1 Dec. 13, 2007
Pandev et al. (“Pandev”) US 2017/0076440 A1 Mar. 16, 2017
Zhang et al. (“Zhang”) US 2017/0351952 A1 Dec. 7, 2017
Fouquet et al.
(“Fouquet”)
US 2018/0365369 A1 Dec. 20, 2018

REJECTIONS
The Examiner maintains, and Appellant requests our review of, the
following rejections under 35 U.S.C. § 103(a):
1. Claims 11, 12, and 14 as unpatentable over Neureuther in view
of Pandev;
2. Claim 15 as unpatentable over Neureuther in view of Pandev,
and further in view of Zhang;
3. Claims 16 and 18 as unpatentable over Neureuther in view of
Pandev, and further in view of Fouquet;4
4. Claim 17 as unpatentable over Neureuther in view of Pandev
and Fouquet, and further in view of Burch; and

4 The Examiner inadvertently omits claim 18 from this rejection statement,
but discusses claim 18 in the body of this rejection. Final Act. 4–5.
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Application 16/107,942

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5. Claim 20 as unpatentable over Neureuther in view of Pandev,
and further in view of Burch.
OPINION
Rejection 1: Obviousness of Claims 11, 12, and 14
The Examiner rejects claims 11, 12, and 14 as unpatentable over
Neureuther in view of Pandev. Final Act. 2–3. The Examiner finds that
Neureuther discloses a method for reconstructing wafer maps of
semiconductor wafers comprising receiving, by a processor, test data of a
wafer at sparse sampling locations on the wafer selected based on a probing
mask, and computing, by the processor, a reconstructed wafer map by
performing compressed sensing with Zernike polynomials on the test data.
Id. The Examiner acknowledges that Neureuther fails to disclose the wafer
containing a plurality of dies, the test data being characteristic of the dies,
and the reconstruction includes the characteristics of all the dies of the
wafer. Id. at 3. However, the Examiner finds Pandev, being directed to
semiconductor die processing methods, is in the same or similar field of
endeavor as Neureuther and that Pandev discloses each of these features. Id.
The Examiner concludes that it would have been obvious to have processes
Neureuther’s semiconductor dies in accordance with Pandev in order to
improve measurement parameters. Id.
Appellant argues that, contrary to the Examiner’s finding, Neureuther
fails to disclose reconstructing wafer maps of semiconductor wafers. Appeal
Br. 3. Appellant asserts that Neureuther instead is directed to characterizing
aberrations in an imaging lens and lens systems which apply to visual testing
and integrated circuit (“IC”) mask analysis. Id. As such, Appellant contends
that Neureuther applies to semiconductor manufacture only to the extent of
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Application 16/107,942

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disclosing predicting the locations of feature changes in a chip layout due to
aberrations in the lens used to focus an IC patterning beam. Id.
Appellant similarly argues that, contrary to the Examiner’s finding,
Neureuther fails to disclose test data of characteristics of dies at sparse
sampling locations of a semiconductor wafer. Appeal Br. 4. Appellant
asserts that Neureuther merely discloses a technique for constructing a mask
layout and pattern match, without teaching test characteristics of dies at
sparse sampling locations. Id. Appellant contends that Neureuther’s phase-
shift mask layout is a mask for patterning a semiconductor wafer, not a
probing mask for selecting sparse sampling locations. Id. at 4–5.
Appellant additionally argues that, again contrary to the Examiner’s
finding, Neureuther fails to disclose computing a reconstructed wafer map
by performing compressed sensing with Zernike polynomial on the test data
of the dies. Appeal Br. 5. Appellant asserts that Neureuther merely discloses
forming data structures, such as layer maps representing the output of the
pattern matcher and corresponding to the locations of patterns created by
optical aberrations in the lens system. Id. at 6. Appellant contends that
Neureuther computes a representation of patterns using Zernike polynomials
to model optical aberrations in a lens, rather than a reconstructed wafer map
of characteristics of all the dies of a semiconductor wafer. Id. at 6–7.
Appellant’s arguments are persuasive of reversible error. The
Examiner finds that Neureuther teaches that the “underlying wafer
topography can likely also be estimated [. . .] in predicting yield loss due to a
standard normal distribution of misalignment” and finds that such
estimations of wafer topography are equivalent to the claimed reconstruction
of wafer maps. Ans. 4. However, claim 11 requires receiving test data of
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Application 16/107,942

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characteristics of dies at sparse sampling locations of a semiconductor wafer,
the sparse sampling locations being selected based on a probing mask. In
other words, claim 11 requires testing a wafer via a wafer prober at sparse
sampling locations on the wafer. See Spec. ¶¶ 4 (“A wafer prober may be
used [to] test the functionality and performance of each die on the
wafer . . . .”); 8 and 18 (describing generating sparse locations of the probing
mask); 49 (“computing a set of sampling points (a probe mask) to be used
for all wafers of a wafer set”); 59 (describing use of the probing mask and
wafer prober to test a subset of dies to generate the test data). In contrast,
Neureuther discloses estimating or predicting what the wafer structures
would be based on analyzing aberrations in the lens system that is used to
create those structures, rather than testing or probing the wafer dies to
generate the test data.
Further, Neureuther does not assess the wafer structures at sparse
sampling locations or a fraction (subset) of the dies on the wafer. Instead,
Neureuther describes identifying aberrations in the lens system used to
create patterns through a mask, wherein the mask has a probe opening
surrounded by the mask’s pattern geometry. Neureuther ¶ 92; Fig. 16.
Indeed, Neureuther teaches that the probe mask is used to determine
locations in large IC layouts (used to produce pattern structures on a wafer
surface) that are most impacted by aberrations in the projecting lens system
which requires searching across the entire layout via an array of locations
throughout the wafer field. Id. ¶¶ 7, 87, 151, 185. The Examiner fails to
direct our attention to any disclosure in Neureuther suggesting sparse
sampling locations of a semiconductor wafer.
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Appellant’s argument that Neureuther fails to disclose computing a
reconstructed wafer map by performing compressed sensing with Zernike
polynomial on the test data of the dies is also persuasive. As discussed
above, we find the Examiner failed to establish that Neureuther discloses
reconstructing wafer maps of semiconductor wafers by receiving test data of
characteristics of dies at sparse sampling locations of a semiconductor wafer.
As such, we likewise find that Neureuther fails to disclose that such wafer
map reconstruction from test data of characteristics of dies at sparse
sampling locations of a semiconductor wafer is performed by compressed
sensing with Zernike polynomial on the test data of the dies.
Accordingly, we do not sustain the Examiner’s obviousness rejection
of claim 11, and claims 12 and 14 which depend therefrom.
Rejections 2–5: Obviousness of Claims 15–18 and 20
The Examiner rejects claims 15–18 and 20 as unpatentable over
Neureuther in view of Pandev, and further in view of Zhang, Fouquet, and/or
Burch. Final Act. 3–5. However, the Examiner does not rely on any of these
additional tertiary references to remedy the deficiencies in the combination
of Neureuther and Pandev discussed above. Accordingly, we do not sustain
the Examiner’s obviousness rejections of claims 15–18 and 20.

CONCLUSION
Upon consideration of the record and for the reasons set forth above
and in the Appeal and Reply Briefs, the Examiner’s decision to reject claims
11, 12, 14–18, and 20 under 35 U.S.C. § 103 as unpatentable over
Neureuther in view of Pandev, alone or further in view of one or more of
Zhang, Fouquet, and Burch, is reversed.
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Application 16/107,942

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DECISION SUMMARY
In summary:
Claim(s)
Rejected
35
U.S.C. §
Reference(s)/Basis Affirmed Reversed
11, 12,
14
103 Neureuther, Pandev 11, 12, 14
15 103 Neureuther, Pandev,
Zhang
15
16, 18 103 Neureuther, Pandev,
Fouquet
16, 18
17 103 Neureuther, Pandev,
Fouquet, Burch
17
20 103 Neureuther, Pandev,
Burch
20
Overall
Outcome
11, 12, 14–
18, 20

REVERSED