RADWARE, LTD.

Patent Trials and Appeals Board

Dec 24, 2021

2020003272 (P.T.A.B. Dec. 24, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/870,600 09/30/2015 Shy MAROM RADW P0438 8463
122066 7590 12/24/2021
M&B IP Analysts, LLC
150 Morristown Road
Suite 205
Bernardsville, NJ 07924-2626
EXAMINER
KHANAL, SANDARVA
ART UNIT PAPER NUMBER
2453
NOTIFICATION DATE DELIVERY MODE
12/24/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
eofficeaction@appcoll.com
pair@mb-ip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
_______________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_______________

Ex parte SHY MAROM
_______________

Appeal 2020-003272
Application 14/870,600
Technology Center 2400
_______________

Before JEREMY J. CURCURI, NATHAN A. ENGELS, and
JAMES W. DEJMEK, Administrative Patent Judges.

DEJMEK, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1, 5–14, and 18–26. Appellant has canceled claims 2–4 and 15–17.
See Appeal Br. 25–30. We have jurisdiction over the remaining pending
claims under 35 U.S.C. § 6(b).
We affirm in part.

1 Throughout this Decision, we use the word “Appellant” to refer to
“applicant” as defined in 37 C.F.R. § 1.42 (2019). Appellant identifies
RADWARE, LTD as the real party in interest. Appeal Br. 3.
Appeal 2020-003272
Application 14/870,600

2
STATEMENT OF THE CASE
Introduction
Appellant’s disclosed and claimed invention generally relates to “a
system which performs network address translation such that directional
flows land on the same packet-processing thread.” Spec. ¶ 1. Appellant
describes that in a distributed software architecture, including a plurality of
central processing units (CPUs), each CPU may be used to execute a packet-
processing thread. Spec. ¶ 2. In addition, Appellant describes that it is
known to use Receive-Side Scaling (RSS) to distribute packets between
packet-processing threads. Spec. ¶ 3. According to the Specification, RSS
is asymmetric, which means the forward (e.g., client-to-server) packet flow
will end at a particular packet-processing core, but the return direction flow
(e.g., server-to-client) will most likely end at a different packet-processing
core. Spec. ¶¶ 4–5. Moreover, Appellant describes that current approaches
to force symmetric RSS behavior are not effective while performing
Network Address Translation (NAT). Spec. ¶¶ 7–11.
In a disclosed embodiment, Appellant describes a network diagram,
the network comprising an application delivery controller (ADC), a plurality
of client devices, and a plurality of destination servers. Spec. ¶ 25, Fig. 1.
Appellant describes the ADC as including a plurality of processing cores.
Spec. ¶ 26. Additionally, the ADC is configured to distribute network traffic
in a way such that bidirectional flow is always processed by the same core.
Spec. ¶¶ 29–33.
More specifically, Appellant describes that for a particular number of
processing cores, m, the ADC is configured to process only the least number
Appeal 2020-003272
Application 14/870,600

3
of bits, n, of an RSS result of a traffic flow, where the least number of bits,
n, is defined by the equation:
log
Spec. ¶¶ 34–35. As described in the Specification, when a first packet of a
flow is received, a traffic distributor (i.e., functionality within the ADC)
examines n bits from an RSS result and delivers the packet to one of the
processing cores, which sends the packet to a destination server. Spec. ¶ 35.
The processing core also selects a new source port for the back-end flow
“such that the modulo result of the original RSS result is equal to or higher
than the modulo result of the new RSS result.” Spec. ¶ 35. According to the
Specification, this ensures that the same processing core is used for both the
front-end and back-end flows. Spec. ¶ 35.
Claim 1 is exemplary of the subject matter on appeal and is
reproduced below with the disputed limitations emphasized in italics:
1. A method for stateless distribution of bidirectional flows
with network address translation (NAT), comprising:
determining an original source port for a first packet of a
front-end flow received from a client device, wherein the original
source port is associated with a processing core;
selecting a new source port for a back-end flow, wherein
the new source port is selected such that the back-end flow is
returned to the processing core of the front-end flow;
replacing the original source port with the new source port;
and
transmitting the back-end flow with the new source port to
a destination server;
wherein selecting the new source port further comprises:
selecting a port number ensuring that a first number of
least significant bits of a receive-side scaling (RSS) result for the
Appeal 2020-003272
Application 14/870,600

4
front-end flow is identical to a second number of least significant
bits of a RSS result for the back-end flow;
wherein there are more than two processing cores, and
wherein a port number ensures that the first number of
least significant bits of a receive-side scaling (RSS) result for the
front-end flow is identical to the second number of least
significant bits of a RSS result for the back-end flow when a
result of applying a modulo operation between the RSS result for
the front-end flow and the first number is equal to a result of
applying a modulo operation between the RSS result for the
back-end flow and the second number.

The Examiner’s Rejections
1. Claim 26 stands rejected under 35 U.S.C. § 102(a)(2) as being
anticipated by Friend (US 9,712,460 B1; July 18, 2017). Final Act. 6–8.
2. Claims 1, 5, 7–9, 13, 14, 18, and 20–22 stand rejected under
35 U.S.C. § 103 as being unpatentable over Friend and Adam Sawicki, Bit
Tricks with Modulo, Feb. 2011, http://www.asawicki.info/news_1433_
bit_tricks_with_modulo.html (last visited Dec. 13, 2021) (“Sawicki”). Final
Act. 8–12.
3. Claims 6 and 19 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Friend, Sawicki, and Microsoft, Scalable Networking:
Eliminating the Receive Processing Bottleneck—Introducing RSS, WinHEC
2004 Version (April 14, 2004) (“Microsoft”). Final Act. 12–13.
4. Claims 10–12 and 23–25 stand rejected under 35 U.S.C. § 103
as being unpatentable over Friend, Sawicki, and Goel et al. (US
2015/0156271 A1; June 4, 2015) (“Goel”). Final Act. 13–16.

Appeal 2020-003272
Application 14/870,600

5
ANALYSIS2
Claims 1, 5–14, and 18–25
In rejecting independent claims 1 and 14, inter alia, the Examiner
finds Friend teaches all of the limitations except for using a modulo
operation of the RSS result for a front-end flow and a first number, and a
modulo operation of the RSS result for a back-end flow and a second
number, as recited in independent claims 1 and 14. See Final Act. 9–11.
More specifically, the Examiner finds Friend teaches applying an XOR (i.e.,
exclusive-OR) operation, rather than a modulo operation, to the RSS results
of front-end and back-end flows with a first second number, respectively.
See Final Act. 10 (citing Friend, col. 9, l. 10–col. 10, l. 34, col. 11, ll. 38–67,
Abstr.). However, the Examiner finds Sawicki teaches a “modulo operation
is one of the alternatives to XOR operation commonly used in operation.”
See Final Act. 11. As such, the Examiner determines it would have been
obvious to one of ordinary skill in the art to incorporate Sawicki’s teachings
of using a modulo operation as a substitute for an XOR operation into the
system of Friend “so that one could cycle between [a] subsequent range of
numbers.” See Final Act. 11.
Appellant asserts that any alleged equivalence between modulo
operations and XOR operations is limited to a particular case of two values
and that “[t]his means the technique could only be used with two processors
at most rather than more than two as called for by claim 1.” Appeal Br. 9–

2 Throughout this Decision, we have considered the Appeal Brief, filed
September 18, 2019 (“Appeal Br.”); the Reply Brief, filed March 27, 2020
(“Reply Br.”); the Examiner’s Answer, mailed January 31, 2020 (“Ans.”);
and the Final Office Action, mailed March 22, 2019 (“Final Act.”), from
which this Appeal is taken.
Appeal 2020-003272
Application 14/870,600

6
14 (emphases omitted). Moreover, Appellant argues Sawicki teaches XOR
may be used (in very limited applications) as a simplification to using a
modulo operation. Appeal Br. 14, 17. Thus, Appellant argues one of
ordinary skill in the art would not have been motivated to modify Friend’s
XOR operation with a more complex modulo operation. Appeal Br. 14, 17.
In response, the Examiner finds Sawicki teaches an equivalence
between bitwise modulo and bitwise XOR in the particular case of two
values, namely 0 and 1 (i.e., binary numbers). Ans. 5. Thus, the Examiner
determines that “bitwise modulo operation yields the same results as bitwise
XOR operation for binary numbers.” Ans. 6. Further, the Examiner
presents a table that purports to show similar results for bitwise XOR and
bitwise modulo operations for all combinations of 2 digit binary numbers.
See Ans. 8, Table. The Examiner determines that bitwise XOR and bitwise
modulo operations performed on 3-digit binary numbers would also yield
similar results. Ans. 8–9. Thus, the Examiner explains “bitwise modulo
operation yields the same results as bitwise XOR operation for binary
numbers involving n-digits, where n is integer greater than or equal to 1.”
Ans. 9.
In addition, although the Examiner notes that XOR and modulo are
not always mathematically equivalent, the Examiner reasons that for two 1-
bit numbers, one may substitute a modulo operation for an XOR operation,
as suggested by Sawicki. Ans. 15. The Examiner also states that “by
repeatedly performing bitwise modulo operation over each corresponding
pair of bits instead of bitwise XOR operation, one could arrive at the
claimed invention using the teaching of Friend in view of Sawicki.”
Ans. 15, 21–24. Further, the Examiner determines the limitation of
Appeal 2020-003272
Application 14/870,600

7
requiring more than two processing cores is unrelated to the rest of the claim
language and “appears to be an independent claim limitation.” Ans. 18.
In reply, Appellant disputes the Examiner’s determination of an
equivalence between the recited modulo operation and a bitwise XOR
operation. Reply Br. 2–6.
We are mindful that although one of ordinary skill in the art may
understand that two references could be combined as reasoned by the
Examiner, this does not imply a motivation to combine the references.
Personal Web Techs., LLC v. Apple, Inc., 848 F.3d 987 993–94 (Fed. Cir.
2017); see also Belden Inc. v. Berk–Tek LLC, 805 F.3d 1064, 1073 (Fed. Cir.
2015) (“[O]bviousness concerns whether a skilled artisan not only could
have made but would have been motivated to make the combinations or
modifications of prior art to arrive at the claimed invention.”); InTouch
Techs., Inc. v. VGO Communications, Inc., 751 F.3d 1327, 1352 (Fed. Cir.
2014).
As an initial matter, we note that Sawicki describes a modulo
operation as “quite slow.” See Sawicki 1. Thus, in limited applications, an
XOR operation may be performed instead. See Sawicki 1. As described
above, Friend describes a process already using an XOR operation. The
Examiner’s proposed combination would therefore modify Friend with a
modulo operation. See Final Act. 11. To the extent Sawicki teaches an
equivalence between the results of a modulo operation and an XOR
operation—for a particular, limited situation, we do not agree that an
ordinarily skilled artisan would have been motivated to replace Friend’s
XOR operation with a modulo operation (which is “quite slow”).
Appeal 2020-003272
Application 14/870,600

8
Moreover, we do not agree with the Examiner’s tables purporting to
show an equivalence between XOR and modulo operations for binary
numbers. See, e.g., Ans. 6, 8. Referring to the table of single-digit binary
numbers on page 6 of the Answer, we note that 0 mod 1 should be 0, rather
than 1. Further, referring to the table on page 8 of the Answer, there appears
to be a number of errors in the last column (i.e., W Mod Z). For instance, 3
mod 1 is 0. Thus, one would expect 11 (i.e., 3) mod 01 (i.e., 1) to be 00.
The Examiner’s table indicates the result as 10 (i.e., 2). To the extent the
Examiner is trying to distinguish a modulo operation from a type of bitwise
modulo operation, we decline to accept such a distinction as that is an
unreasonably broad construction of the claimed modulo operation and not
consistent with Appellant’s Specification. Thus, as proffered by the
Examiner, we do not find an equivalence between XOR operations and
modulo operations.
For the reasons discussed supra, we are persuaded of Examiner error.
Accordingly, we do not sustain the Examiner’s rejection of independent
claim 1. For similar reasons, we do not sustain the Examiner’s rejection of
independent claim 14, which commensurately recites applying a modulo
operation. In addition, we do not sustain the Examiner’s rejections of claims
5–13 and 18–25, which depend directly or indirectly from either claim 1 or
14.

Claim 26
Independent claim 26 is reproduced below with the disputed
limitation emphasized in italics:
Appeal 2020-003272
Application 14/870,600

9
26. A method for stateless distribution of bidirectional flows
with network address translation (NAT), comprising:
determining an original source port for a first packet of a
front-end flow received from a client device, wherein the original
source port is associated with a processing core;
selecting a new source port for a back-end flow, wherein
the new source port is selected such that the back-end flow is
returned to the processing core of the front-end flow;
replacing the original source port with the new source port;
and
transmitting the back-end flow with the new source port to
a destination server;
wherein selecting the new source port further comprises:
selecting, without using pre-computed values, a port
number ensuring that a first number of least significant bits of a
receive-side scaling (RSS) result for the front-end flow is
identical to a second number of least significant bits of a RSS
result for the back-end flow.
Appellant disputes the Examiner’s finding that Friend anticipates
claim 26. Appeal Br. 19–23; Reply Br. 7–8. In particular, Appellant argues
that Friend describes selecting a port number using pre-computed values—
that is a lookup (or Swizzle) table. Appeal Br. 19. Further, Appellant
argues the Examiner’s rejection disregards the overall method of Friend and
instead focuses on a special case of Friend. Appeal Br. 20–21; Reply Br. 7–
8.
Appeal 2020-003272
Application 14/870,600

10
Figure 3 of Friend is illustrative and is reproduced below:

Figure 3 of Friend illustrates a flowchart of a process for “select[ing] a
local port number for use in ensuring that returning network packets return
to a same device as sending related network packets.” Friend, col. 1, ll. 55–
58.
Appeal 2020-003272
Application 14/870,600

11
As shown in Figure 3 (and as identified by the Examiner), Friend
describes a path wherein the delta error is zero and a local port is therefore
selected without using the Swizzle table. See Final Act. 7–8; Ans. 34–35;
see also Friend, col. 9, l. 53–col. 10, l. 34. Thus, we are unpersuaded of
Examiner error. Accordingly, we sustain the Examiner’s rejection of
independent claim 26.
To the extent Appellant “appeals the determination” by the Examiner
not to enter a proposed amendment to the claim language of claim 26 (see
Appeal Br. 22), we decline to rule on the Examiner’s decision as it is a
petitionable matter rather than an appealable decision. See 37 C.F.R.
§ 41.37 (c)(2) (“Review of an examiner’s refusal to admit an amendment . . .
is by petition to the Director.”); see also 37 C.F.R. § 1.181, MPEP §§ 1201
(“The Board will not ordinarily hear a question that should be decided by the
Director on petition . . . .”), 1205, 2272.

CONCLUSION
We reverse the Examiner’s decision rejecting claims 1, 5–14, 18–25
under 35 U.S.C. § 103.
We affirm the Examiner’s decision rejecting claim 26 under
35 U.S.C. § 102(a)(2).

DECISION SUMMARY
Claim(s)
Rejected
35 U.S.C. § References/Basis Affirmed Reversed
1, 5, 7–9,
13, 14, 18,
20–22
103 Friend, Sawicki 1, 5, 7–9,
13, 14,
18, 20–22
Appeal 2020-003272
Application 14/870,600

12
Claim(s)
Rejected
35 U.S.C. § References/Basis Affirmed Reversed
6, 19 103 Friend, Sawicki,
Microsoft
6, 19
10–12, 23–
25
103 Friend, Sawicki,
Goel
10–12,
23–25
26 102(a)(2) Friend 26
Overall
Outcome
26 1, 5–14,
18–25

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See
37 C.F.R. § 41.50(f).

AFFIRMED IN PART