QUALCOMM Incorporated

Patent Trials and Appeals Board

May 10, 2021

2019006963 (P.T.A.B. May. 10, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/271,403 09/21/2016 Anil Krishna 162811/1173-403 5074
115309 7590 05/10/2021
W&T/Qualcomm
106 Pinedale Springs Way
Cary, NC 27511
EXAMINER
GIROUX, GEORGE
ART UNIT PAPER NUMBER
2125
NOTIFICATION DATE DELIVERY MODE
05/10/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ocpat_uspto@qualcomm.com
patents@wt-ip.com
us-docketing@qualcomm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte ANIL KRISHNA,
VIGNYAN REDDY KOTHINTI NARESH,
and GREGORY MICHAEL WRIGHT
____________

Appeal 2019-006963
Application 15/271,403
Technology Center 2100
____________

Before KALYAN K. DESHPANDE, CHARLES J. BOUDREAU, and
SHARON FENICK, Administrative Patent Judges.

BOUDREAU, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1, 3–14, 17, and 19–28, which are all of
the pending claims. We have jurisdiction under 35 U.S.C. § 6(b)(1).
We REVERSE.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies Qualcomm Incorporated as the real
party in interest. Appeal Br. 3.
Appeal 2019-006963
Application 15/271,403

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CLAIMED SUBJECT MATTER
Appellant’s invention relates to “branch prediction in processor-based
systems capable of processor core fusion,” where “[b]ranch predictors are
processor circuits or logic that attempt to predict an upcoming discontinuity
in an instruction fetch stream, and, if necessary, to speculatively determine a
target instruction block or instruction that is predicted to succeed the
discontinuity,” and “core fusion” is “a feature that enables multiple
individual processor cores to logically ‘fuse’ and work together as a higher-
performing single-threaded processor.” Spec. ¶¶ 1–3.
Claims 1 and 17 are independent. Claim 1, reproduced below, is
illustrative of the subject matter on appeal (emphases added):
1. A distributed branch predictor for a multi-core processor-
based system, comprising:
a plurality of processor cores configured to interoperate
as a fused processor core, and each comprising:
a branch predictor; and
a plurality of predict-and-fetch engines (PFEs);
and
each processor core of the plurality of processor cores
configured to:
receive, from a second processor core of the
plurality of processor cores, a program identifier
associated with an instruction block and corresponding to
the processor core as a received program identifier;
allocate a PFE of the plurality of PFEs for storing
the received program identifier;
predict, using the branch predictor, a subsequent
program identifier as a predicted program identifier;
identify, based on the predicted program identifier,
a processor core of the plurality of processor cores
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corresponding to the predicted program identifier as a
target processor core;
store an identifier of the target processor core in
the PFE;
send the predicted program identifier to the target
processor core;
initiate a fetch of one of a header for the
instruction block and one or more instructions of the
instruction block based on the received program
identifier;
receive an instruction window tracker identifying a
processor core of the plurality of processor cores as an
execution processor core for the received program
identifier;
store an identifier of the execution processor core
in the PFE;
receive the one of the header for the instruction
block and the one or more instructions of the instruction
block as fetched data;
send the fetched data to the execution processor
core for the received program identifier;
identify a processor core of the plurality of
processor cores as an execution processor core for the
predicted program identifier;
send an instruction window tracker identifying the
execution processor core for the predicted program
identifier to the target processor core, based on the PFE;
and
deallocate the PFE.
Appeal Br. 15–16 (Claims App.).
Appeal 2019-006963
Application 15/271,403

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REJECTIONS2
The Examiner rejects claims 1, 3–10, 17, and 19–26 under 35 U.S.C.
§ 103 as being unpatentable over Burger3 and Akkary.4 Final Act. 9–18.
The Examiner rejects claims 11–14, 27, and 28 under 35 U.S.C. § 103
as being unpatentable over Burger, and Akkary, and Bonanno.5 Final
Act. 19–22.
OPINION
Independent claim 1 recites, inter alia, “receiv[ing] an instruction
window tracker identifying a processor core of the plurality of processor
cores as an execution processor core for the received program identifier” and
“send[ing] an instruction window tracker identifying the execution processor
core for the predicted program identifier to the target processor core, based
on the PFE.” Independent claim 17 recites similar limitations. With respect
to these limitations, the Examiner states:
Burger is relied upon for teaching receiving and sending, by the
processor cores, trackers (identifiers) of blocks of instructions,
based upon predictions performed in the processor cores, to
identify and move execution of blocks of instructions between
processor cores . . . while Akkary is relied upon for teaching
that a block/group of instructions may be grouped as an
instruction window . . . . Therefore, in the combination, this

2 Rejections of claim 15 under 35 U.S.C. § 112(b) and 35 U.S.C. § 103 have
been withdrawn in view of Appellant’s cancellation of claim 15. See
Advisory Action (Jan. 31, 2019) 1–2 (entering amendment canceling claim
15; not listing claim 15 among “Claim(s) rejected”); Final Act. 6–8, 13.
3 Burger et al., US 2010/0146249 A1 (pub. June 10, 2010).
4 Akkary et al., US 2003/0196075 A1 (pub. Oct. 16, 2003).
5 Bonanno et al., US 2009/0204797 A1 (pub. Aug. 13, 2009).
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“instruction window” is to be used as the (instruction block)
which is identified/tracked by an identifier passed between
cores, in the system of Burger.
Ans. 3–4 (citing Burger ¶¶ 29–32, 37–40; Akkary ¶¶ 3–4); see also
Advisory Act. 2. According to the Examiner, it would have been obvious to
one of ordinary skill in the art to “use the instruction window tracking taught
by Akkary in the multicore processors of the system of Burger.” Final
Act. 12.
Appellant argues that, while the cited portions of Akkary discuss an
instruction window,
Akkary does not disclose or suggest the “promote wave”
functionality in claim 1, whereby “processor cores” are
configured to “receive” and “send” “instruction window
tracker[s]” between each other to identify and move execution
of “instructions” between different “processor cores” based on
other “processor cores” performing “predictions” in “predict-
and-fetch engines (PFEs).” All that Akkary discloses in
paragraphs 0003-0004 therein is an “out-of-order” processor
where “instructions” can be assigned to “different execution
units.”
Appeal Br. 12–13.6
We agree with Appellant that the combination of Burger and Akkary
fails to teach or suggest receiving “an instruction window tracker identifying
a processor core of the plurality of processor cores as an execution processor
core for the received program identifier” and sending “an instruction

6 The Specification describes a “promote wave” as a “sequence of execution
proceed[ing] in order from processor core to processor core” in which “[t]he
processor core . . . fetches a header and/or one or more instructions for the
received program identifier, and sends the header and/or the one or more
instructions to the appropriate processor core for execution.” Spec. ¶ 5.
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window tracker identifying the execution processor core for the predicted
program identifier to the target processor core, based on the PFE,” as recited
in independent claims 1 and 17. See Appeal Br. 11–13. As pointed out by
Appellant, the portions of Akkary cited by the Examiner generally disclose
an instruction window containing processor instructions and that different
processor instructions in the instruction window “can be scheduled to be
executed by different execution units.” Akkary ¶¶ 3–4; see Appeal
Br. 12–13. The Examiner proposes using Akkary’s instruction window as
Burger’s “(instruction block) which is identified/tracked by an identifier
passed between cores.” Ans. 4. However, the Examiner does not show, and
we do not discern, where Akkary teaches or suggests instruction windows
identifying execution processor cores for received or predicted program
identifiers. Nor does the Examiner show, and we do not discern, where
Burger teaches or suggests that its instruction blocks, or identifiers tracking
such instruction blocks, identify an execution processor core for the received
program identifier, or are sent to the target processor core while identifying
the execution processor core for the predicted program identifier.
Accordingly, we reverse the Examiner’s § 103 rejections of
independent claims 1 and 17 and claims 3–14 and 19–28 dependent from
them.
CONCLUSION
The Examiner’s rejections of claims 1, 3–14, 17, and 19–28 under
35 U.S.C. § 103 are reversed.

Appeal 2019-006963
Application 15/271,403

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DECISION SUMMARY
In summary:

REVERSED

Claim(s)
Rejected 35 U.S.C. §
Reference(s)/
Basis Affirmed Reversed
1, 3–10, 17,
19–26
103 Burger, Akkary 1, 3–10, 17,
19–26
11–14, 27, 28 103 Burger, Akkary,
Bonanno
11–14, 27, 28
Overall
Outcome
1, 3–14, 17,
19–28