Oracle International Corporation

Patent Trials and Appeals Board

Dec 2, 2021

2020003091 (P.T.A.B. Dec. 2, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/317,691 06/27/2014 Christopher H. Olson 6000-67600 1377
58467 7590 12/02/2021
Kowert Hood Munyon Rankin & Goetzel (Oracle)
1120 S. Capital of Texas Hwy
Building 2, Suite 300
AUSTIN, TX 78746
EXAMINER
CALDWELL, ANDREW T
ART UNIT PAPER NUMBER
2100
NOTIFICATION DATE DELIVERY MODE
12/02/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patent_docketing@intprop.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte CHRISTOPHER H. OLSON, JEFFREY S. BROOKS,
and ALBERT DANYSH
____________

Appeal 2020-003091
Application 14/317,691
Technology Center 2100
____________

Before JOSEPH L. DIXON, JAMES R. HUGHES, and
DENISE M. POTHIER, Administrative Patent Judges.

POTHIER, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
This case returns to us from a previous appeal to the Board, where the
rejection of claims 1–20 under 35 U.S.C. § 101 was affirmed. October 2018
Decision 1, 14 (“October 2018 Dec.”).
Appellant elected to reopen prosecution and amended independent
claims 1, 8, and 15.
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Appellant1,2 again appeals under 35 U.S.C. § 134(a) from the
Examiner’s rejection of claims 1–20 under 35 U.S.C. § 101. See Appeal Br.
10.
We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM.
CLAIMED SUBJECT MATTER
Appellant’s invention relates to an apparatus, method, and system
“disclosed for performing arithmetic operations.” Spec., Abstr.
Claim 8 is reproduced below:
8. A method, comprising:
in response to determining that an operation received by a
processor corresponds to a divide operation, issuing, by an
instruction fetch unit of the processor, the divide operation
to an arithmetic logic unit (ALU) of the processor;
storing, by a load store unit of the processor, a first operand and
a second operand into a data cache, wherein a value of the
first operand and a value of the second operand each include
respective binary-coded decimal (BCD) values; and
executing, by the ALU, the divide operation to perform division
using the first and second operands, wherein performing the
division comprises:
retrieving, by the ALU, the first operand and the second
operand from the data cache;

1 Throughout this opinion, we refer to (1) the Final Office Action (Final
Act.) mailed May 7, 2019, (2) the Appeal Brief (Appeal Br.) filed December
5, 2019, (3) the Examiner’s Answer (Ans.) mailed January 22, 2020, and (4)
the Reply Brief (Reply Br.) filed March 18, 2020.
2 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42(a). Appellant identifies the real party in interest as Oracle
International Corporation. Appeal Br. 3.
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scaling, by the ALU, the value of the first operand and the
value of the second operand to generate a first scaled
value and a second scaled value, respectively;
compressing, by the ALU, the first scaled value to generate
a first compressed value;
compressing, by the ALU, the second scaled value to
generate a second compressed value by replacing a
fractional portion of the second scaled value with a non-
BCD value;
wherein a number of data bits included in the first
compressed value is less than a number of data bits
included in the first scaled value, and a number of data
bits included in the second compressed value is less than
a number of data bits included in the second scaled value;
and
estimating, by the ALU, a portion of a result of the divide
operation dependent upon the first compressed value and
the second compressed value.
Appeal Br. 28–29 (Claims App.) (emphasis added indicating claim language
added since last appeal).
THE INELIGIBLITY REJECTION
Claims 1–20 are rejected under 35 U.S.C. § 101 as being directed to
patent-ineligible subject matter. Final Act. 2–3; Ans. 3–4. Appellant argues
(1) claims 1, 5, 7, 8, 12, 14, 15, 19, and 20 as a group and (2) dependent
claims 2–4, 6, 9–11, 13, and 16–18 as a group. Appeal Br. 13–25. We
select claims 8 and 9 as representative. See 37 C.F.R. § 41.37(c)(1)(iv).

LEGAL FRAMEWORK
An invention is patent-eligible if it claims a “new and useful process,
machine, manufacture, or composition of matter.” 35 U.S.C. § 101.
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However, the Supreme Court has long interpreted 35 U.S.C. § 101 to include
implicit exceptions: “[l]aws of nature, natural phenomena, and abstract
ideas” are not patentable. See Alice Corp. v. CLS Bank Int’l, 573 U.S. 208,
216 (2014).
In determining whether a claim falls within an excluded category, we
are guided by the Supreme Court’s two-step framework, described in Mayo
and Alice. Id. at 217–18 (citing Mayo Collaborative Servs. v. Prometheus
Labs., Inc., 566 U.S. 66, 75–77 (2012)). Under that framework, we first
determine what concept the claim is “directed to.” See Alice, 573 U.S. at
219; see also Bilski v. Kappos, 561 U.S. 593, 611 (2010). Concepts
determined to be abstract ideas, and thus patent ineligible, include certain
methods of organizing human activity, such as fundamental economic
practices (Alice, 573 U.S. at 219–20; Bilski, 561 U.S. at 611); mathematical
formulas (Parker v. Flook, 437 U.S. 584, 594–95 (1978)); and mental
processes (Gottschalk v. Benson, 409 U.S. 63, 69 (1972)).
If the claim is “directed to” an abstract idea, we turn to the second
step of the Alice and Mayo framework, where “we must examine the
elements of the claim to determine whether it contains an ‘inventive
concept’ sufficient to ‘transform’ the claimed abstract idea into a
patent-eligible application.” Alice, 573 U.S. at 221 (internal quotation marks
omitted). “A claim that recites an abstract idea must include ‘additional
features’ to ensure ‘that the [claim] is more than a drafting effort designed to
monopolize the [abstract idea].’” Id. (quoting Mayo, 566 U.S. at 77).
“[M]erely requir[ing] generic computer implementation[] fail[s] to transform
that abstract idea into a patent-eligible invention.” Id.
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The PTO published revised guidance concerning 35 U.S.C. § 101.
2019 Revised Patent Subject Matter Eligibility Guidance (“2019
Guidance”), 84 Fed. Reg. 50 (Jan. 7, 2019).3 Under this guidance, we first
look to whether the claim recites:
(1) any judicial exceptions, including certain groupings of abstract
ideas (i.e., mathematical concepts, certain methods of organizing
human interactions such as a fundamental economic practice, or
mental processes) (“Step 2A, Prong One”); and
(2) additional elements that integrate the judicial exception into a
practical application (see MPEP § 2106.05(a)–(c), (e)–(h)) (“Step 2A,
Prong Two”).
See 2019 Guidance, 84 Fed. Reg. 50–52, 54–55.
If a claim (1) recites a judicial exception and (2) does not integrate
that exception into a practical application, we further consider whether the
claim:
(3) adds a specific limitation beyond the judicial exception that is not
“well-understood, routine, conventional” in the field (see MPEP
§ 2106.05(d)); or
(4) simply appends well-understood, routine, conventional activities
previously known to the industry, specified at a high level of
generality, to the judicial exception (“Step 2B”).
See 2019 Guidance, 84 Fed. Reg. at 56.

3 The Office’s current eligibility guidance may also be found in the most
recent update to the Manual of Patent Examination Procedure (MPEP),
Ninth Edition, Revision 10.2019 (revised June 2020). See MPEP §§ 2103
through 2106.07(c).
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ANALYSIS
Claims 1, 5, 7, 8, 12, 14, 15, 19, and 20
The Examiner determines claim 8, including “[a]ll of the steps recited
in” claim 8, are directed to “performing division via a mathematical
algorithm” and “fall with[in] the ‘Mathematical Concepts’ grouping of
abstract ideas.” Final Act. 2; see Ans. 3. The rejection further indicates that
the abstract idea “is not integrated into a practical application,” and in
particular, the recited “instruction fetch unit,” “ALU,” “load store unit,”
“data cache,” and “processor” found in claim 8 do not “constitute a
particular machine,” but rather are “generic elements” (Final Act. 2) that “do
not impose any meaningful limitations on practicing the abstract ideas” (id.
at 2–3). See also Ans. 3–5. The Examiner also analyzes the claims under
Steps 2A and 2B of the 2019 Guidance. See id. at 3–4.
Based on the record, we find no error.
Preliminary Assertion
Appellant argues that the Examiner did not apply the 2019 Guidance.
See Appeal Br. 11; see also Reply Br. 2. To the extent Appellant asserts the
Examiner failed to follow the 2019 Guidance, this argument concerns a
petitionable matter, which is not within the jurisdiction of the Board. See
MPEP §§ 1002 and 1201; see also In re Hengehold, 440 F.2d 1395, 1403
(CCPA 1971) (stating that there are many kinds of decisions made by
examiners, “which have not been and are not now appealable to the board or
to this court when they are not directly connected with the merits of issues
involving rejections of claims, but traditionally have been settled by petition
to the Commissioner.”). Moreover, the Examiner discusses and analyzes the
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claims under the 2019 Guidance in the Examiner’s Answer. See Ans. 3–4
(discussing Step 2A, Prongs 1 and 2 and Step 2B).
The Judicial Exception — Revised Step 2A, Prong 1
The Examiner finds all the steps of the claims, including claim 8, are
directed to “performing division via a mathematical algorithm” and “fall
with[in] the ‘Mathematical Concepts’ grouping of abstract ideas.” Final
Act. 2. The rejection thus has identified an abstract idea addressed by the
courts—mathematical concepts. See 2019 Guidance at 52.
Claim 8 is reproduced below, with the claim limitations that recite the
abstract idea in italics:
A method, comprising:
in response to determining that an operation received by a processor
corresponds to a divide operation, issuing, by an instruction fetch
unit of the processor, the divide operation to an arithmetic logic
unit (ALU) of the processor;
storing, by a load store unit of the processor, a first operand and a
second operand into a data cache, wherein a value of the first
operand and a value of the second operand each include respective
binary-coded decimal (BCD) values; and
executing, by the ALU, the divide operation to perform division using
the first and second operands, wherein performing the division
comprises:
retrieving, by the ALU, the first operand and the second operand
from the data cache;
scaling, by the ALU, the value of the first operand and the value of
the second operand to generate a first scaled value and a
second scaled value, respectively;
compressing, by the ALU, the first scaled value to generate a first
compressed value;
compressing, by the ALU, the second scaled value to generate a
second compressed value by replacing a fractional portion of
the second scaled value with a non-BCD value;
wherein a number of data bits included in the first compressed
value is less than a number of data bits included in the first
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scaled value, and a number of data bits included in the second
compressed value is less than a number of data bits included in
the second scaled value; and
estimating, by the ALU, a portion of a result of the divide
operation dependent upon the first compressed value and the
second compressed value.
Appeal Br. 28–29 (Claims App.) (emphases added).
Performing division and estimating a portion of the divide operation’s
result using two operands involves mathematical concepts (e.g.,
mathematical equations, calculations, and relationships). See 2019
Guidance, 84 Fed. Reg. at 52 (explaining that the grouping of “Mathematical
concepts” includes “mathematical relationships, mathematical formulas or
equations, and mathematical calculations”). As recited in claim 8,
“executing . . . the divide operation to perform division using the first and
second operands” additionally involves “scaling . . . the value of the first
operand and the value of the second operand to generate a first scaled value
and a second scaled value, respectively,” “compressing . . . the first scaled
value to generate a first compressed value,” “compressing . . . the second
scaled value to generate a second compressed value by replacing a fractional
portion of the second scaled value with a non-BCD value,” “wherein a
number of data . . . included in the first compressed value is less than a
number of data . . . included in the first scaled value, and a number of data . .
. included in the second compressed value is less than a number of data . . .
included in the second scaled value,” and “estimating . . . a portion of a
result of the divide operation dependent upon the first compressed value and
the second compressed value.” Thus, claim 8, as a whole, focuses on a
divide operation (e.g., a mathematical algorithm or manipulating numbers)
by scaling values through compression so that the number of data bits in a
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first and second compressed value is less the number of data bits in the first
and second scaled value and estimating a portion of a result dependent on
the compressed values.
The Specification also supports the claimed steps are drawn to
mathematical algorithms that compute or manipulate numbers as part of a
division and estimation operations. Spec. ¶¶ 67, 71, 80, Figs. 6–7, steps 605,
702 (describing scaling operand values by shifting the decimal place of an
operand), ¶¶ 72–74, 80, Figs. 6–7, steps 606, 703 (describing compressing a
number by truncating a value to an integer value or compressing a fractional
part into a fixed number of bits that is less than original number of bits, such
as from 0.63333 to two or three binary bits (e.g., “10” or “101”)), ¶¶ 75, 81–
83, Figs. 6–7, steps 607, 704-709 (computing minimum and maximum
values to determine if values provides enough accuracy for most
calculations). Court cases demonstrate claim 8’s steps of gathering,
computing, and manipulating information (e.g., operands, operand values,
compressed values, scaled values, and a result portion) are directed to an
abstract idea. See Elec. Power Grp., LLC v. Alstom S.A., 830 F.3d
1350, 1353 (Fed. Cir. 2016); Content Extraction & Transmission LLC v.
Wells Fargo Bank, Nat’l Ass’n, 776 F.3d 1343, 1347 (Fed. Cir. 2014).
Thus, like the Examiner found (see Final Act. 2), claim 8’s focus is to
a process for solving the above type of mathematical problem (e.g., a divide
operation and an estimation operation) or mathematical algorithms. Also,
like Benson, the heart of claim 8 is a sequence of instructions or functions
for a digital computer (e.g., a processor’s ALU). See Benson, 409 U.S. at
65; see also SAP Am., Inc. v. InvestPic, LLC, 898 F.3d 1161, 1163 (Fed. Cir.
2018) (stating the subject of the claims are “nothing but a series of
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mathematical calculations based on selected information” and are “ineligible
subject matter”); id. at 1167 (stating “[t]he focus of the claims . . . is on
selecting certain information” and “analyzing it using mathematical
techniques,” which “is all abstract.”)
Additionally, the above-identified recitations as well as italicized step
of “in response to determining that an operation . . . corresponds to a divide
operation, issuing . . . the divide operation,” “storing . . . a first operand and
a second operand,” and “retrieving . . . the first operand and the second
operand” are mental processes that can be performed in the human mind or
with the aid of pen and paper. See 2019 Guidance 52 (indicating “Mental
processes” include “concepts performed in the human mind”); see also
Benson, 409 U.S. at 67 (stating “the conversion of BCD numeral to pure
binary numeral can be done mentally through use of the foregoing table”).
Also, the recited steps can be viewed as mental steps because the noted steps
involve collecting, identifying, and analyzing data—all of which can be
accomplished by the human mind or with the assistance of pen and paper.
See 2019 Guidance at 52; see also Elec. Power Grp., LLC v. Alstom S.A.,
830 F.3d 1350, 1353–54 (Fed. Cir. 2016) (explaining that “analyzing
information by steps people go through in their minds . . . without more” is a
mental process within the abstract-idea category); Smart Sys. Innovations,
LLC v. Chicago Transit Auth., 873 F.3d 1364, 1372 (Fed. Cir. 2017)
(concluding “the collection, storage, and recognition of data” was abstract);
In re TLI Comm’ns LLC Patent Litigation, 823 F.3d 607, 611 (Fed. Cir.
2016) (indicating storing digital images is an abstract idea); Cybersource
Corp. v. Retail Decisions, Inc., 654 F.3d 1366, 1372–73 (Fed. Cir. 2011)
(indicating its claimed “method steps [that] can be performed in the human
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mind, or by a human using pen and paper” included “data-gathering steps”
did not confer patent eligibility).
We further note that “[a]dding one abstract idea (math) to another
abstract idea” (e.g., mental processes) “does not render the claim non-
abstract.” See RecogniCorp, LLC v. Nintendo Co., 855 F.3d 1322, 1327
(Fed. Cir. 2017).
Appellant does not challenge that performing division or other noted
steps (e.g., determining an operation corresponds to a divide operation,
storing operands, retrieving operands, and estimating a portion) recited in
claim 8 are not abstract ideas in the Appeal Brief. Rather, Appellant’s
assertions relate to Revised Step 2A, Prong 2 of the 2019 Guidance, which
we address below. See Appeal Br. 13–19, 22–25.
For the first time in the Reply Brief, Appellant argues that scaling and
compressing are additional elements of the claims and thus not part of the
claims’ abstract idea. See Reply Br. 5. Although untimely raised4, we
disagree with Appellant. As claimed, the “division operation”—part of the
above-identified judicial exception—includes “scaling” the operands and
“compressing” the scaled values. See Appeal Br. 28–29 (Claims App.).
Also, as previously discussed, the identified judicial exception involves both
mathematical concepts and mental processes in performing the divide
operation, which involves both the “scaling” and “compressing” steps.

4 Appellant did not raise that argument in the opening brief and good cause
has not been shown why this argument should be considered. 37 C.F.R.
§ 41.41(b)(2) (2021); Ex parte Borden, 93 USPQ2d 1473, 1474 (BPAI
2010) (informative) (“[T]he reply brief [is not] an opportunity to make
arguments that could have been made in the principal brief on appeal to
rebut the Examiner’s rejections, but were not.”).
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For the above reasons, we are not persuaded that the Examiner erred
in determining that the claims recite a judicial exception.
Integration into a Practical Application — Revised Step 2A, Prong 2
Because the claims recite at least one judicial exception, we next
determine whether the claims as a whole integrate the abstract idea into a
practical application. 2019 Guidance, 84 Fed. Reg. at 54. To determine
whether the judicial exception is integrated into a practical application, we
identify whether there are “any additional elements recited in the claim
beyond the judicial exception(s)” and evaluate those elements alone and
collectively to determine whether they integrate the judicial exception into a
recognized practical application. 2019 Guidance, 84 Fed. Reg. at 54–55
(emphasis added); see also Manual of Patent Examining Procedure
(“MPEP”) § 2106.05(a)-(c), (e)-(h).
We, as did the Examiner, find the additional limitations in claim 8 do
not integrate the judicial exception into a practical application. See Final
Act. 2–3; Ans. 3. More particularly, the claims do not recite (i) an
improvement to the functionality of a computer or other technology or
technical field (see MPEP § 2106.05(a)); (ii) the judicial exception is applied
with or used by a “particular machine” (see MPEP § 2106.05(b)); (iii) a
particular transformation of an article to a different thing or state (see MPEP
§ 2106.05(c)); or (iv) any other meaningful limitation (see MPEP
§ 2106.05(e)). See also 2019 Guidance, 84 Fed. Reg. at 55; see also Final
Act. 2–3.
Regarding claim 8, the additional elements beyond the judicial
exception are “a processor,” “issuing, by an instruction fetch unit of the
processor, the divide operation to an arithmetic logic unit (ALU) of the
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processor,” “a load store unit of the processor,” “a data cache,” and “data
bits.” Appeal Br. 28–29 (Claims App.); see also Final Act. 2 (noting “a
fetch unit,” “an ALU,” “processor,” “load store unit,” and “data cache”
when addressing that the abstract idea is not integrated into a practical
application); Ans. 3 (noting these components as “additional elements”).
Appellant does not contend that these additional elements themselves are a
technological improvement (see Appeal Br. 16–19, 22–24), and we agree
with the Examiner that these elements amount to generic
computer/processing elements (see Final Act. 2). See discussion of items
(i)–(ii), infra.
As for item (ii) above, Appellant argues that “‘performing division’ is
in fact implemented by a ‘particular machine . . . that is integral to the
claim,’ and is thus integrated into a practical application . . . .” Appeal Br.
14 (citing 2019 Guidance 84 Fed. Reg. at 55). Appellant argues that the
Examiner has not considered the claims as a whole. Id. at 15 (citing 2019
Guidance 84 Fed. Reg. 50, 55). Appellant argues that claim 85 does not
recite a generic machine but rather a particular machine—“a processor that
executes instructions to perform division—and moreover, contains circuity
that performs recited sub-operations (scaling, compressing, and estimating)
in order to do so.” Id.
We are not persuaded. The rejection considered the claims as a
whole. See Ans. 3–4. Also, claim 8 does not recite “circuitry” explicitly,
but rather an ALU that performs the noted “sub-operations.” See Appeal Br.

5 Appellant contend “the arguments . . . have primarily been directed to
aspects of claim 1” but that “similar arguments apply to independent claims
8 and 15.” Appeal Br. 19.
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28–29 (Claims App.). We further underscore that the “sub-operations” of
performing division in claim 8, discussed by Appellant, are part of judicial
exception, not additional elements recited in the claim beyond the judicial
exception. See 2019 Guidance, 84 Fed. Reg. at 55 (stating the Office should
“identif[y[] whether there are any additional elements recited in the claim
beyond the judicial exception” and “evaluat[e] those additional elements
individually and in combination to determine whether they integrated the
exception into a practical application”) (emphasis added).
We additionally disagree that the additional elements, the ALU and
the processor, comprise a particular machine or particular machines that
implement the identified judicial exception as Appellant argued. Rather, the
ALU is recited as a general purpose computer (e.g., a processor’s ALU)
performing the above-noted judicial exception (e.g., implementing the
division and estimation operations involving mathematical concepts and
mental processes as previous discussed), which is not a patentable
application or integration of the judicial exception. See Alice, 573 U.S. at
222 (stating “[w]e accordingly “held that simply implementing a
mathematical principle on a physical machine, namely a computer, [i]s not a
patentable application of that principle.”) (citation omitted), 223 (stating “the
mere recitation of a generic computer cannot transform a patent-ineligible
abstract ide into a patent-eligible invention.”). The courts have found
“precisely the holding of the Supreme Court in Gottschalk v. Benson,” which
similarly recites a sequence of instructions for a digital computer that
convert signals from BCD to another form (id., 409 U.S. at 65–67), was that
a “purely mental processes can be unpatentable, even when performed by a
computer . . . .” CyberSource Corp., 654 F.3d at 1375; see also Benson, 409
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U.S. at 71–72 (stating “the mathematical formula involved here has no
substantial practical application except in connection with a digital computer
. . .”); Ultramercial, Inc. v. Hulu, LLC, 772 F.3d 709, 716–17 (Fed. Cir.
2014) (indicating its claims were tied to “general purpose computer” and not
“a particular machine.”).
The remaining additional elements in claim 8—the processor’s
instruction fetch unit, the load store unit, data cache, and data bits—are not
identified by Appellant as being part of the purported particular machine that
is integral to claim 8. See, e.g., Appeal Br. 15 (focusing on the processor
that executes the instructions to perform division and the “circuitry” that
performs scaling, compressing, and estimating). Moreover, most of these
elements are not used to perform the divide and estimate operations as
recited. In any event, claim 8 is claimed and disclosed at a high level of
generality as merely general computer hardware for performing the recited
functional limitations, which we identified above as being directed to an
abstract idea.
For example, the “instruction fetch unit” in claim 8 is a general
computer component performing generic computer functions—receiving,
using, and providing data or instructions—that do not include a particular
algorithm for performing these functions. The Specification also describes a
fetch unit as a unit that prepares instructions for execution. Spec. ¶ 3. As
another example, an ALU is described in the Specification as a unit that
performs arithmetic operations, Boolean operations, and other desired
functions, including formatting numbers. Id. ¶¶ 3–4. Thus, the claimed
functions performed in claim 8 (e.g., scale, compress, and estimate
information and retrieve operands responsive to instructions) include
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established, generalized processing functions that processors (computer
components) including an ALU and a fetch unit regularly perform. We
therefore disagree claim 8’s additional elements are non-generic as asserted.
Similarly, the “load store unit,” “data cache,” and “data bits” are
general computer components performing general computer functions and
are part of the abstract idea (e.g., storing data and compressing data) that do
not include a particular algorithm for performing these functions.
See FairWarning IP, LLC v. Iatric Sys., Inc., 839 F.3d 1089, 1096 (Fed. Cir.
2016) (“[T]he use of generic computer elements like a microprocessor or
user interface do not alone transform an otherwise abstract idea into patent-
eligible subject matter”). Rather, these additional elements (e.g., ALU,
instruction fetch unit, and data bits) are merely tools used to perform the
claim’s functions. See MPEP § 2106(d)(I) (explaining that “[m]erely
reciting the words ‘apply it’ (or an equivalent) with the judicial exception, or
merely including instructions to implement an abstract idea on a computer,
or merely using a computer as a tool to perform an abstract idea” by itself is
insufficient to integrate the abstract idea into a practical application); see
Alice, 573 U.S. at 223 (holding “the mere recitation of a generic computer
cannot transform a patent-ineligible abstract idea into a patent-eligible
invention”). Additionally, the Specification describes the additional
elements generally, without any particular structure, and shows each of them
as boxes in Figure 3. See also Spec. ¶¶ 38–39, 42, 45, Fig. 3 (e.g., elements
300, 310, 340, 350, 352); Appeal Br. 6 (mapping elements of claim 8 to the
Specification).
To the extent the “issuing, by an instruction fetch unit of the
processor, the divide operation to an arithmetic logic unit (ALU) of the
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processor,” “executing, by the ALU, the divide operation,” and “retrieving,
by the ALU, the first operand and second operand from the data cache” steps
are not considered part of the abstract idea, these are merely insignificant
extra-solution activity of gathering data so that the information can be
analyzed to determine certain values and data. 2019 Guidance, 84 Fed. Reg.
at 55 n.31 (explaining that extra-solution activities, such as gathering data
and outputting the results of an abstract idea, are insufficient to integrate the
abstract idea into a practical application). Such extra-solution activities do
not confer patent eligibility. See MPEP § 2106.05(g); see also CyberSource
Corp., 654 F.3d at 1375 (explaining that data gathering is insignificant extra-
solution activity); Parker v. Flook, 437 U.S. at 590 (adjusting an alarm limit
based on output of the abstract idea was insufficient to render the claimed
method patent eligible).
Similar additional elements found in claim 8 are recited in claims 1
and 15. Compare Appeal Br. 27 (Claims App.), with id. at 28–31 (Claims
App.). Thus, we further determine the additional elements in claims 1 and
15 do not implement or use the judicial exception with a particular machine
as argued. Claim 15 further recites “an execution unit,” “a memory” and “an
interface.” Id. at 30–31 (Claims App.). The “execution unit,” “memory”
and “interface” are also claimed and disclosed in the Specification at a high
level of generality as merely generic computer hardware for performing the
recited functional limitations, some of which we identified above as being
directed to an abstract idea (e.g., storing data). For example, the recited
“memory” is claimed simply as being “configured to store one or more
program instructions” and the recited “interface” is recited simply as being
“configured to couple the processor and the memory.” The Specification
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further describes these elements and its processor generally and shows them
as boxes. See Spec. ¶¶ 30 (indicating system memory is “not shown”), 32–
33, Fig. 2 (elements 200, 220, 230); Appeal Br. 7 (mapping elements claim
15 to the Specification). Moreover, the recited “interface” simply couples
the processor and memory, and is not involved in implementing the recited
“divide operation” or “estimating” function. Appeal Br. 30 (Claims App.).
These elements are similarly computer tools that do no more than implement
the above-discussed abstract ideas (e.g., performing mathematical concepts
and mental processes discussed above) and do not add enough to implement
the identified judicial exception with a particular machine integral with the
claim.
As for item (i) above, Appellant contends claim 8 as a whole reflects
an improvement in the functioning of a computer or other technology.
Appeal Br. 16–19, 22, 24. Appellant argues that claim 8 “is directed to an
integrated circuit that is capable of operating on BCD-encoded operands
without requiring their prior conversion from BCD to some other format”
and “is directed to a particular hardware implementation for the division of
BCD-encoded operands.” Id. at 16–17; see also id. at 18. Specifically,
Appellant asserts that “using compressed operands to estimate a quotient
digit enables a simpler processor design,” “reducing the number of bits to be
operated on reduces number and/or complexity of hardware devices (e.g.,
transistors and/or logic gates),” and results in “implementing circuitry faster,
smaller, or some combination of the two” as well as “manufacturing cost and
power consumption of the circuit . . . .” Id. at 17 (citing Spec. ¶ 75); see also
id. at 10–11 (citing Spec. ¶¶ 24, 44, 59, 72, 75), 22; Reply Br. 2–4.
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As discussed above, we disagree that claims 1, 8, and 15 are directed
to a “particular hardware implementation for the division of BCD-encoded
operands” as argued. Additionally, the claims do not explicitly recited “an
integrated circuit” as Appellant asserts. As for the noted steps that allegedly
reduce the hardware complexities, costs, and power consumption (Appeal
Br. 17) (identifying steps of using compressed operands to estimate a
quotient and operating on BCD-encoded operands without prior conversion
from BCD to some other format as improving the computer’s function or
other technology), Appellant’s claims, read in light of the Specification, do
not embody an improvement to a computer or other technology. Storing,
retrieving, and processing data in different numeric formats for the general
goal of performing a divide operation (see Spec. ¶¶ 24, 44, 59, 71–76, cited
in part in Appeal Br. 10–11, 17) do not recite any particular technological or
computer improvement. Instead, the claimed subject matter determines,
stores, retrieves, and analyzes information, which is an ineligible abstract
concept. See Elec. Power, 830 F.3d 1350.
Furthermore, the disputed steps (e.g., scaling values, compressing
scaled values, and estimating a portion of a result of the divide operation)
argued by Appellant to improve on the computer or technology are, in
actuality, part of the identified judicial exception of performing a division
operation with two operands as recited that involves mathematical concepts
and mental processes as previously discussed. That is, Appellant’s noted
improvement (e.g., “efficiently implement circuitry to perform a certain type
of mathematical operation in a particular machine and in doing so, enable an
improved design” (Appeal Br. 17)) are elements of the steps identified above
as the abstract idea. But, “a claim for a new abstract idea is still an abstract
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idea.” Synopsys, Inc. v. Mentor Graphics Corp., 839 F.3d 1138, 1151 (Fed.
Cir. 2016). And the additional features in claims 1, 8, and 15 (e.g., the fetch
unit, ALU, processor, data cache, data bits, an execution unit, a load store
unit, a memory, and an interface) are also merely tools to perform their
expected functions rather than a technological improvement. The noted
additional elements merely recite or apply generic computer elements to an
abstract idea, which cannot transform a patent-ineligible abstract idea into a
patent-eligible invention. See Alice, 573 U.S. at 223.
Even considering the additional elements in combination with the
abstract idea, using generic computer-based devices to perform these steps
limits the abstract idea at most to a particular technological environment
(e.g., processors operating on and processing machine-independent number
formats (see Spec. ¶¶ 1, 4–5)), which is insufficient to integrate the abstract
idea into a practical application. See Alice, 573 U.S. at 223; see also Elec.
Power Grp., 830 F.3d at 1354 (stating “limiting the claims to a particular
technological environment . . . is, without more, insufficient to transform
them into patent-eligible applications of the abstract idea at their core.”);
2019 Guidance, 84 Fed. Reg. at 55. Also, “merely adding computer
functionality to increase the speed or efficiency of the process does not
confer patent eligibility on an otherwise abstract idea.” Capital One Bank,
792 F.3d at 1370. We thus disagree with Appellant that the claimed subject
matter improves on a computer or other technical field. See Appeal Br. 16–
19. Rather, the claimed subject matter relates to the above-identified
abstract idea performed by generic computer systems as previously
explained.
As for item (iv) above, Appellant also contends claim 8, as a whole,
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meaningful limits the abstract idea of “performing division” without
foreclosing the use of the abstract idea. Appeal Br. 16. Appellant argues
that “there are numerous ways in which this abstract idea could be
implemented that are not encumbered by the claims.” Id.; see also Reply Br.
2–3. But lack of preemption does not make a claim any less abstract. See
Ariosa Diagnostics, Inc. v. Sequenom, Inc., 788 F.3d 1371, 1379 (Fed. Cir.
2015) (“While preemption may signal patent ineligible subject matter, the
absence of complete preemption does not demonstrate patent eligibility”);
see also Parker v. Flook, 437 U.S. at 589.
Appellant further argues that there is no authority to find “the
improvement conferred by a claim must be inevitable and always present.”
Id. at 18 (citing October 2018 Dec. 8). Additionally, Appellant argues that
there is no authority to determine the “improvement must necessarily follow
from the recitations of claim 1 . . . .” Id. We are not persuaded. As one
example, in DDR Holdings, LLC v. Hotels.com, L.P., 773 F.3d 1245 (Fed.
Cir. 2014), the court found the claims were patent eligible because “[t]he
claimed solution is necessarily rooted in computer technology in order to
overcome a problem specifically arising in the realm of computer networks.”
Id., 773 F.3d at 1257 (emphasis added). In any event and for the above
reasons, we have explained why the additional elements individually and as
combination do not impose a meaningful limit on the identified judicial
exception.
Accordingly, we are not persuaded that the claims integrate the
identified judicial exception into a practical application.
The Inventive Concept —Step 2B
Because we determine the claims are directed to an abstract idea or
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combination of abstract ideas, we evaluate whether the claims include an
inventive concept. See 2019 Guidance, 84 Fed. Reg. at 56. Specifically, we
determine whether the claims (1) add a specific limitation, or combination of
limitations, that is not well-understood, routine, conventional activity in the
field, or (2) simply append well-understood, routine, conventional activities
at a high level of generality. Id. at 56.
The Examiner determined the additional elements do not amount to
significantly more than the abstract idea and the combination of elements
“are well-understood, routine and conventional elements in the data
processing field,” insufficient “to provide an inventive concept.” Ans. 4.
Appellant argues that the ordered combination of recited features that
improves on an integrated circuit and computer functioning are non-
conventional and non-generic because the record indicates the claims are
allowable over the art and thus fails to demonstrate these features are known.
See Appeal Br. 22–23; see also Reply Br. 5. But “§ 101 subject-matter
eligibility is a requirement separate from other patentability inquiries.” See
Return Mail, Inc. v. U.S. Postal Serv., 868 F.3d 1350, 1370 (Fed. Cir.
2017); see also Mayo, 566 U.S. at 90; Diehr, 450 U.S. at 190 (1981) (“The
question . . . of whether a particular invention is novel is ‘wholly apart from
whether the invention falls into a category of statutory subject matter.”’).
In the Reply Brief, Appellant argues “there is no record evidence
supporting this proposition” that the ordered combination is well-known,
routine, and conventional. Reply Br. 5 (underlining omitted). We are not
persuaded. First, the Examiner found the additional elements as well as its
combination are well-understood, routine, and conventional. See Ans. 4.
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Second, in response to Berkheimer v. HP Inc., 881 F.3d 1360 (Fed.
Cir. 2018), reh'g denied en banc, 890 F.3d 1369 (Fed. Cir. 2018), the Office
issued Changes in Examination Procedure Pertaining to Subject Matter
Eligibility, Recent Subject Matter Eligibility Decision (Berkheimer v. HP,
Inc.) (Apr. 19, 2018) (“2018 Memorandum”). Specifically, the 2018
Memorandum states an additional element (or combination of elements) is
not well-understood, routine or conventional to one skilled in the
art unless the Examiner finds and supports the §101 rejection with one or
more of the following: (1) a citation to an express statement in the
Specification or to a statement made by applicants during prosecution
demonstrating the well-understood, routine, and conventional nature of the
additional elements, (2) a citation to one or more court decisions in MPEP
§ 2106.05(d)(II) as noting the well-understood, routine, and conventional
nature of the additional elements, (3) a citation to a publication that
demonstrates the well-understood, routine, and conventional nature of the
additional elements, and (4) a statement that the Examiner is taking official
notice of the well-understood, routine, and conventional nature of the
additional elements. 2018 Memorandum 3–4.
Upon review of the record, the Specification states
Modern processors typically include various functional blocks,
each with a dedicated task. For example, a processor may
include an instruction fetch unit, a memory management unit,
and an arithmetic logic unit (ALU). An instruction fetch unit
may prepare program instructions for execution by decoding
the program instructions and checking for scheduling hazards.
Arithmetic operations such as addition, subtraction,
multiplication, and division as well as and Boolean operations
(e.g., AND, OR, etc.) may be performed by an ALU. Some
processors include high-speed memory (commonly referred to
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as ‘cache memories’ or ‘caches’) used for storing frequently
used instructions or data.

Spec. ¶ 3 (emphases added); see also October 2018 Dec. 10–11 (citing Spec.
¶¶ 3–4 and stating these features are “routine[] and conventional.”). Thus,
the Specification (Spec. ¶ 3) supports that processors are known to include
an instruction fetch unit that prepares program instructions for execution, an
ALU to perform mathematical operations, including division, and a
memory/cache for storing data just as claim 8 recites. See also Reply Br. 4
(stating “all microprocessors fundamentally implement mathematical
operations.”).
As for the additional elements, including the “load storing unit,”
“execution unit,” and “interface” in claims 1 and 15, the courts have
determined that these types of elements are well-known, routine, and
conventional. For example, Mortgage Grader, Inc. v. First Choice Loan
Services Inc., 811 F.3d 1314 (Fed. Cir. 2016) indicates that components,
such an interface and a database, are generic computer components that do
not satisfy the inventive concept requirement. See id. at 1324–35. As other
examples, claim limitations related to additional elements that receive, store,
communicate, and perform mathematical calculations, like the “processor,”
‘instruction fetch unit,” an ALU, “load store unit,” “execution unit,” and
“data bits,” can be considered conventional computer activities, falling
squarely within our precedent finding generic computer components
insufficient to add an inventive concept to an otherwise abstract idea. See
also Alice, 573 U.S. at 226 (“Nearly every computer will include a
‘communications controller’ and a ‘data storage unit’ capable of performing
the basic calculation, storage, and transmission functions required by the
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method claims.”); Content Extraction, 776 F.3d at 1345, 1348 (“storing
information” into memory, and using a computer to “translate the shapes on
a physical page into typeface characters,” insufficient confer patent
eligibility); BuySAFE v. Google, Inc., 765 F.3d 1350, 1355 (Fed. Cir. 2014)
(“That a computer receives and sends the information over a network—with
no further specification—is not even arguably inventive.”).
Additionally, when combining the additional elements found in claim
8, the combination simply appends well-understood, routine, and
conventional activities previously known in the industry specified at a high
level of generality to the judicial exception as previously discussed.
Appellant also contends the claims, as a whole, does not impose a risk
of pre-emption. See Appeal Br. 23–24. As previously noted, lack of
preemption does not make a claim any less abstract. See Ariosa, 788 F.3d at
1379; see also See Parker v. Flook, 437 U.S. at 589.
Accordingly, we are not persuaded that the claims include an
inventive concept.
Conclusion
For the foregoing reasons, Appellant has not persuaded us of error in
the rejection under 35 U.S.C. § 101 of independent claims 1, 8, and 15 and
dependent claims 5, 7, 12, 14, 19, and 20, which are not argued separately.
Claims 2–4, 6, 9–11, 13, and 16–186
As for representative dependent claim 9, Appellant asserts this claim
adds a “lookup table” feature. Appeal Br. 29 (Claims App.). According to

6 As already stated, Appellant argues dependent claims 2, 9, and 16 as a
group. Appeal Br. 19–21, 25. Appellant states “[c]laims 2–4, 6, 9–11, 13,
and 16–18 stand or fall together.” Id. at 19.
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Appellant, the lookup table may be more compact and may be significantly
faster to access, adding a specific improvement in computer performance.
Appeal Br. 19–20 (citing Spec. ¶¶ 85, 91). For this reason and because the
lookup table enables a more compact circuit design, Appellant contends
claim 9 recites significantly more than an abstract idea. Appeal Br. 25–26;
see also Reply Br. 3.
The Judicial Exception — Revised Step 2A, Prong 1
Claim 9 recites a more detailed version of how the step of “estimating
the portion of the result of the operation” is performed, which is part of the
above-identified abstract idea. Additionally, the step of “selecting, from a . .
. table, a given one of a plurality of entries dependent on the first
compressed value and the second compressed value” (Appeal Br. 29 (Claims
App.)) in claim 9 is mental process, which is a judicial exception. See 2019
Guidance at 52; see also Smart Sys. Innovations, 873 F.3d at 1372
(concluding “the collection, storage, and recognition of data” was abstract);
Cybersource, 654 F.3d at 1372-73 (indicating its claimed “method steps
[that] can be performed in the human mind, or by a human using pen and
paper” included “data-gathering steps” did not confer patent eligibility).
Appellant fails to challenge that the “selecting” step in claim 9 is not
part of the above-discussed judicial exception. See Appeal Br. 19–21.
For the above reasons, we are not persuaded that the Examiner erred
in determining that the claims recite a judicial exception.
Integration into a Practical Application — Revised Step 2A, Prong 2
Because the claims recite a judicial exception, we next determine
whether the claims as a whole integrate the abstract idea into a practical
application. 2019 Guidance, 84 Fed. Reg. at 54. Similar to the Examiner
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(Final Act. 2), we also determine the “lookup table” is an additional element
of claim 9. As explained below, we determine claim 9 as a whole does not
integrate the judicial exception into a practical application. See Final Act.
2–3.
More particularly, the Examiner finds the “lookup table” is an
additional element and is a generic element that does not: (1) integrate the
abstract idea into a practical application, (2) impose meaningful limitations
on the abstract idea, or (3) improve a technical field. Final Act. 2–3. We
agree that claim 9 does not recite an improvement to the functionality of a
computer or other technology as argued. Rather, most of the claim’s
limitations focus on improving on the abstract idea that involves using
mathematical concepts and mental processes (e.g., “estimating the portion of
the result of the operation”). But an abstract idea itself cannot integrate the
abstract idea into a practical application. See Trading Techs. Int'l, Inc. v.
IBG LLC, 921 F.3d 1378, 1385 (Fed. Cir. 2019) (quoting SAP, 898 F.3d at
1171 (“The abstract idea itself cannot supply the inventive concept, ‘no
matter how groundbreaking the advance.”’). To the extent that the
“selecting” function in claim 9 is also an additional element beyond the
judicial exception, the recited selection function does not integrate the
judicial exception into a practical application but rather is an insignificant
extra-solution activity to the judicial exception. See MPEP § 2106.05(g);
see also CyberSource Corp., 654 F.3d at 1375 (explaining that data
gathering is insignificant extra-solution activity); Parker v. Flook, 437 U.S.
at 590.
According to Appellant, the lookup table may be more compact and
may be significantly faster to access, adding a specific improvement in
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computer performance. Appeal Br. 19–20 (citing Spec. ¶¶ 85, 91).
However, this additional element (i.e., the lookup table) in claim 9 is
claimed and disclosed at a high level of generality for performing the recited
functional limitations, which we identified above as being directed to an
abstract idea (e.g., selecting data). For example, the Specification describes
lookup table 800 generally as having an index for selecting a corresponding
table entry. See Spec. ¶ 86, Fig. 8. Thus, the noted additional element (e.g.,
the lookup table) merely recites or applies a generic computer element to an
abstract idea, which cannot transform a patent-ineligible abstract idea into a
patent-eligible invention. See Alice, 573 U.S. at 223. The “lookup table” is
a similarly a computer tool that does no more than implement the above-
discussed abstract ideas (e.g., performing mathematical concepts and mental
processes discussed above, which includes estimating the portion of the
result by selecting an entry from the table) and does not add enough to
implement the identified judicial exception with a particular machine
integral with the claim and does not reflect an improvement in a computer or
technical field.
Additionally, as to the asserted technical advantages (e.g., more
compact circuitry and faster access for directly calculating a result) (Appeal
Br. 20), the Specification further indicates “a lookup table may provide a
speed improvement versus calculating Qmax and Qmin for each digit of the
quotient”“[i]f the lookup table is small enough.” Spec. ¶ 85 (emphasis
added). The claimed “lookup table” in claim 9, however, does not recite the
size of the lookup table, such that the table reflects the alleged improved
functioning in the computer or technical field or amounts to a particular
machine that is integral to the claim. See Appeal Br. 29 (Claims App.).
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Similarly, cited paragraph 91 states “[u]sing lookup table 800 may provide a
more efficient method for determining Qmin and Qmax” (Spec. ¶ 91), but
claim 9 does not reflect the alleged improvement in a computer’s
functioning or other technology. Moreover, the alleged improvements
enhances the identified abstract idea rather than a computer/technological
improvement. “[A] claim for a new abstract idea is still an abstract idea.”
Synopsys, Inc. v. Mentor Graphics Corp., 839 F.3d 1138, 1151 (Fed. Cir.
2016). Even more, as previously stated, “merely adding computer
functionality to increase the speed or efficiency of the process does not
confer patent eligibility on an otherwise abstract idea.” Capital One Bank,
792 F.3d at 1370.
Thus, when considering claim 9, as a whole, the recited “lookup
table” and any other additional elements in claim 9 do not add enough to
integrate the judicial exception into a practical application.
Appellant further argues that there is no authority to find “the
improvement conferred by a claim must be inevitable and always present.”
Appeal Br. 18 (citing October 2018 Dec. 8). Additionally, Appellant argues
that there is no authority to determine the “improvement must necessarily
follow from the recitations of claim 1.” Id. We are not persuaded. For
example, in DDR Holdings, LLC v. Hotels.com, L.P., 773 F.3d 1245 (Fed.
Cir. 2014), the court found the claims were found to be patent eligible
because “[t]he claimed solution is necessarily rooted in computer
technology in order to overcome a problem specifically arising in the realm
of computer networks.” Id. at 1257 (emphasis added). In any event, as
discussed above, the claimed “lookup table” is described and claimed
generally in terms of performing generic computer functions of a lookup
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table—selecting entries from the table based on other values, which does not
reflect an improvement in the functioning of a computer or other technology
or provide any other meaningful limitation.
When considering the elements of claim 9 both individually and as a
combination, we determine claim 9’s additional element(s) do not integrate
the judicial exception into a practical application.
The Inventive Concept —Step 2B
Because we determine the claims are directed to an abstract idea or
combination of abstract ideas, we evaluate whether the claims include an
inventive concept. See 2019 Guidance, 84 Fed. Reg. at 56. Specifically, we
determine whether the claims (1) add a specific limitation, or combination of
limitations, that is not well-understood, routine, conventional activity in the
field, or (2) simply append well-understood, routine, conventional activities
at a high level of generality. 2019 Guidance, 84 Fed. Reg. at 56.
The Examiner determined the additional elements, which includes the
recited “lookup table” in claim 9 (Ans. 3), do not amount to significantly
more than the abstract idea and the combination of elements “are well-
understood, routine and conventional elements in the data processing field,”
insufficient “to provide an inventive concept.” Id. at 4.
Appellant argues that the ordered combination of recited features that
improves on an integrated circuit and computer functioning are non-
conventional and non-generic because the record indicates the claims are
allowable over the art and thus fails to demonstrate these features are known.
See Appeal Br. 22–23; see also Reply Br. 5. But, as previously noted,
Ҥ 101 subject-matter eligibility is a requirement separate from other
patentability inquiries.” See Return Mail, 868 F.3d at 1370; see also Mayo,
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566 U.S. at 90; Diehr, 450 U.S. at 190.
Appellant also argues “there is no record evidence supporting this
proposition” that the ordered combination is well-known, routine, and
conventional. Reply Br. 5 (underlining omitted). We are not persuaded.
Mortgage Grader, Inc. v. First Choice Loan Services Inc., 811 F.3d 1314
indicates that components, such a “database,” are generic computer
component that do not satisfy the inventive concept requirement. See id.,
811 F.3d at 1324–35. Similarly, a lookup table, like a database, is a known
computer component for storing and obtaining data. Additionally, to the
extent that “selecting” step in claim 9 is considered an additional element of
the claim, courts have indicated that a step of retrieving information from
memory is well-understood, routine, and conventional activity when claimed
in a generic manner. See Versata Dev. Group, Inc. v. SAP Am., Inc., 793
F.3d 1306, 1334 (Fed. Cir. 2015); see also OIP Techs., Inc., v. Amazon.com,
Inc., 788 F.3d 1359, 1363 (Fed. Cir. 2015). The “selecting, from a lookup
table, a given one of a plurality of entries” step in claim 9 is similar to
retrieving information from memory claimed in a generic manner.
Moreover, when considering the combination of additional element(s) in
claim 9, the combination simply appends well-understood, routine, and
conventional activities previously known in the industry specified at a high
level of generality to the judicial exception as previously discussed.
Accordingly, we are not persuaded that the claims include an
inventive concept.
Conclusion
Accordingly, Appellant has not persuaded us the Examiner erred in
the rejecting claim 9 under 35 U.S.C. § 101 and claims 2–4, 6, 10, 11, 13,
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and 16–18, which are not argued separately.

DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1–20 101 Eligibility 1–20

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED