NVIDIA Corporation

Patent Trials and Appeals Board

Aug 4, 2020

14043461 - (D) (P.T.A.B. Aug. 4, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/043,461 10/01/2013 Ziyad S. HAKURA NVDA/SC-13-0117-US1 8135
102324 7590 08/04/2020
Artegis Law Group, LLP/NVIDIA
7710 Cherry Park Drive Suite T #104
Houston, TX 77095
EXAMINER
MCCULLEY, RYAN D
ART UNIT PAPER NUMBER
2611
NOTIFICATION DATE DELIVERY MODE
08/04/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
jmatthews@artegislaw.com
kcruz@artegislaw.com
sjohnson@artegislaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________
Ex parte ZIYAD S. HAKURA and ROUSLAN DIMITROV
____________________

Appeal 2019-002077
Application 14/043,4611
Technology Center 2600
____________________

Before JOHN A. EVANS, JOHN P. PINKERTON, and
MICHAEL M. BARRY, Administrative Patent Judges.

PINKERTON, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1–4, 8–13, 17–20, and 22, which constitute all the
claims pending in this application. Claims 26 and 27 “are allowed.” Final
Act. 9. Claims 5, 6, 14, and 15 “are objected to as being dependent upon a
rejected base claim, but would be allowable if rewritten in independent form
including all of the limitations of the base claim and any intervening
claims.” Id. Claims 7, 16, 21, and 23–25 are canceled. Appeal Br. 17, 19,
20 (Claims App.). We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies the real party in interest as NVIDIA
Corporation. Appeal Br. 3.
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STATEMENT OF THE CASE
Introduction
Appellant generally describes the disclosed and claimed invention as
relating to “graphics processing and, more specifically, to scheduling cache
traffic in a tile-based architecture.” Spec. ¶ 2.
Claims 1, 10, and 19 are independent. Independent claim 1 is
illustrative of the subject matter on appeal and reads as follows:
1. A tile-based system for processing graphics data, the
system comprising:
a first screen-space pipeline;
a cache unit; and
a first tiling unit that:
determines that a first set of primitives overlaps a
first cache tile,
generates a first prefetch command upon
determining that a second set of primitives
overlaps a first portion of a second cache tile,
but does not overlap a second portion of the
second cache tile, wherein the first prefetch
command causes the cache unit to fetch data
from an external memory unit for only the
first portion of the second cache tile,
transmits the first set of primitives and the first
prefetch command to the first screen-space
pipeline for processing, and
after transmitting the first prefetch command to the
first screen-space pipeline, transmits the
second set of primitives to the first
screen-space pipeline for processing.
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References
Name Reference Date
Duluk, Jr. et al.
(“Duluk”)
US 6,229,553 B1 May 8, 2001
Baldwin US 8,643,659 B1 Feb. 4, 2014
Heeschen et al.
(“Heeschen”)
US 6,380,935 B1 Apr. 30, 2002

Rejections on Appeal
The Examiner rejected claims 1, 2, 8, 10, 11, 17, 19, and 20 under
pre-AIA 35 U.S.C. § 103(a) as being unpatentable over Duluk and Baldwin.
Final Act. 3–5.
The Examiner rejected claims 3, 4, 9, 12, 13, 18, and 22 under
pre-AIA 35 U.S.C. § 103(a) as being unpatentable over Duluk, Baldwin, and
Heeschen. Id. at 6–8.
ANALYSIS
In rejecting claim 1, the Examiner relies on the combined teachings of
Duluk and Baldwin. Final Act. 3–5; see also Advisory Act. 1–2; Ans. 3–7.
Appellant’s arguments center on the following limitation of independent
claim 1:
a first tiling unit that: . . . generates a first prefetch command
upon determining that a second set of primitives overlaps a first
portion of a second cache tile, but does not overlap a second
portion of the second cache tile, wherein the first prefetch
command causes the cache unit to fetch data from an external
memory unit for only the first portion of the second cache tile.
Appeal Br. 10–14; Reply Br. 3–7. Appellant likewise argues that because
“each of independent claims 10 and 19 recite limitations that are
substantially similar to those discussed above with respect to allowable
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claim 1. . . , claims 10 and 19 and all claims dependent thereon, respectively,
are in condition for allowance for at least the reasons set forth herein.”
Appeal Br. 14.
We are not persuaded by Appellant’s arguments. To the extent
consistent with our discussion below, we adopt as our own the Examiner’s
findings, reasoning, and conclusions, as set forth in the Final Office Action
(Final Act. 2–10), Advisory Action (Advisory Act. 1–2), and Examiner’s
Answer (Ans. 3–7). For emphasis, we provide the following discussion that
highlights certain findings, reasons, and arguments before us.
The Examiner relies on Duluk for teaching the following portion of
the disputed limitation: “a first tiling unit that: . . . generates a first prefetch
command upon determining that a second set of primitives overlaps a first
portion of a second cache tile, . . . wherein the first prefetch command
causes the cache unit to fetch data from an external memory unit.” Final
Act. 3–4 (citing Duluk 8:55, 19:20–25, 19:30–35, 30:10–15, Fig. 3). In
particular, the Examiner finds Duluk teaches these claim elements because
Duluk discloses a graphics processor pipeline including a sort block (SRT)
that bins primitives based on the tiles they touch (i.e., intersect or overlap),
processes primitives in tile-by-tile order, and sends a prefetch BeginTile
command to the backend block (BKE) so tiles can be prefetched into PIX-
BKE pixel buffers and the BKE can read from the frame buffer ahead of
time. Duluk, 8:55, 19:20–24, 19:30–35, 30:10–15, Fig. 3, see also id. at
8:16–26, 8:49–55, 14:57–59, 17:14–15, 19:35–41, 20:1–9. Appellant does
not contest these findings of the Examiner.
According to the Examiner, “Duluk does not disclose that the second
set of primitives does not overlap a second portion of the second cache
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tile or prefetching data for only the first portion of the second cache tile.”
Final Act. 4. The Examiner cites Baldwin for teaching or suggesting these
remaining elements of the disputed limitation. Id. It is important to note
here that
[t]he Examiner does not rely on Baldwin to teach tile pre-
fetching. The Examiner relies on Duluk to teach tile pre-fetching,
but since Duluk only discloses pre-fetching entire tiles, Baldwin
is relied on to show that when moving tile data from a tile cache
to a screenspace pipeline, it is obvious to move only a portion of
a tile that intersects with a set of primitives.
Advisory Act. 2.
In particular, the Examiner finds Baldwin discloses, among other
things: (1) a binning subsystem including a rasterizer that tests super tiles,
tiles, and partial tiles to determine which tiles (or pixels therein) are inside or
intersect the edges of a primitive and outputs a tile message (including the
tile’s coordinate and tile mask) that controls the rest of the core; (2) a sub tile
message, coordinate information for the primitive (that the sub tile belongs
to), and sub tile addresses passed to an SD cache; and (3) updating tiles in an
SD cache on a sub tile granularity. Id. (citing Baldwin 19:15–20, 19:25–30);
Advisory Act. 2 (additionally citing Baldwin 13:24–35); Ans. 3–6
(additionally citing Baldwin 13:36–37, 19:40–41, 19:55–57).
The Examiner explains that
[w]hen these points are taken together, Baldwin renders obvious
fetching a sub tile based on an intersection with graphics
primitives. In particular, the recitations “the primitive (that the
sub tile belongs to)” and cache tiles “are updated on a sub tile
granularity,” when taken together and in the context of the whole
SD subsystem, suggest that the sub tiles are identified and
fetched when the sub tiles belong to (i.e. intersects) particular
primitives. Such a configuration aligns with the very nature of
how cache memories work. Cache memories retrieve data from
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external memory that is required for processing. In the context of
the SD subsystem of Baldwin, the data required for processing
the current primitive is a sub tile that intersects the primitive.
Fetching any other sub tile that does not intersect the current
primitive would be superfluous since space in a cache memory
is extremely limited.
Ans. 5.
The Examiner concludes that
it would have been obvious to one having ordinary skill in the art
to use the sub tile granularity caching techniques of Baldwin in
the prefetching tile cache of Duluk. The motivation would have
been to increase efficiency by limiting the amount of data that
needs to be prefetched for any particular operation.
Final Act. 4–5.
Appellant’s arguments do not persuade us that the Examiner’s
findings, reasoning, or conclusion are erroneous. As an initial matter, we are
not persuaded by Appellant’s arguments that neither Duluk nor Baldwin
individually discloses the disputed limitation in its entirety. See, e.g.,
Appeal Br. 10 (arguing that Duluk does not disclose the disputed limitation),
id. at 11–12 (“Baldwin fails to disclose that the subtiles stored within the SD
cache are updated based on an intersection with a set of graphics primitives.
. . . [T]he subtiles in the SD cache are not updated before transmitting a
particular set of graphics primitives to the screen-space pipeline for
processing.”).2 Appellant’s arguments fall short because they attack the

2 See also Reply Br. 3 (“the cited portions [of Duluk] do not disclose a
prefetch command that causes data to be fetched . . . for only a first portion
of a cache tile . . . intersected by a particular set of graphics primitives,
without fetching data for a second portion . . . not intersected”), id. at 4
(“Baldwin also fails to disclose a prefetch command that causes data to be
fetched . . . for only a first portion of a cache tile . . . intersected by a
particular set of graphics primitives, without fetching data for a second
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teachings of Duluk and Baldwin individually without appreciating what the
combined teachings of Duluk and Baldwin would have suggested to those of
ordinary skill in the art. The cited references must be considered for the
entirety of what they teach and suggest to one skilled in the art. See, e.g., In
re Hedges, 783 F.2d 1038, 1039 (Fed. Cir. 1986) (citing In re Wesslau, 353
F.2d 238, 241 (CCPA 1965)). Further, each reference cited by the Examiner
must be read, not in isolation, but for what it fairly teaches in combination
with the prior art as a whole. See In re Merck & Co., 800 F.2d 1091, 1097
(Fed. Cir. 1986). The relevant inquiry is “what the combined teachings of
th[os]e references would have suggested to those of ordinary skill in the art.”
In re Keller, 642 F.2d 413, 425 (CCPA 1981) (emphasis added). And, to the
extent Appellant is asserting that part or all of Baldwin’s 3D graphics
pipeline (e.g., the SD subsystem) must be bodily incorporated or physically
integrated into Duluk’s graphics pipeline processor, we note “the criterion
[is] not whether the references could be physically combined but whether the
claimed inventions are rendered obvious by the teachings of the prior art as a
whole.” In re Etter, 756 F.2d 852, 859 (Fed. Cir. 1985). Nor does
Appellant present any persuasive evidence to support its conclusory
assertion that the Examiner has engaged in impermissible hindsight. See
Reply Br. 6.
In response to Appellant’s arguments about the purported deficiencies
of additionally cited disclosures of Baldwin, including its SD subsystem’s

portion . . . not intersected”;, id. at 6 (“Baldwin does not disclose that (i) a
set of graphics primitives is received, (ii) a determination is made that the set
of graphics primitives overlaps a first portion of a tile, but not a second
portion of the tile, and (iii) data for the first portion, but not the second
portion, is fetched to the SD Cache”).
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operations and fragment operations,3 the Examiner does not rely specifically
on these features to show the obviousness of claim 1. See, e.g., Ans. 7 (“The
Examiner previously cited this portion [about cache misses] to provide
additional context as to how the graphics subsystem of Baldwin works.
However, the Examiner believes that the arguments above are sufficient to
show the obviousness of the disputed limitations, therefore the Examiner
believes the relevancy of this additional citation is moot.”), see also id.
(“[T]he Examiner does not rely on whether operations on fragments are
inherently operations on graphics primitives in order to show the
obviousness of the disputed limitations.”). Rather, the Examiner relies on
Baldwin for the suggested concepts of processing a set of primitives that
overlaps only a portion of a tile,4 and a cache unit fetching data for only that

3 See, e.g., Appeal Br. 12–14 (disputing Advisory Action’s additional
citations of Baldwin’s fragment operations); Reply Br. 6 (“Baldwin fails to
disclose determining . . . a first portion of a tile (e.g., one or more subtiles
included in a tile) . . . intersected by a set of graphics primitives and then
fetching data to the SD cache only for that . . . portion . . . without fetching
data for a second portion of the tile (e.g., one or more different subtiles
included in the tile) . . . not intersected.”), id. at 5 (“Baldwin does not
disclose that the SD Subsystem processes plane equations to determine
intersections between a particular set of graphics primitives and the subtiles
included in a particular tile.”), id. at 6 (“Baldwin does not disclose that the
SD Subsystem processes Sub Tile messages to determine intersections
between a particular set of graphics primitives and the subtiles included in a
particular tile” because “in Baldwin, individual subtiles are processed by the
SD Subsystem without any regard to other subtiles that are overlapped by a
particular set of graphics primitives.”).
4 See, e.g., Baldwin 13:24–37 (“Once the edges of the primitive and a start
tile are known, the rasterizer seeks out screen-aligned super tiles (32x32
pixels) which are inside the edges or intersect the edges of the primitive. . . .
Super tiles that pass this stage are further divided into 8x8 tiles for finer
testing. Tiles that pass this second stage will be either totally inside or
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portion of the cache tile.5 See Final Act. 4; Advisory Act. 1–2; Ans. 3–6.
and (“tiles are updated on a sub tile granularity”). Contrary to Appellant’s
arguments, “[t]he obviousness analysis cannot be confined by a formalistic
conception of the words teaching, suggestion, and motivation, or by
overemphasis on the importance of published articles and the explicit
content of issued patents.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 419
(2007) (emphasis added).
Nor do Appellant’s arguments include any persuasive evidence that
the proposed combination would have been uniquely challenging or
anything more than a routine exercise of combining familiar elements
according to known methods or applying known techniques to achieve
predictable results. See KSR, 550 U.S. at 416–17 (explaining as examples of
combinations likely to be obvious “[t]he combination of familiar elements
according to known methods . . . when it does no more than yield predictable
results” and “the mere application of a known technique to a piece of prior
art ready for the improvement”); Leapfrog Enters., Inc. v. Fisher-Price, Inc.,
485 F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, 550 U.S. at 418). Like
Appellant’s invention, both Duluk and Baldwin employ the known
technique of using a tile-based architecture that divides a screen into smaller
portions (i.e., tiles, or portions thereof) for processing primitives of a three-

partially inside the primitive. Partial tiles are further tested to determine
which pixels in the tile are inside the primitive, and a tile mask is built up . .
The output of the rasterizer is the Tile message which controls the rest of the
core.”), 19:18–20 (“in response to a SubTile message, will generate a
tile/sub tile addresses and pass this to SD cache”), 19:40–41 (“coordinate
information for the primitive (that the sub tile belongs to)”).
5 See, e.g., Baldwin 19:27–30 (“The super tile may be partially populated
with tiles, and the tiles are updated on a sub tile granularity”).
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dimensional scene of objects into a two-dimensional image of pixels for
display. Appellant has not shown that applying this known technique—such
that the screen is divided further into portions of tiles and primitives
overlapping each of those portions are processed—would not have been
predictable to the skilled artisan. Appellant’s Specification—which
describes only non-limiting examples of dividing a tile into portions,
determining that primitives overlap a portion of a tile, and prefetching data
only for that portion—does not compel a different result. See, e.g., Spec.
¶¶ 75, 110, 112.
For the foregoing reasons, Appellant does not persuade us that the
Office’s burden of proof for obviousness has not been met. Therefore, we
sustain the Examiner’s § 103(a) rejection of independent claims 1, 10, and
19, as well as the § 103(a) rejections of dependent claims 2–4, 8, 9, 11–13,
17, 18, 20, and 22, which Appellant does not argue separately.
CONCLUSION
We affirm the Examiner’s rejection of claims 1–4, 8–13, 17–20, and
22 under pre-AIA 35 U.S.C. § 103(a).
No period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See 37 C.F.R.
§ 41.50(f).

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DECISION SUMMARY

Claims
Rejected
35 U.S.C.
§
Reference(s)
/Basis
Affirmed Reversed
1, 2, 8, 10, 11,
17, 19, 20
103(a) Duluk, Baldwin 1, 2, 8, 10,
11, 17, 19, 20

3, 4, 9, 12, 13,
18, 22
103(a) Duluk,
Baldwin,
Heeschen
3, 4, 9, 12,
13, 18, 22

Overall
Outcome
1–4, 8–13,
17–20, 22

AFFIRMED