Naoki MATSUNAGA

Patent Trials and Appeals Board

Jul 22, 2020

2019006722 (P.T.A.B. Jul. 22, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/366,617 12/01/2016 Naoki MATSUNAGA TAI/0180USR 9627
103314 7590 07/22/2020
Kim & Stewart LLP - Toshiba America, Inc.
1910 Pacific Ave. Suite 11500
Dallas, TX 75201
EXAMINER
LEE, CHRISTOPHER E
ART UNIT PAPER NUMBER
3992
NOTIFICATION DATE DELIVERY MODE
07/22/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@kimandstewart.com
fkim@kimandstewart.com
jcardenas@kimandstewart.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte NAOKI MATSUNAGA

____________________

Appeal 2019-006722
Application 15/366,6171
Patent 9,355,685 B2
Technology Center 3900
___________________

Before ALLEN R. MacDONALD, JOHN A. JEFFERY, and
JENNIFER L. McKEOWN, Administrative Patent Judges.

MacDONALD, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from a Final
Rejection of claims 1 and 3–27. Claim 2 has been cancelled. Appeal Br.
16–21. We have jurisdiction under 35 U.S.C. § 6(b). We affirm in part.

1 Filed December 1, 2016, seeking to reissue U.S. Patent 9,355,685 B2,
issued May 31, 2016, based on Application 14/590,626, filed January 6,
2015 as a continuation of 13/773,305, filed on Feb. 21, 2013, now U.S.
Patent 8,929,117 issued January 6, 2015.
2 Appellant identifies the real party in interest is Toshiba Memory
Corporation. Appeal Br. 3.
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Patent 9,355,685 B2

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CLAIMED SUBJECT MATTER
Reissue claims 1, 3, and 20 on appeal are illustrative of the claimed
subject matter (emphasis, formatting, and bracketed material added):
Claim 1. A memory system comprising:
[A.] a first memory chip in a multi-chip package;
[B.] a second memory chip in the multi-chip package;
[C.] a first internal wiring within the multi-chip package
and that couples the first memory chip to a first terminal on the
multi-chip package through which a first chip-enable signal is
received; and
[D.] a second internal wiring within the multi-chip
package and that couples the second memory chip to a second
terminal on the multi-chip package through which a second
chip-enable signal is received,
[E.] wherein the first memory chip comprises[:]
[i.] a chip address memory region configured to store
an initial address for the first memory chip,
[ii.] an initial value-setting module configured to set
the initial address in the chip address memory
region, and
[iii.] a rewrite module configured to write a different
address from the initial address into the chip
address memory region based on an external
operation addressed to the initial address.
Claim 3. The memory system according to claim 1,
wherein the first memory chip includes address-setting pins and
the initial value-setting module is configured to set the initial
state of the address based on voltages applied to the address-
setting pins.
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Claim 20. A semiconductor memory device, comprising:
[A.] a first external terminal for receiving a chip enable
signal;
[B.] a second external terminal for receiving the chip
enable signal;
[C.] a plurality of third external terminals for receiving a
command;
[D.] a first semiconductor chip including a first nonvolatile
memory cell array and a first control circuit, the first nonvolatile
memory cell array including a plurality of first memory cells, the
first control circuit being connectable to the first external
terminal;
[E.] a second semiconductor chip including a second
nonvolatile memory cell array and a second control circuit, the
second nonvolatile memory cell array including a plurality of
second memory cells, the second control circuit being
connectable to the second external terminal;
[F.] a substrate having a first surface on which the first and
second semiconductor chips are provided and a second surface
on which, the first, second, and third external terminals are
arranged; and
[G.] a resin material covering the first and second
semiconductor chips,
[H.] wherein the first control circuit is configured to
perform a function corresponding to the command received
through the plurality of third external terminals if
[i.] the chip enable signal is asserted and
[ii.] an address associated with the command matches
first information stored in the first semiconductor
chip, the first information distinguishing the first
semiconductor chip from the second
semiconductor chip.

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Application 15/366,617
Patent 9,355,685 B2

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REFERENCES3
The Examiner relies on the following references:
Name Reference Date
Lo US 6,055,594 Apr. 25, 2000
Tu US 7,477,545 B2 Jan. 13, 2009
Fujita US 7,486,569 B2 Feb. 3, 2009
Okumura US 7,880,312 B2 Feb. 1, 2011

REJECTIONS
A. Section 112, First Paragraph
The Examiner rejects claims 24–27 under 35 U.S.C. 112, first
paragraph, as failing to comply with the written description requirement.
Final Act. 4–5.
We select claim 24 as representative. Appellant does not argue
separate patentability for remaining claims 25–27. Appeal Br. 10–11.
Except for our ultimate decision, we do not address the merits of the § 112,
first paragraph, rejection of claims 25–27 further herein.
A portion of the § 112, first paragraph, rejection of claim 24 is
analogous to a now withdrawn (Ans. 3, 6) rejection of claim 11 under 35
U.S.C. § 112, first paragraph. To the extent that these rejections of claims
11 and 24 are analogous, we treat the analogous portion of the rejection of
claim 24 under 35 U.S.C. § 112, first paragraph, as also being withdrawn.

3 All citations herein to patent and pre-grant publication references are by
reference to the first named inventor only.
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B. Section 112, Second Paragraph
The Examiner rejects claims 3, 4, 11–19, 22, and 23 under 35 U.S.C.
112, second paragraph, as being indefinite. Final Act. 5–6.
We select claims 3 and 11 as representative. Appellant does not argue
separate patentability for remaining claims 4 and 12–19. Appeal Br. 5–8.
We do not find where the Appeal Brief presents arguments for the
§ 112, second paragraph, rejection of claims 22 and 23. Therefore, we
affirm pro forma the Examiner’s § 112, second paragraph, rejection of
claims 22 and 23.
Except for our ultimate decision, we do not address the merits of the
§ 112, second paragraph, rejection of claims 4, 12–19, 22, and 23
further herein.
C. Section 251 – New Matter
The Examiner rejects claims 24–27 under 35 U.S.C. § 251 as being
based on new matter. Final Act. 6.4
We select claim 24 as representative. Appellant does not argue
separate patentability for remaining claims 25–27. Appeal Br. 12. Except
for our ultimate decision, we do not address the merits of the § 251 rejection
of claims 25–27 further herein.

4 The rejection of claims 11–19 under 35 U.S.C. § 251 as being based on
new matter has been withdrawn. Ans. 3, 11 n.3.
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D. Section 103(a)
D.1.
The Examiner rejects claims 1, 3–6, and 8–10, under 35 U.S.C.
§ 103(a) as being unpatentable over the combination of Fujita and Tu.
Final Act. 6–11.
Appellant does not present separate arguments for claims 3–6 and 8–
10. We select claim 1 as the representative claim for this rejection. Except
for our ultimate decision, we do not address the merits of the § 103(a)
rejection of claims 3–6 and 8–10 further herein.5
D.2.
The Examiner rejects claim 7 under 35 U.S.C. § 103(a) as being
unpatentable over the combinations of Fujita, Tu, and Lo. Final Act. 11–12.
Appellant does not present separate arguments for claim 7. Appeal
Br. 13. Thus, the rejection of this claim turns on our decisions as to claim 1.
Except for our ultimate decision, we do not address the merits of the
§ 103(a) rejection of claim 7 further herein.
D.3.
The Examiner rejects claims 20–23 under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Fujita, Tu, and Okumura. Final Act.
12–15.

5 Claim 10 was modified on July 9, 2018 to change “written” to –rewritten–
without indicating (on that date or subsequently) as required by 37 CFR
§ 1.173(d)(2) that the change was an intended amendment. For purposes of
this appeal, we treat this change as though it was a proper amendment.
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Appellant does not present separate arguments for claims 21–23.
Appeal Br. 14. We select claim 20 as the representative claim for this
rejection. Except for our ultimate decision, we do not address the merits of
the § 103(a) rejection of claims 21–23 further herein.
OPINION
We have reviewed the Examiner’s rejections in light of Appellant’s
Appeal Brief and Reply Brief arguments that the Examiner has erred.
A. Section 112, First Paragraph
The Examiner rejects claim 24 under 35 U.S.C. § 112, first paragraph,
as failing to comply with the written description requirement. Final Act. 4–
5. Again, we note the Examiner has withdrawn a similar rejection of claim
11. Ans. 3, 6. In part the Examiner states:
The invention of the claim 24 includes the particular elements
“board-side terminals on the circuit board” and the particularly
connecting structure “a plurality of signal lines on the circuit
board connecting the controller to said board-side terminals,”
which make the invention of the claim 11 be different from the
invention of the claim 24.
Ans. 6. The Examiner further determines:
[T]he Appellant alleges that the written description
requirement is met with regard to claim 24 because Fig. 8 shows
that the claimed subject matter “a plurality of external terminals”
could be mapped to a plurality of solder balls, and the
specification describes (i) the claimed subject matter “a plurality
of board-side terminals” at col. 5, lines 50-53 and col. 7, lines 26-
31 and 43-47, and (ii) the claimed subject matter “a plurality of
signal lines” at col. 3, lines 3-5 (See the Appeal Brief, page 11,
lines 3-16).
. . . .
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Based on the Appellant’s allegation, the Examiner finds
the fact of disclosing a multi-chip package 10 (i.e., memory
package) that includes multiple memory chips 11a to 11d (i.e.,
multiple memory chips) having bonding wires 55 (i.e., a plurality
of internal wirings) between each of solder balls 56 (i.e., a
plurality of external terminals) in Fig. 7. And, the Figs. 8-9
further implicitly disclose that said solder balls I/Oo-o through
I/O7-0, I/O0-1 through I/O7-1, CE 0/1, and ALE-0/1 may be
correspondingly connected to a plurality of pins I/O 0 to I/O 7, a
pin of CE, and a pin of ALE per memory chip (i.e., each first and
second memory chips) via said bonding wires (i.e., via said
plurality of internal wirings).
Nevertheless, the term “board-side terminal” is not
defined in the specification, thus it would be understood such as
a terminal located at the side of the circuit board by one of
ordinary skill in the art. And, the specification does not disclose
that (i) the plurality of board-side terminals on the circuit board
include the first, second, third, and fourth terminals; (ii) the
plurality of signal lines on the circuit board connect the controller
to the plurality of board-side terminals; (iii) the plurality of
signal lines include the first, second, third, and fourth signal lines
electrically connected to their corresponding first, second, third,
and fourth terminals. Furthermore, the specification is silent
upon (i) how those signal lines are connecting the controller to
the plurality of board-side terminals, and further (ii) how those
signal lines are electrically connected to the first, second, third,
and fourth terminals of the plurality of board-side terminals.
Accordingly, the plurality of board-side terminals and
their combination with other elements claimed in the claim 24
are not supported by the specification of the patent sought to be
reissued.
Ans. 7–8 (emphasis added).
Appellant argues:
With regard to “board-side terminals,” Applicant notes
disclosure of ball grid array packages and pin grid array packages
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at col. 5, line 50-53 and description of a device
assembly/manufacture at col. 7, line 26-31 & line 43-47.
With regard to “a plurality of signal lines” Applicant notes
description at col. 3, line 3-5 (“the connection wiring of each
channel contains the 1/0 signal line, the control signal line, and
the R/B signal line.”).
Appeal Br. 11.
Our review determines that to the extent the Examiner requires
“board-side terminals on the circuit board,” this is disclosed at column 5,
lines 36–53 and Figures 6–7 of the Specification.
On the substrate 51, multiple terminals (bonding pads) 52
are arranged. The pins disposed in the memory chips 11a to 11d
are electrically connected to the terminals 52 on the substrate 51
via the bonding wires 55. The multiple memory chips 11a to 11d
and the bonding wires 55 laminated onto the substrate 51 are
sealed off by the molding resin 57. Also, solder balls 56 are
arranged on the lower surface of the substrate 51. The solder balls
56 are electrically connected to the terminals 52. The NAND
memory 1, for example, is soldered and assembled together with
the transfer controller 2 and the RAM 3 on a printed circuit board
equipped in the SSD 100. The various types of signals from the
transfer controller 2 are input via the solder balls 56, the
terminals 52, and the bonding wires 55 to the pins equipped in
the memory chips 11a to 11d.
Spec. col. 5:36–49.
The essence of Appellant’s argument is that an artisan would
understand the solder balls 56 to be claimed board-side terminals. We agree.
Therefore, based on our review, we determine the Examiner’s analysis fails
to demonstrate that claim 24 lacks written description support.
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B. Section 112, Second Paragraph
B.1. Claim 3
The Examiner rejects claim 3 under 35 U.S.C. § 112, second
paragraph, as being indefinite.
Claim 3 recites the limitation “the initial state” in line 3.
There is insufficient antecedent basis for this limitation in the
claim.
Furthermore, it recites the limitation “the address” in line
3. However, its prior claim 1 recites “an initial address” in line
11 and “a different address” in line 13. Thus, the limitation “the
address” does not sufficiently point out its antecedent basis,
which could be one of “initial address” and “different address”.
The Examiner presumes that the terms “the initial state”
and “the address” could be considered as --an initial state-- and
--the initial state-- in light of the specification, respectively, for
the purpose of the claim rejection.
Final Act. 5 (emphasis added).
In response to the rejection, Appellant merely asserts:
Since the scope of claim 3 is reasonably ascertainable by those
skilled in the art, claim 3 is not indefinite because there is no
confusion with regard the meaning of “the initial state of the
address” in this context[.]
Appeal Br. 11.
We are unpersuaded by Appellant’s assertion. Claim 1 of the patent
for which reissue is being sought contained only a single “an address.”
Therefore, the antecedent basis of “the address” of patent claim 3 was
clearly the single “an address” of claim 1. However, during prosecution of
Appellant’s reissue application, claim 1 on appeal has been amended to
recite two separate “an initial address” and “a different address.”
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We agree with the Examiner that there is now ambiguity as to the
antecedent basis of “set the initial state of the address” recited in claim 3.
We suggest that more appropriate language might be “set the initial
address.”
B.2. Claim 11
The Examiner rejects claim 11 under 35 U.S.C. § 112, second
paragraph, as being indefinite.
Claim 11 recites the limitation “the chip enable signal” in
lines 20 and 30. However, it recites “a chip enable signal” in lines
14, 28, and 37. Thus, the limitation “the chip enable signal”
recited in line 30 does not sufficiently point out its antecedent
basis, and furthermore, the three different subject matters “a chip
enable signal” separately recited in lines 14, 28, and 37 are not
clearly defined in the claim, e.g., what are the differences among
the three different subject matters “a chip enable signal”.
Final Act. 5–6 (emphasis added).
In response to the rejection, Appellant merely asserts:
Read in the context of claim 11 as a whole, each instance of “a
chip enable signal” and “the chip enable signal” is appropriate
and more importantly the scope of claim 11 is reasonably
ascertainable by those skilled in the art and thus not indefinite.
Appeal Br. 12.
We agree with Appellant that read in the context of claim 11, each
instance of “a chip enable signal” (lines 14, 28, and 37) and the first instance
of “the chip enable signal” (line 20) are appropriate. However, we agree
with the Examiner that “the chip enable signal” limitation recited in line 30
does not sufficiently point out whether its antecedent basis is the first recited
“a chip enable signal” (line 14) or the second recited “a chip enable signal”
(line 28).
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Therefore, based on our review, we determine the Examiner’s analysis
demonstrates that claim 11 is indefinite.
C. Section 251 – New Matter
As to claim 24, Appellant argues the § 251 new matter rejection by
reference to the arguments as to the § 112, first paragraph, written
description rejection.
This rejection is [] derivative of the rejection of these same
claims for failure or the written description requirement under 35
U.S.C. § 112. Applicant reiterates here the arguments provided
above regarding these claims with respect to the written
description rejection. As each of these claims is fully supported
by the original patent specification (as discussed above), they are
not new matter for purposes of reissue.
Appeal Br. 12.
As discussed above, we are persuaded by Appellant’s § 112, first
paragraph, arguments. Therefore, we are persuaded by Appellant’s
arguments as to the § 251 new matter rejection for the same reasons.
D. Section 103(a)
D.1.
Appellant raises the following argument in contending that the
Examiner erred in rejecting claim 1 under 35 U.S.C. § 103(a).
The reprogramming operations/actions in Tu are not
addressed to an already stored (initial) address, but rather operate
only by overriding/ignoring any previously stored/set address.
Therefore, Tu must fail to teach or suggest chip address changes
by “a rewrite module configured to write a different address from
the initial address into the chip address memory region based on
an external operation addressed to the initial address.”
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Appeal Br. 13.
The Examiner responds by determining:
Tu teaches that rewriting the initial address of a memory chip
(i.e., replacing or reprogramming the predetermined unique
address of the non-defective memory die) is based on an external
operation (i.e., based on a package testing) addressed to said
initial address of memory chip (i.e., addressed to said
predetermined unique address of memory die; See Tu, Steps 312-
324 in Fig. 4 and col. 7, line 46 through col. 8, line 25; in fact,
the package level testing performs bit and word line tests,
memory cell tests for reading, writing, and data retention, etc. on
the memory dies being addressed by their predetermined unique
addresses).
Ans. 15 (emphasis added).
E.
As articulated by the Federal Circuit, the Examiner’s burden of
proving non-patentability is by a preponderance of the evidence. See In re
Caveney, 761 F.2d 671, 674 (Fed. Cir. 1985) (“preponderance of the
evidence is the standard that must be met by the PTO in making rejections”).
“A rejection based on section 103 clearly must rest on a factual basis[.]” In
re Warner, 379 F.2d 1011, 1017 (CCPA 1967). “The Patent Office has the
initial duty of supplying the factual basis for its rejection. It may not . . .
resort to speculation, unfounded assumptions or hindsight reconstruction to
supply deficiencies in its factual basis.” Id. We conclude the Examiner’s
analysis fails to meet this standard because the rejection does not adequately
explain the Examiner’s findings of fact.
Particularly, we agree with Appellant that the language of claim 1
requires “a rewrite module configured to write a different address from the
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initial address into the chip address memory region based on an external
operation addressed to the initial address,” and we disagree with the
Examiner’s reasoning that Tu without more is sufficient to show the argued
claim limitation. We conclude, consistent with Appellant’s arguments, that
there is insufficient articulated reasoning to support the Examiner’s finding
that Tu discloses the argued claim limitation.
Therefore, we conclude that there is insufficient articulated reasoning
to support the Examiner’s final conclusion that claim 1 would have been
obvious to one of ordinary skill in the art at the time of Appellant’s
invention.
D.2.
Also, Appellant raises the following argument in contending that the
Examiner erred in rejecting claim 20 under 35 U.S.C. § 103(a).
[B]ecause Fujita already has separate/isolatable chip enable
(CE) terminals for its different chips (see Fujita, Fig. 2-3,
terminals CE0 and CE1), these chips are already separately
addressable by a controller, independent of any internal chip
address, and thus there is no need to reprogram the internal chip
addresses in Fujita because communications between the outside
controller and said chips is based on the internal functions of the
disclosed controller (2) without particular reference to any
internal chip address.
Tu specifically incorporates means of reprogramming an
internal address (post-packaging) because the various disclosed
chips must rely on a common CE terminal/signal (See Tu, col. 4,
line 67 to col. 5, line 2; “Control line 122 is a master chip enable
line. Each memory device is generally enabled in response to a
master chip enable signal provided by controller 110.”)
However, when a common CE is not being utilized, there is no
particular need for distinct internal chip addresses in the device
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of Tu. Consequently, there is no motivation to modify Fujita to
incorporate reprogramming of an internal chip address, whether
or not such reprogramming provides “a continuous range” of
internal chip addresses since the setting of such an internal
address is irrelevant because the controller resulting from the
combination would not need to distinguish different chips by use
of preset internal addresses because such a controller would
enable/disable each chip according to supply (or not) of a
dedicated chip enable signal via the distinct chip CE terminals.
Okumura does nothing to cure this deficiency.
Accordingly, this obviousness rejection is based on clearly
erroneous hindsight bias.
Appeal Br. 14 (emphasis added).
We are unpersuaded by Appellant’s arguments. We conclude the
combination of Fujita’s semiconductor memory device and Tu’s
programmable chip enable and chip address in a memory system is the mere
substitution of one chip enable process (Tu’s) for another existing chip
enable process (Fujita’s) without any change in the resulting enabling of the
chip, i.e., yielding predictable results.
[W]hen a patent claims a structure already known in the prior art
that is altered by the mere substitution of one element for another
known in the field, the combination must do more than yield a
predictable result.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In support of the rejection, the Examiner sets forth a clear articulated
reasoning at pages 12–15 of the Final Action. Appellant cites no case law to
support the position that a more complex articulated reasoning is required.
Rather, as set forth by the Court in KSR, in some circumstances (e.g., mere
substitution) the required analysis is minimal, while in complex
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circumstances “this analysis should be made explicit.” KSR, 550 U.S. at
418. As the situation before us is one of mere substitution rendering nothing
more than predictable results, we conclude the Examiner’s analysis is
sufficient for the simple circumstances before us. We find the Examiner’s
conclusion (and analysis) well founded.
Further, Appellant has not presented evidence sufficient to show that
combining the prior art was “uniquely challenging or difficult for one of
ordinary skill in the art” or “represented an unobvious step over the prior
art.” Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed.
Cir. 2007) (citing KSR, 550 U.S. at 418–19).
CONCLUSIONS
The Appellant has demonstrated the Examiner erred in rejecting
claims 24–27 under 35 U.S.C. § 112, first paragraph, as failing to comply
with the written description requirement.
The Appellant has demonstrated the Examiner erred in rejecting
claims 24–27 under 35 U.S.C. § 251 as being based on new matter.
The Appellant has demonstrated the Examiner erred in rejecting
claims 1 and 3–10 as being unpatentable under 35 U.S.C. § 103(a).
The Examiner has not erred in rejecting claims 3, 4, 11–19, 22, and 23
under 35 U.S.C. § 112, second paragraph, as being indefinite.
The Examiner has not erred in rejecting claims 20–23 as being
unpatentable under 35 U.S.C. § 103(a).
The Examiner’s rejections of claims 24–27 under 35 U.S.C. § 112,
first paragraph, as lacking written description is reversed.
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The Examiner’s rejection of claims 24–27 under 35 U.S.C. § 251 as
being based on new matter is reversed.
The Examiner’s rejections of claims 1 and 3–10 as being unpatentable
under 35 U.S.C. § 103(a) are reversed.
The Examiner’s rejection of claims 3, 4, 11–19, 22, and 23 under
35 U.S.C. § 112, second paragraph, as being indefinite is affirmed.
The Examiner’s rejection of claims 20–23 as being unpatentable
under 35 U.S.C. § 103(a) is affirmed.
DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
24–27 112, 1st ¶ Written Description 24–27
3, 4, 11–19,
22, 23
112, 2nd ¶ Indefiniteness 3, 4, 11–19,
22, 23

24–27 251 New Matter 24–27
1, 3–6, 8–10 103(a) Fujita, Tu 1, 3–6, 8–10
7 103(a) Fujita, Tu, Lo 7
20–23 103(a) Fujita, Tu, Okumura 20–23
Overall
Outcome

3, 4, 11–23 1, 5–10, 24–
27

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED IN PART