MLC INTELLECTUAL PROPERTY, LLC (PATENT OWNER) et al.

Patent Trials and Appeals Board

Nov 30, 2021

2021005426 (P.T.A.B. Nov. 30, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
90/014,421 12/20/2019 5764571 1063
37086 7590 11/30/2021
POLSINELLI PC
(NDQ REEXAMINATION GROUP)
PO Box 140310
Kansas City, MO 64114-0310
EXAMINER
LEE, CHRISTOPHER E
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
11/30/2021 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte MLC INTELLECTUAL PROPERTY, LLC
Patent Owner and Appellant
____________

Appeal 2021-005426
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Patent 5,764,571
Technology Center 3900
____________

Before ALLEN R. MacDONALD, JOHN A. JEFFERY, and
KEVIN F. TURNER, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. §§ 134 and 306 the Examiner’s
decision to reject claims 15–17. We have jurisdiction under 35 U.S.C.
§§ 134 and 306.
We AFFIRM and enter a new ground of rejection.

1 Appellant identifies the real party in interest as MLC Intellectual Property,
LLC. Appeal Br. 1.
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STATEMENT OF THE CASE
This proceeding arose from a request for ex parte reexamination filed
on December 20, 2019 of United States Patent 5,764,571 (“the ’571 patent”),
issued to Gerald J. Banks on June 9, 1998.
The ’571 patent describes an electrically-alterable, non-volatile multi-
bit memory cell with predetermined memory states. The cell’s programming
is verified by (1) selecting a reference signal corresponding to information to
be stored, and (2) comparing a cell signal with the selected reference signal.
See Abstract. Claim 15 is illustrative of the invention and is reproduced
below:
15. Multi-level memory apparatus, comprising:

an electrically alterable non-volatile memory cell having
more than two predetermined memory states;

a selecting device which selects one of a plurality of
reference signals in accordance with information indicating a
memory state to which said memory cell is to be programmed,
each reference signal corresponding to a different memory state
of said memory cell;

a programming signal source which applies a
programming signal to said memory cell; and

a control device which controls the application of said
programming signal to said memory cell based on the selected
reference signal.

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RELATED PROCEEDINGS
This appeal is related to various proceedings. First, Appellant informs
us of related copending litigation, namely MLC Intellectual Property, LLC v.
Micron Technology, Inc., No. 3:14-cv-03657 (N.D. Cal. Aug. 12, 2014).
Appeal Br. 2.2
Appellant also informs us that the ’571 patent was the subject of two
inter partes review (IPR) proceedings, IPR2015-00504 and IPR2015-00517,
where the Board denied institution in both proceedings. Appeal Br. 2.
Appellant adds that the ’571 patent is also the subject of two ex parte
reexamination proceedings, control numbers 90/020,112 and 90/014,245,
where the former confirmed the claims’ patentability over the combination
of Kitamura (cited in full below) and Connolly, the latter reference not at
issue here. See id. In an appeal in connection with the ’245 reexamination,
we affirmed the Examiner’s decision to reject claims 1, 9, 12, 30, 42, and 45
of the ’571 patent as obvious under 35 U.S.C. § 103 over the same prior art
references at issue here, namely Kitamura and Noguchi. See Ex parte MLC
Intellectual Property, LLC, Appeal 2020-005915 (PTAB Nov. 2, 2020),
reh’g granted (PTAB Mar. 1, 2021), reh’g denied (PTAB Nov. 2, 2021).3

2 Throughout this opinion, we refer to (1) the Final Rejection mailed August
21, 2020 (“Final Act.”); (2) the Appeal Brief filed February 17, 2021
(“Appeal Br.”); (3) the Examiner’s Answer mailed July 14, 2021 (“Ans.”);
and (4) the Reply Brief filed September 14, 2021 (“Reply Br.”).
3 For citation purposes, we refer to our November 2020 decision as “Nov.
2020 Dec.” We also refer to our March 2021 and November 2021 decisions
on rehearing as “Mar. 2021 Reh’g Dec.” and “Nov. 2021 Reh’g Dec.”
respectively.
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In our March 2021 decision, we granted Appellant’s request to rehear
our November 2020 decision only to the extent that we (1) designated our
affirmance of the Examiner’s decision to reject the claims as obvious over
Kitamura and Noguchi as a new ground of rejection; (2) entered a
Supplemental Declaration from Dr. Jack Lee submitted with Appellant’s
first rehearing request; and (3) modified our decision solely to address
Appellant’s newly-raised arguments based on that newly-submitted
declaration. All other aspects of our November 2020 decision, however,
remained the same and were incorporated by reference in the March 2021
decision. See Mar. 2021 Reh’g Dec. 2. After our March 2021 decision,
Appellant filed another rehearing request that we denied on November 2,
2021. Our November 2021 decision likewise incorporated our November
2020 decision by reference except for those portions modified in our March
2021 decision. See Nov. 2021 Reh’g Dec. 2.

THE REJECTION
The Examiner rejected claims 15–17 under 35 U.S.C. § 103 as
unpatentable over Kitamura (JP62-34398 A; published Feb. 14, 1987) and
Noguchi (US 5,262,984; issued Nov. 16, 1993). Final Act. 7–9.

CONTENTIONS, FINDINGS, AND CONCLUSIONS
Regarding independent claim 15, the Examiner finds that Kitamura’s
multi-level memory device includes, among other things, a converting
device for generating one of plural reference signals, namely threshold
voltages VT, according to input information, namely digital signals B1 and
B2. Final Act. 7–8. Although the Examiner acknowledges that Kitamura’s
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converting device does not select a reference signal according to the recited
information, the Examiner cites Noguchi for teaching this feature in
concluding that the claim would have been obvious. Final Act. 8.
According to the Examiner, substituting Noguchi’s input data changeover
circuit 40 and constant voltage changeover circuit 44 in Figure 12, which the
Examiner maps collectively to the recited selecting device, for Noguchi’s
digital-to-analog (D/A) conversion circuit 10 in Figure 1 would have been a
simple substitution to obtain predictable results. Id. This substitution is said
to provide more versatility than Kitamura’s D/A converting device by
enabling analog output voltage levels to be set independently to best suit the
memory cell’s characteristics. Id.
Appellant argues that the Examiner not only contradicts the Board’s
earlier determinations, the Examiner’s proposed replacement of Kitamura’s
D/A converter with Noguchi’s multiplexer is based solely on impermissible
hindsight, and there is no reason to combine the references as the Examiner
proposes. Appeal Br. 9–32; Reply Br. 10–14. Appellant adds that the
Examiner’s proposed substitution not only changes Kitamura’s principle of
operation from two-way uniform conversion to non-uniform selection and
conversion, the proposed substitution renders Kitamura inoperable for its
intended purpose by, among other things, eliminating shared circuitry
needed to maintain the operating margin between verification and reading.
Appeal Br. 24–32; Reply Br. 3–9.
Appellant adds that our decision in the ’245 reexamination is
inapplicable to the present appeal because the Examiner does not propose to
share four reference voltage supply circuits under the proposed combination
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or cite Dr. Liu’s testimony as did the Board in the ’245 reexamination
proceeding. Appeal Br. 8–9. Rather, the Examiner’s rejection is said to be
premised on sharing only a single voltage supply to preserve uniformity—
not four reference voltage supplies. Id.
Because claims 16 and 17 are not argued separately with particularity
(see generally Appeal Br.; Reply Br.), we determine this appeal on the basis
of claim 15.

ISSUE
Under § 103, has the Examiner erred in rejecting claim 15 by finding
that Kitamura and Noguchi collectively would have taught or suggested a
multi-level memory apparatus with a selecting device for selecting one of
plural reference signals in accordance with information indicating a memory
state to which a memory cell is to be programmed? This issue turns on
whether substituting Noguchi’s input data changeover circuit and constant
voltage changeover circuit for Kitamura’s D/A conversion circuit as the
Examiner proposes renders Kitamura unsuitable for its intended purpose.

ANALYSIS
We begin by noting that because the ’571 patent expired, we construe
the claims under the standard set forth in Phillips v. AWH Corp., 415 F.3d
1303 (Fed. Cir. 2005) (en banc). See In re Rambus, Inc., 753 F.3d 1253,
1256 (Fed. Cir. 2014).
Under the Phillips standard, claim terms are generally given their
ordinary and customary meaning, namely the meaning the term would have
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to an ordinarily skilled artisan at the time of the invention. Phillips, 415
F.3d at 1312. In construing the claim, we begin with the intrinsic evidence
of record, namely the claim language, the patent specification, and, if in
evidence, the prosecution history. See id. at 1313.
Here, this appeal does not turn on claim construction. Rather, as
noted previously, this appeal turns on the cited references’ combinability.
We, therefore, confine our discussion to that issue.
Turning to the rejection, the Examiner acknowledges that Kitamura
does not disclose the recited selecting device for selecting one of plural
reference signals, but rather discloses a converting device that generates one
of plural reference signals, namely D/A conversion circuit 10 in Figure 1.
See Final Act. 7–8. The Examiner, however, concludes that substituting
Noguchi’s input data changeover circuit 40 and constant voltage changeover
circuit 44 in Figure 12, which the Examiner maps collectively to the recited
selecting device, for Noguchi’s D/A conversion circuit, would have been a
simple substitution to obtain predictable results. Id. at 8.
On this record, we see no error in the Examiner’s proposed
combination. First, the Examiner’s findings and conclusions do not conflict
with those of the Board in the related IPR proceedings, despite Appellant’s
arguments to the contrary. See Appeal Br. 11–13.
As the Examiner indicates (Ans. 6–8, 13–14), the Board did not
consider the Kitamura/Noguchi combination at issue here, but rather
considered whether the Petitioner was reasonably likely to prevail in
showing that at least one of the challenged claims was unpatentable as
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obvious over either the Kitamura or Mehrotra4 references, the latter not at
issue here. See Micron Tech., Inc. v. MLC Intellectual Property, LLC,
IPR2015-00517, Paper 9 at 3–15 (PTAB July 20, 2015) (“IPR Dec.”).
Although the Board concluded that the Petitioner was not reasonably likely
to prevail in showing that the claimed invention would have been obvious
based on Kitamura (or Mehrotra) alone, Noguchi was simply not at issue in
the IPR proceeding, let alone the proposed Kitamura/Noguchi combination
at issue here. Accord Declaration of David Kuan-Yu Liu, dated Dec. 20,
2019 (“Liu Decl.”) ¶ 59 (noting that the obviousness grounds in the IPR
petitions each involved obviousness over a single reference). Appellant’s
contention, then, that the Board ostensibly already considered and rejected
the argument that Kitamura and Noguchi allegedly perform the same
function (Appeal Br. 27–28) is, at best, overstated since Noguchi was not
before the Board in the related IPR proceedings.
In the related IPR proceedings, the Board found that Kitamura does
not disclose the D/A conversion circuit’s specific functioning, let alone
selecting between reference voltages or signals. See IPR Dec. 10. In
reaching its conclusion, the Board noted that a D/A converter’s normal
function is not selecting between reference voltages, but rather rendering
digital input into analog form. Id. The Board added that the Petitions in
those proceedings provided no rationale why Kitamura’s disclosure of D/A
conversion renders selecting a reference voltage or signal obvious. Id.
Our emphasis underscores that the Board’s findings and conclusions
in this regard were based solely on Kitamura—not Kitamura combined with

4 Mehrotra, US 5,172,338, issued Dec. 15, 1992.
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other references, let alone Noguchi, as is the case here. Nevertheless, the
Examiner’s findings regarding Kitamura reasonably comport with those of
the Board in the related IPR proceedings, namely that Kitamura does not
disclose the recited selecting device that selects one of plural reference
signals, but rather discloses a converting device that generates one of plural
reference signals, namely D/A conversion circuit 10 in Figure 1. See Final
Act. 7–8; Ans. 2 (noting that Kitamura discloses every recited element
except for the selecting device).
Notably, the Examiner’s obviousness rejection is not based on
Kitamura alone as in the related IPR proceedings, but rather Kitamura and
Noguchi collectively. Moreover, the Examiner articulates why it would have
been obvious for an ordinarily skilled artisan5 to select reference voltages in
Kitamura in light of Noguchi, namely to provide more versatility to
Kitamura’s D/A conversion circuit by enabling independently setting output
voltages to best suit the memory cell’s characteristics. See Final Act. 8;
Ans. 4–8, 20–22, 42–43. Accord Liu Decl. ¶ 100 (noting that Noguchi’s

5 Both Dr. Lee and Dr. Liu describe the level of ordinary skill in the
pertinent art similarly. See Declaration of Dr. Jack Lee, dated Apr. 26, 2019
(“Lee Decl.”) ¶ 11; see also Liu Decl. ¶ 12. Therefore, we find, as did the
court in a related proceeding, that one of ordinary skill in the art at the time
of the invention would have (1) an undergraduate degree in electrical
engineering (or equivalent subject), along with three to four years of post-
graduate experience designing semiconductor and memory devices, or (2) a
master’s degree in electrical engineering (or equivalent subject) together
with one or two years of post-graduate experience designing semiconductor
and memory devices. Accord MLC Intellectual Property, LLC v. Micron
Technology, Inc., No. 3:14-cv-03657-SI, 2016 WL 6563343), at *2–3 (N.D.
Cal. Nov. 4, 2016) (adopting this skill level).
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approach in Figure 12 would provide more versatility than a typical D/A
converter because Noguchi’s constant voltage circuits independently
generate their respective constant voltages, thus allowing the system
designer to set voltage levels independently for each input bit combination to
best suit memory cell characteristics).6
On this record, we see no error in Examiner’s conclusion. As shown
in Noguchi’s Figure 12, reproduced below, input buffers for binary data D0
and D1 are connected to input data changeover circuit 40 that is connected to
constant voltage changeover circuit 44. See Noguchi, col. 10, ll. 3–58.

6 Although Dr. Liu’s declaration also discusses the Briner reference that is
not at issue here, Dr. Liu’s discussion regarding Kitamura, Noguchi, and
their combinability is nonetheless pertinent to the obviousness rejection
before us.
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Noguchi’s input data and constant voltage changeover circuits in Figure
12

As noted previously, the Examiner maps Noguchi’s input data and
constant voltage changeover circuits 40 and 44 collectively to the recited
selecting device. See Final Act. 8; Ans. 2, 5, 7, 13, 16–17, 30.
We see no error in this mapping. As Dr. Liu explains, Noguchi’s
input data and constant voltage changeover circuits 40 and 44 collectively
perform the same overall function as a 2-bit D/A converter by (1) receiving a
2-bit input (D0 and D1), and (2) outputting one of four constant analog
voltages corresponding to the input by selecting that voltage—functionality
commensurate with that of an analog multiplexer. See Liu Decl. ¶¶ 82–95.
Accord Ans. 18 (referring to Dr. Liu’s testimony in this regard).
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Given Noguchi’s D/A conversion and voltage selection functionality,
we see no error in the Examiner’s conclusion that providing such selection
functionality in addition to D/A conversion under Examiner’s proposed
combination would have been at least an obvious variation yielding a
predictable result. Such an enhancement uses prior art elements predictably
according to their established functions—an obvious improvement. See KSR
Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007).
Appellant’s contention that Noguchi’s constant voltage changeover
circuit is not a D/A converter because the digital input and analog outputs
ostensibly have no relationship is unavailing. See Appeal Br. 12 (citing
Declaration of Jerry Banks Pursuant to 37 C.F.R. § 1.132, dated Nov. 7,
2019 (“Banks Decl.”) ¶ 19). Although we appreciate Mr. Banks’ insights in
this regard, the fact that he is an interested party, namely the inventor, in this
proceeding reduces the probative value of his declaration, at least with
respect to his views regarding patentability of his invention over the cited
prior art. See Ashland Oil, Inc. v. Delta Resins & Refractories, Inc., 776
F.2d 281, 294 (Fed. Cir. 1985) (noting that an expert’s interest in the
outcome of the case is a factor in assessing the probative value of an expert
opinion). Moreover, Mr. Bank’s averments regarding Noguchi’s alleged
lack of a D/A converter are undercut by Dr. Liu’s averments to the contrary.
See Liu Decl. ¶ 85 (noting that Noguchi’s input data and constant voltage
changeover circuits 40 and 44 collectively perform the same overall function
as a 2-bit D/A converter). Therefore, to the extent that Appellant contends
that the proposed combination somehow eliminates D/A conversion, we
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disagree given Noguchi’s D/A conversion and selection functionality noted
above. Accord Ans. 18 (noting this dual functionality).
Nor are we persuaded that combining the teachings of Noguchi with
those of Kitamura as the Examiner proposes would render Kitamura
inoperable or unsuitable for its intended purpose as Appellant contends. See
Appeal Br. 32–38; Reply Br. 5–9. As Dr. Liu explains, Noguchi’s circuits
40 and 44 collectively achieve the same result and conversion function,
namely converting digital input to analog output, as Kitamura’s D/A
conversion circuit 10. Liu Decl. ¶¶ 85, 99. Therefore, using Noguchi’s
circuits 40 and 44 in place of Kitamura’s D/A conversion circuit 10 would
simply use Noguchi’s 4-input analog multiplexer structure to perform in the
same predictable manner that the 4-input multiplexer performs in Noguchi
as Dr. Liu indicates. Id. ¶ 99.
Notably, as Dr. Liu explains in paragraph 102 of his declaration, the
Kitamura/Noguchi combination does not alter Kitamura’s programming
verification and overall memory cell programming technique. With the
proposed combination, Kitamura’s comparator 9 still uses the output of the
modified D/A conversion circuit in the same manner Kitamura discloses.
See Liu Decl. ¶ 102. In short, differences in the way Kitamura uses the
output of D/A conversion circuit 10 and the way Noguchi uses the output of
circuit 44 do not make Noguchi’s conversion technique any less applicable
to Kitamura. Id. Although Kitamura and Noguchi use the outputs of their
conversions differently, ordinarily skilled artisans would nonetheless
recognize the conversions themselves are commensurate, and that Noguchi’s
circuits 40 and 44 could be used to perform Kitamura’s conversion as Dr.
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Liu indicates. See id. ¶¶ 102–104. Such an enhancement uses prior art
elements predictably according to their established functions—an obvious
improvement. See KSR, 550 U.S. at 417. So even assuming, without
deciding, that Noguchi’s constant voltage changeover circuit is not used for
verification as Appellant contends (Appeal Br. 24–26) and Dr. Lee avers in
paragraph 85 of his declaration, the fact that Noguchi’s conversion output is
not used for this particular purpose does not mean that Noguchi’s converter
cannot be used for another purpose, such as that in Kitamura as the
Examiner proposes. Nor has Appellant shown persuasively that the cited
references criticize, discredit, or otherwise discourage the Examiner’s
proposed combination to teach away from that approach. See Norgren Inc.
v. Int’l Trade Comm’n, 699 F.3d 1317, 1326 (Fed. Cir. 2012); see also In re
Kahn, 441 F.3d 977, 990 (Fed. Cir. 2006).
Appellant’s contention that replacing Kitamura’s D/A conversion
circuit 10 with that shown in Noguchi’s Figure 12 would break the
uniformity of characteristics of Kitamura’s D/A and A/D conversion circuits
provided by sharing a voltage dividing element and reference voltage supply
(Appeal Br. 32–33) is unavailing. To be sure, Kitamura’s D/A and A/D
conversion circuits 10 and 13 preferably share a voltage dividing element
and reference voltage supply to make their characteristics uniform.
Kitamura ¶ 11. Our emphasis on the term “preferably” underscores that
sharing these elements to achieve uniformity is merely a preference—not a
requirement—as Dr. Liu indicates. See Liu Decl. ¶ 117. Accord Ans. 25
(noting this preference). Although Kitamura’s particular shared arrangement
may be preferred to achieve uniformity, ordinarily skilled artisans would
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nevertheless infer from Kitamura’s articulation that there may be other ways
to achieve uniformity as the Examiner indicates (Ans. 25)—albeit less
preferred.
For example, Dr. Liu explains that, under the proposed combination,
uniformity between Kitamura’s circuits 10 and 13 can be achieved by
sharing a reference voltage supply, namely by replacing Kitamura’s single
reference voltage supply and voltage dividing element with four separate
reference voltage supply circuits. Liu Decl. ¶ 121. On this record, we see
no reason why these four reference voltage supplies under the proposed
combination could not be shared to achieve uniformity as Dr. Liu indicates.
See id. Sharing these voltage supplies to achieve uniformity is not only
reasonably consistent with Kitamura’s teachings, there is no persuasive
evidence on this record to rebut this finding.
We reach this conclusion despite Dr. Lee’s view that replacing
Kitamura’s D/A conversion circuit 10 with Noguchi’s Figure 12 would
break uniformity, and that the proposed combination would likely render
Kitamura inoperable for its intended purpose. See Lee Decl. ¶ 84. Leaving
aside Dr. Lee’s speculative term “likely” in connection with Kitamura’s
alleged inoperability under the proposed combination, Dr. Lee’s averments
are undercut by those of Dr. Liu as noted above.
To the extent that Appellant contends that using shared voltage
supplies under the Kitamura/Noguchi combination as Dr. Liu explains
somehow eliminates shared circuity needed to maintain the operating margin
between verification and reading (see Reply Br. 8–9), there is no persuasive
evidence on this record to substantiate such a contention. Although we
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appreciate Mr. Banks’ insights in this regard in paragraphs 8 to 18 of his
declaration, he is nonetheless an interested party, namely the inventor, in this
proceeding—a fact that reduces the probative value of his declaration, at
least with respect to his views regarding patentability of his invention over
the cited prior art. See Ashland Oil, 776 F.2d at 294. Nevertheless, Mr.
Banks’s averments do not squarely address the particular alternative noted
above by Dr. Liu, namely using four shared reference voltage supplies under
the Kitamura/Noguchi combination. To the extent that Appellant contends
that this proposed modification somehow eliminates shared circuity needed
to maintain the operating margin between verification and reading, there is
no persuasive evidence on this record to substantiate such a contention.
Lastly, we note that the propriety of the Examiner’s obviousness
rejection is not based on whether Noguchi’s features can be bodily
incorporated into Kitamura’s structure, but rather what the combined
teachings of the references would have suggested to those of ordinary skill
in the art. See In re Keller, 642 F.2d 413, 425 (CCPA 1981). Nor do
obviousness determinations based on teachings from multiple references
require an actual, physical substitution of elements. In re Mouttet, 686 F.3d
1322, 1332 (Fed. Cir. 2012) (citations omitted). On this record, Appellant
has not persuasively rebutted the Examiner’s proposed combination given
the cited references’ collective teachings considered in light of the evidence
of record. As noted previously, we find the proposed enhancement to
Kitamura, namely providing both conversion and selection in light of
Noguchi’s circuitry in Figure 12, would provide more versatility by enabling
analog output voltage levels to be set independently to best suit the memory
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cell’s characteristics as the Examiner and Dr. Liu indicate. See Ans. 4–8,
20–22, 42–43; see also Liu Decl. ¶ 100. This proposed enhancement uses
prior art elements predictably according to their established functions—an
obvious improvement. See KSR, 550 U.S. at 417.
To the extent Appellant contends that our reliance on the fundamental
notion that obviousness determinations based on teachings from multiple
references do not require an actual, physical substitution of elements, but
rather what the cited references’ collective teachings would have suggested
to ordinarily skilled artisans, see Mouttet, 686 F.3d at 1332, is somehow
inapplicable to the Examiner’s obviousness rejection because the rejection is
ostensibly limited to substituting one circuit for another as was contended in
the related appeal,7 we disagree. Nevertheless, to the extent the Examiner’s
articulated basis for the rejection and Answer somehow ignores or otherwise
discounts this fundamental obviousness principle, we nonetheless reiterate it
here as an independent basis for obviousness and, therefore, designate our
affirmance as a new ground of rejection.
Lastly, to the extent Appellant contends that our relying on portions of
Dr. Liu’s testimony that were not cited explicitly by the Examiner somehow
renders our decision in the related appeal inapplicable to the present appeal
or otherwise runs counter to the Examiner’s findings and conclusions (see
Appeal Br. 8–9), we disagree. Nevertheless, we designate this aspect of our
decision as a new ground of rejection consistent with our treatment of this

7 Ex parte MLC Intellectual Property, LLC, Appeal 2020-005915 (PTAB
Nov. 2, 2020), reh’g granted (PTAB Mar. 1, 2021), at 4–5 (including this
independent basis for obviousness as part of the Board’s new ground of
rejection).
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issue in the related appeal. See Ex parte MLC Intellectual Property, LLC,
Appeal 2020-005915 (PTAB Nov. 2, 2020), reh’g granted (PTAB Mar. 1,
2021).
Therefore, we are not persuaded that the Examiner erred in rejecting
claim 15, and claims 16 and 17 not argued separately with particularity.

CONCLUSION
The Examiner’s decision rejecting claims 15–17 is affirmed. We
designate our affirmance of the Examiner’s rejection as a new ground of
rejection.

DECISION SUMMARY
In summary:
Claim(s)
Rejected
35
U.S.C.
§
Reference(s)/Basis Affirmed Reversed New
Ground
15–17 103 Kitamura, Noguchi 15–17 15–17

REQUESTS FOR EXTENSIONS OF TIME
Requests for extensions of time in this ex parte reexamination
proceeding are governed by 37 C.F.R. § 1.550(c). See 37 C.F.R. § 41.50(f).

NEW GROUND OF REJECTION
This decision contains a new ground of rejection pursuant to 37
C.F.R. § 41.50(b). Section 41.50(b) provides “[a] new ground of rejection
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pursuant to this paragraph shall not be considered final for judicial review.”
Section 41.50(b) also provides:
When the Board enters such a non-final decision, the
appellant, within two months from the date of the decision,
must exercise one of the following two options with respect to
the new ground of rejection to avoid termination of the appeal
as to the rejected claims:

(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new Evidence relating
to the claims so rejected, or both, and have the matter
reconsidered by the examiner, in which event the prosecution
will be remanded to the examiner. The new ground of rejection
is binding upon the examiner unless an amendment or new
Evidence not previously of Record is made which, in the
opinion of the examiner, overcomes the new ground of rejection
designated in the decision. Should the examiner reject the
claims, appellant may again appeal to the Board pursuant to this
subpart.

(2) Request rehearing. Request that the proceeding be
reheard under § 41.52 by the Board upon the same Record. The
request for rehearing must address any new ground of rejection
and state with particularity the points believed to have been
misapprehended or overlooked in entering the new ground of
rejection and also state all other grounds upon which rehearing
is sought.

Further guidance on responding to a new ground of rejection can be
found in the Manual of Patent Examining Procedure § 1214.01.

AFFIRMED
37 C.F.R. § 41.50(b)

Appeal 2021-005426
Reexamination Control 90/014,421
Patent US 5,764,571

20
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SMITH BALUCH LLP
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