Michael A. Briere

Patent Trials and Appeals Board

Apr 28, 2020

12174329 - (D) (P.T.A.B. Apr. 28, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
12/174,329 07/16/2008 Michael A. Briere 1012-1431/2007P80001
US01
8457
57579 7590 04/28/2020
MURPHY, BILAK & HOMILLER/INFINEON TECHNOLOGIES
1255 CRESCENT GREEN
SUITE 200
CARY, NC 27518
EXAMINER
SAYADIAN, HRAYR
ART UNIT PAPER NUMBER
2814
NOTIFICATION DATE DELIVERY MODE
04/28/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
official@mbhiplaw.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL A. BRIERE
Appeal 2018-007889
Application 12/174,329
Technology Center 2800
BEFORE KEVIN F. TURNER, DENISE M. POTHIER, and
MATTHEW J. MCNEILL, Administrative Patent Judges.
POTHIER, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1,2 appeals from the
Examiner’s decision to reject pending claims 1, 2, 12–16, 18, 20, 21, 26 and
27. Appeal Br. 2. We AFFIRM.

1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42(a). Appellant identifies the real party in interest as INFINEON
TECHNOLOGIES AMERICAS CORP. Appeal Br. 2.
2 Throughout this opinion, we refer to the Final Action (Final Act.) mailed
July 13, 2017, the Appeal Brief (Appeal Br.) filed January 25, 2018, the
Examiner’s Answer (Ans.) mailed June 1, 2018, and the Reply Brief (Reply
Br.) filed August 1, 2018.
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CLAIMED SUBJECT MATTER
The claims are directed to Group III-nitride (“III-nitride”) device
technology suitable for high voltage power applications. Spec. ¶¶ 2–4. The
disclosure explains the integrated circuit is used to power III-nitride devices
and that there is a desire to position the integrated driver circuit (IC) close to
the power device to lower power consumption and increase switching speed
by reducing interconnection inductance and resistance. Id. ¶¶ 5–6. To
achieve the desired results, an IC is formed in a silicon body having a
surface to serve as the substrate for a III-nitride device, and the IC and the
III-nitride device are operatively coupled to form an integrated device. Id.
¶ 7.
Claim 1, below, is illustrative of the claimed subject matter:
1. A semiconductor integrated device comprising:
a support substrate that includes a silicon body having a silicon
device formed therein;
a III-nitride body formed over a planar top surface of said
silicon body, said III-nitride body comprising a III-nitride
semiconductor device formed over said silicon body;
said planar top surface of said silicon body extending from
beneath opposite sides of said III-nitride body;
wherein said silicon device is disposed under a III-nitride
heterojunction of said III-nitride semiconductor device in a direction
perpendicular to said planar top surface and lateral to said III-nitride
semiconductor device;
wherein said III-nitride semiconductor device includes a two-
dimensional electron gas (2-DEG).

Appeal Br. 18, Claims App.
We have reviewed the Examiner’s rejection in light of Appellant’s
arguments presented in this appeal. Arguments which Appellant could have
made but did not make in the Brief are waived. See 37 C.F.R.
§ 41.37(c)(1)(iv). On the record before us, we are unpersuaded the
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Examiner has erred. Except as noted below, we adopt as our own the
findings and reasons set forth in the rejections from which the appeal is
taken and in the Examiner’s Answer.
REFERENCES
The prior art relied upon by the Examiner is:
Name Reference Date
Matthews US 4,474,624 Oct. 2, 1984
Zavracky US 4,940,672 July 10, 1990
Piner US 2003/0132433 Al July 17, 2003
Thornton US 2005/0184343 Al Aug. 25, 2005
Seacrist US 2007/0176238 Al Aug. 2, 2007
Lee KR 20030049169 A
(Abstract)
June 25, 2003

OBVIOUSNESS REJECTION OVER THORNTON,
ZAVRACKY, LEE, AND PINER

Claims 1, 2, 15, 16, 18, 20, 21, 26, and 27 are rejected under 35
U.S.C. § 103(a) as being unpatentable over Thornton, Zavracky, Lee, and
Piner (“as evidence”). Final Act. 2–6.
Claims 1, 2, and 27
Appellant argues claims 1, 2, and 27 as a group. Appeal Br. 4–13.
We select claim 1 as representative. See 37 C.F.R. § 41.37(c)(1)(iv). For
claim 1, the Examiner found Thornton teaches an integrated semiconductor
device having a support substrate (e.g., 56, 58), a silicon body having a
silicon device (e.g., poly-silicon gate 70, n- and p-channels), and a III-nitride
body comprising a III-N device (e.g., 64, 66) formed over the silicon
substrate that extends from beneath opposite sides of the III-nitride
body/device. Final Act. 3 (citing Thornton ¶¶ 20, 46, 51, Figs. 1–2, 3a–m).
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The Examiner found Thornton does not teach placing the silicon device in
the silicon body so that the device is “in a direction perpendicular to said
planar top surface” of the silicon body as recited. Final Act. 3. The
Examiner turned to Zavracky and Piner in combination with Thornton to
teach integrating silicon device within the silicon body and below a III-
nitride device as recited. Id. at 3–4 (citing Zavracky, Fig. 2 (elements 14,
22); Piner). The Examiner further turned to Lee in combination with
Thornton, Zavracky, and Piner to teach the III-nitride device can include a
two-dimensional electron gas. Id. at 5 (citing Lee, Abstract).
Appellant mainly argues Thornton fails to teach or suggest integrating
devices fabricated in different semiconductor technologies (e.g., different
material types) and disposed in different planes (e.g., silicon body extending
from beneath opposite sides of a III-nitride body) but rather uses the same
technology (e.g., the same semiconductor material) and disposed in the same
plane. See Appeal Br. 4–9 (citing Thornton ¶¶ 20–23, Abstract, Figs. 1–5b,
7a–9b). Appellant also argues the Examiner failed to articulate a reason why
an artisan would have modified Thornton based on Zavracky. Id. at 9–12.

MAIN ISSUES
(I) Under § 103, has the Examiner erred in rejecting claim 1 by
finding that Thornton, Zavracky, and Piner collectively would have taught or
suggested:
A semiconductor integrated device comprising:

a support substrate that includes a silicon body having a silicon device
formed therein; [and ]

a III-nitride body formed over a planar top surface of said silicon
body, said III-nitride body comprising a III-nitride semiconductor
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device formed over said silicon body[,] said planar top surf ace of said
silicon body extending from beneath opposite sides of said III-nitride
body[?]

(II) Is the Examiner’s reason to combine Zavracky with Thornton
supported by articulated reasoning with some rational underpinning to
justify the Examiner’s obviousness conclusion?
ANALYSIS
Based on the record before us, we find no error in the Examiner’s
rejection of claim 1.
I.
At the outset, we note that claim 1 does not recite explicitly using
different semiconductor technologies (see Appeal Br. 8) but rather using
different materials for the recited “silicon device” and the recited “III-nitride
body.” Appeal Br. 18, Claims App. To the extent Appellant’s assertions
related to different technologies include an argument unrelated to the recited
materials (see id. at 4–11), we are not persuaded. We further note that
although claim 1 recites “a silicon body having a silicon device,” this does
not preclude the device from having other materials as part of its
composition.
Turning to Thornton, Appellant argues its MOSFETs (metal oxide
semiconductor field effect transistors), which the Examiner mapped to the
recited “silicon body having a silicon device” (see Final Act. 3), and
MESFETs (metal semiconductor FETs), which the Examiner mapped to the
recited “III-nitride body” (see id,; Ans. 10), are formed in the same
semiconductor material and same plane and therefore must be made of the
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same material. See Appeal Br. 6–7 (citing Thornton ¶ 20) (reproducing
Thornton, Fig. 3m (annotated)). We are not persuaded.
Although Thornton shows a MOSFET (e.g., 52, including n-well
region 60 and p-well region 62) within the same plane as a MESFET (e.g.,
54, including p-well region 64 and n-well region 66) in Figures 3a through
3d, Thornton does not teach that the MOSFET and MESFET contain the
same materials. Thornton, Fig. 3a. For example, Thornton teaches the
MOSFET’s n-well region 60 and p-well region 62 each contain a poly-
silicon gate 70 and 74 respectively. Id. ¶ 51, Fig. 3d. Gates 70 and 74 of the
MOSFET also seem to exist in some form at the end of the semiconductor
manufacturing process. See id., Fig. 3m–n. Thornton thus teaches its
MOSFET is made from a poly-silicon and thus include “a silicon body
having a silicon device” as broadly as recited. See id. ¶ 51, Figs. 3d, m–n.
Additionally, Thornton teaches MESFETs can be fabricated from
“any other technology” than silicon, such as gallium nitride (Thornton ¶¶ 20,
22), which is a III-nitride according to the Specification (Spec. ¶ 2). Thus,
presuming without agreeing that both the MOSFET and MOSFET elements
60, 62, 64, and 66 in Thornton’s Figures 3a through 3d are made from the
same material (e.g., a III-nitride) as argued, Thornton still teaches elements
60 and 62 each include a poly-silicon material. That is, Thornton discusses
the gates as having poly-silicon (see Thornton ¶ 51) and does not discuss
using another material for the gates even when discussing (1) the different
materials that can be used for the MESFETs (see id. ¶¶ 20, 22) or (2) both
the MOSFETs and MESFETS together (see id. ¶¶ 51–59). Thus, Thornton
teaches its MOSFET is made from one material (e.g., “a silicon body having
a silicon device” as claim 1 recites) and its MESFET is made from another
material (e.g., “a III-nitride body” as claim 1 recites).
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We further agree with the Examiner that Thornton at least suggests its
MESFETs and MOSFETs can be fabricated with different materials. See
Final Act. 3; see also Ans. 10. As noted above, Thornton teaches fabricating
a MESFET from different materials (see id. ¶¶ 20, 22) but does not discuss
using different materials for a MOSFET (see id. ¶¶ 47–50). Also, contrary
to Appellant’s assertion (Reply Br. 2), Thornton’s Figure 1 is not described
as prior art. See Thornton ¶¶ 9, 20.
Nonetheless, Zavracky, cited by the Examiner, further supports and
strengthens the Examiner’s position that it was known in the art to use
different materials (e.g., silicon and non-silicon based) for devices integrated
on a silicon substrate. See Final Act. 3–4 (citing Zavracky, Fig. 2 (elements
14, 22)). Zavracky teaches a silicon device/driver (e.g., 14) integrated with a
non-silicon device (e.g., III-V device 22) in a monolithic fashion. Zavracky
1:36–39, 62–66, 4:16–19, Fig. 2. Zavracky further shows forming the
silicon device in a silicon substrate/body (e.g., 10), the silicon body’s top
surface extending beneath opposite sides of the III device’s body, and the
silicon device is disposed under a III device in a direction perpendicular to
the top surface and lateral to the III device as claim 1 recites. See id., Fig. 2.
The Examiner proposed to modify Thornton based on Zavracky’s teachings
to arrive at the claimed combination. See Final Act. 3–4.
The Examiner also cited Piner to teach integrating silicon and III-V
devices and that arranging a silicon device below a III-nitride device was
known. Id. at 4. The Specification further describes forming a III-nitride
power device over a silicon substrate is “a known design.” Spec. ¶ 4.
As such, the proposed Thornton/Zavracky/Piner combination teaches
or suggests “a support substrate that includes a silicon body having a silicon
device formed therein” and “a III-nitride body formed over a planar top
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surface of said silicon body, said III-nitride body comprising a III-nitride
semiconductor device formed over said silicon body[,] said planar top surf
ace of said silicon body extending from beneath opposite sides of said III-
nitride body” as claim 1 recites. Moreover, because the Examiner turned to
Zavracky and Piner in combination with Thornton to teach integrating
devices fabricated with different materials disposed in different planes,
Appellant’s argument directed to Thornton alone in this regard (see Appeal
Br. 4–9) is unpersuasive.
II.
Regarding Zavracky and its combination with Thornton, Appellant
argues the Examiner failed to articulate a reason why an artisan would have
modified Thornton based on Zavracky’s technology. Id. at 9–12. Appellant
further contends Zavracky concerns an optical device (e.g., a laser) and does
not relate to MOSFETs and MESFETs discussed in Thornton. Id. at 11
(citing Zavracky 1:62–65, 4:16–19, Abstract, Fig. 1h, 2, 3). We are not
persuaded.
We determine the Examiner proposed to modify Thornton’s integrated
circuit using a known technique taught by Zavracky of integrating silicon
and non-silicon devices. See Final Act. 3–4. This proposed modification
(see id.) does no more than apply a known technique of integrating devices,
such as Thornton’s integrated circuit, where its silicon-based device (e.g.,
Thornton’s MOSFET) is located within a silicon substrate as taught by
Zavracky, and predictably yields a semiconductor integrated device
arrangement where the silicon-based device is formed within a silicon body
and the non-silicon-based device is formed above the silicon substrate in a
monolithic manner. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416
(2007). Also, Zavracky teaches that silicon circuit design and fabrication
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technology is well developed and its cost are very attractive, such that
integrating III-V devices with silicon is beneficial. Zavracky 1:27–35.
Zavracky thus provides yet another reason to combine its teachings with
Thornton.
Appellant further argues one skilled in the art would not have
combined Thornton and Zavracky because Thornton does not relate to optic
devices or silicon drive circuits driving optic devices, like Zavracky, and
Zavracky does not relate to MOSFETs or MESFETS, like Thornton. Appeal
Br. 11–12. This argument is unavailing.
Although Zavracky does not address MOSFETs and MESFETS
specifically, Zavracky discusses that its semiconductor devices are part of a
circuit that contains a transistor. See Zavracky 8:3–5 (claim 18). Thus,
although not described with respect to those specific transistors, Zavracky
describes transistors generally.
Additionally, to extent Appellant contends Zavracky is non-analogous
art (see Appeal Br. 11–12), we determine Zavracky is reasonably pertinent
to the problem with which the inventor was concerned. The Specification
describes a desire to position an integrated driver circuit close to a power
device to lower power consumption and increase switching speed. Spec.
¶ 6. Zavracky teaches a monolithic integration technology that positions an
integrated driver circuit (e.g., silicon driver 14) near to a power device (e.g.,
III-V device 22) (Zavracky 1:36–39, Fig. 2) and thus is reasonably pertinent
to the inventor’s concerned problem. The Examiner further states that
lasers, such as element 22 in Zavracky, are high power devices (see Ans.
11), and Thornton concerns III-nitride devices (Thornton ¶¶ 20, 22), which
are known for driving power devices (see Spec. ¶ 5). Appellant does not
rebut these findings in the Appeal Brief or the Reply Brief. See generally
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Appeal Br. and Reply Br. Thus, both Thornton and Zavracky are within the
inventor’s field of endeavor related to driving power devices in high power
applications. See id. ¶¶ 4–5.
Lastly, Appellant argues that the Examiner only presents a conclusory
statement that it would have been obvious to modify Thornton based on
Lee’s teachings without articulating a reason an artisan would have been
motivated to modify Thornton as proposed. Appeal Br. 12–13. We
disagree. The Examiner cited to Lee, indicating that using nitride HEMTs
(High Electron Mobility Transistor) as a power transistor is recognized by an
ordinarily skilled artisan “to have increased density” and “to improve the
high power and frequency characteristics of the transistor.” Final Act. 5
(citing Lee, Abstract). Lee similarly states that manufacturing an HEMT
“having the increased electron density of two dimensional electron gas is
provided to be capable of improving the high power and frequency
characteristics of the transistor . . . .” Lee, Abstract. Thus, the Examiner’s
statement is supported by Lee, provides a reason for the combination, and is
not conclusory.
For the foregoing reasons, Appellant has not persuaded us of error in
the rejection of (1) independent claim 1 and (2) dependent claims 2 and 27
for similar reasons.

Claims 18, 20, and 21
Appellant separately argues independent claim 18. Appeal Br. 12.
Dependent claims 20 and 21 are not separately argued. See generally id. at
4–17. We select claim 18 as representative. See 37 C.F.R. § 41.37(c)(1)(iv).
For those arguments that are the same for both claims 1 and 18, we
are not persuaded and refer to the above discussion.
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Appellant further contends that the Specification discloses the III-
nitride devices are for high voltage applications and Zavracky is not
configured for this application. Appeal Br. 12 (citing Spec. ¶¶ 4, 31). To
clarify, the Specification states III-nitride “is suitable for high voltage power
applications” (Spec. ¶ 4 (emphasis added)), not just high voltage
applications. Also, as the Examiner notes (see Ans. 11), claim 18 does not
recite a high voltage device or even that the recited integrated semiconductor
device is for a high voltage application. Id. (stating “the claims . . . fail to
recite any feature related to high voltage.”); Appeal Br. 19, Claims App. We
therefore determine this argument is unavailing.
For the foregoing reasons, Appellant has persuaded us of error in the
rejection of (1) independent claim 18 and (2) dependent claims 20 and 21 for
similar reasons.
Claim 26
Claim 26 depends from claim 1 and further recites “said silicon device
comprises a passive device configured for use with said III-nitride
semiconductor device.” Appeal Br. 20, Claims App. The Examiner maps
any of Thornton’s silicide contacts to the recited “passive device.” Final
Act. 6.
Appellant argues Thornton’s silicide contacts are not passive devices
configured for use with the III-nitride semiconductor device. Appeal Br. 13.
Appellant contests that these contacts act as contacts to and above
Thornton’s source, drain, and channel regions and an oxide layer separates
the ohmic contact silicide formed on the source and drain contact from the
Schottky gate silicide formed on regions 64 and 66. Id. at 13–14 (quoting
from Thornton ¶¶ 51–52). Appellant thus argues Thornton’s contacts are not
passive devices that form part of “said silicon device” and configured for use
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with said III-nitride semiconductor device as required by claim 26. Id. at 14.
We are not persuaded.
Thornton discusses a gate oxide formed above MOSFET regions but
removed from the MESFET. Thornton ¶ 51, Fig. 3c. Thornton further
describes integrating MOSFETs and MESFETs on the same substrate using
a patterned deposited oxide layer that allows silicide to form and produce
contacts above regions 64 and 66 of MESFET devices and separates these
contacts from the contacts formed on the highly doped source and drain
contacts of the MOSFET. Id. ¶ 52, Fig. 3e. But, Thornton additionally
describes the final manufacturing step involves making electrical contacts to
the MOSFET and MESFET devices, including using plugs to connect the
noted contacts and wiring the transistors together. Id. ¶ 59, Fig. 3m–n. We
therefore disagree that Thornton’s contacts fail to represent the recited
“passive device configured for use with said III-nitride semiconductor
device” in claim 26 as Appellant argues.
Appellant also contends Thornton’s contacts are used as low-resistant
contacts to an active region and do not represent a passive device “as is well-
known in the relevant art.” Appeal Br. 14. This argument is unavailing for
three reasons. First, Appellant provides no support for this statement,
amounting to an argument that cannot take the place of factually supported
evidence. See In re Huang, 100 F.3d 135, 139–40 (Fed. Cir. 1996); see Ans.
11. Second, the Specification does not describe a passive device3 or limit its
meaning (see generally Spec.), such that low-resistant contacts cannot
reasonably map to passive devices when considering the disclosure. Third,
even assuming that a “passive device” is the opposite of an “active device,”

3 A rejection based on a lack of written description is not before us.
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as would have been understood by ordinary artisans, at the time, it is not
clear how Thornton’s contacts, not being an active semiconductor device,
would not satisfy the limitations of claim 26.
We therefore sustain the rejection of claim 26.
Claims 15 and 16
Claim 15 depends from claim 1 and further recites, in pertinent part,
“said silicon device formed in said silicon body comprises a logic device for
operating said power semiconductor device.” Appeal Br. 19, Claim App.
Claim 16 depends from claim 15. Id. The Examiner found Piner in
combination with Thornton, Zavracky, and Lee teach claim 15 and 16’s
features. Final Act. 7–8 (citing Piner ¶¶ 58, 62).
Appellant argues that a digital device, like Piner’s, “does not
necessarily represent a logic device” as claim 15 recites. Appeal Br. 16
(bolding and underlining omitted). Appellant also argues that Piner’s digital
device is not taught to be formed in a silicon body and so there would have
been no reason to modify Thornton based on Piner’s teaching. Id. at 16–17.
We are not persuaded.
As to the later contention, this argument attacks Piner alone without
considering the rejection as proposed, which as previously discussed, relied
on Zavracky and Piner in combination with Thornton to teach or suggest the
recited “silicon device formed in said silicon body” as claimed.
As to the former contention, Appellant merely asserts without
providing supporting evidence that Piner’s digital device is not a logic
device. See id. at 16. On the other hand, the Examiner explains Piner
teaches a silicon geranium-based device can be used as a driver circuit
(Piner ¶ 62) and Piner’s disclosed driver circuit functions as a logic device.
See Ans. 12–13 (citing Piner ¶ 62). Appellant does not rebut this finding.
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See, e.g., Reply Br. Thus, based on the record, Appellant has not persuaded
us of error in the rejection of claim 15 and claim 16, which is not separately
argued from claim 15.

OBVIOUSNESS REJECTION OVER THORNTON,
ZAVRACKY, LEE, PINER, AND MATTHEWS

Claims 12 depends from claim 1 and recites “said support substrate is
a N++ doped silicon substrate.” Appeal Br. 18, Claims App. Claim 12 is
rejected based on Thornton, Zavracky, Lee, Piner (as evidence), and
Matthews. Final Act. 6 (citing Matthews 3:19–32).
Appellant argues Thornton’s MOSFET and MESFET are formed
above oxide layer 58 and electrically insulated from substrate 56. Appeal
Br. 15. For this reason, Appellant contends there would have been no reason
to modify Thornton’s silicon substrate 56 to be N++ doped or P++ doped
because of its recognized suitability as a substrate as the Examiner asserts.
Id. Appellant further contends the Examiner’s reliance on the Manual of
Patent Examination and Procedure (MPEP) § 2144.07 is misplaced, and
there are no tangible benefits to doping Thornton’s substrate 56. Id. at 15–
16. We are not persuaded.
This argument again does not consider the proposed rejection, which
relies on modifying Thornton based on Zavracky’s (and Piner’s) teaching,
such that the recited silicon device is located in the silicon body of the
silicon substrate and below the III-nitride body as recited. Final Act. 2–4
(proposing to modify Thornton with Zavracky’s teaching and resulting in a
silicon device being below the substrate’s surface). Additionally,
Zavracky’s Figure 2 teaches at least one embodiment where an integrated III
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device and a silicon device are arranged on a silicon substrate even with an
intermediary, patterned oxide layer (e.g., 26) (see Zavracky 4:6–12, Fig. 2),
demonstrating that Thornton’s substrate, when modified by Zavracky, will
not be electrically insulated from its substrate.
Concerning MPEP § 2144.07 and the Examiner’s reasons for
combining Matthews with the other references, Matthews states that is
preferable to form complementary transistors in a layer grown on a highly
doped n++ silicon substrate. Matthews 3:19–22. Although Matthews does
not describe it benefits, Matthews implies that such a substrate is beneficial
to ordinary skilled artisan because it is suitable for forming CMOS
transistors (see id. at 3:1–22), similar to the MOSFETs discussed in
Thornton (see Thornton ¶¶ 42–43) and which are located in the silicon body
when modified by Zavracky as previously discussed. We therefore agree
with the Examiner that Matthews suggests N++ doped silicon substrate is a
known material suitable for the intended purpose of growing transistors and
thus, the Examiner’s reliance on MPEP § 2144.07 is not entirely misplaced.
In any event, the proposed modification does no more than apply Matthew’s
known technique of doping a silicon substrate, such as Thornton’s substrate
when modified based on Zavracky’s teaching, and predictably yields a
support substrate that is N++ doped. See KSR, 550 U.S. at 416.
For the foregoing reasons, Appellant has not persuaded us of error in
the rejection of claim 12.

OBVIOUSNESS REJECTION OVER THORNTON,
ZAVRACKY, LEE, PINER, AND SEACRIST

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Claims 13 and 14 depend from claim 1. Appeal Br. 18, Claims App.
Claim 13 recites “said support substrate is a p++ doped silicon substrate,”
and claim 14 recites “said silicon body includes an epitaxially formed
portion.” Id. Claims 13 and 14 are rejected based on Thornton, Zavracky,
Lee, Piner (as evidence), and Seacrist. Final Act. 2–3 (claim 1), 6–7 (citing
Seacrist ¶ 9).
For claim 13, Appellant argues claims 12 and 13 together. Appeal Br.
14–16. We are not persuaded of error for the reasons previously presented
when addressing claim 12. We add that Seacrist, similar to Matthews, states
CMOS applications are known to have silicon substrate doped to a P++
concentration. Seacrist ¶ 9. Thus, Seacrist, like Matthews, is suitable for
forming CMOS transistors (see id. at 3:1–22), like Thornton’s MOSFETs
and which are located in a silicon body when modified by Zavracky as
previously discussed.
For claim 14, Appellant argues the Examiner failed to provide
evidentiary support to teach the feature of the “silicon body including an
epitaxially formed portion” and did not establish a prima facie case of
obviousness. Appeal Br. 14 (citing Final Act. 6–7). This argument is
unavailing. The rejection cites Seacrist to teach an epitaxial layer doped
with a p concentration suitable for a substrate. Id. at 7 (citing Seacrist ¶ 9).
In particular, Seacrist discloses a CMOS silicon wafer comprising an
epitaxial layer doped to a P concentration, at least suggesting forming an
epitaxial portion on a silicon substrate. See Seacrist ¶ 9. Additionally, this
rejection does not just rely on Seacrist but also on the teachings of Thornton,
Zavracky, and Piner to teach and suggest the silicon body feature as claim 1
recites from which claim 14 depends. See Final Act. 2–4. The Examiner
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also provides a line of reasoning for its proposed combination. See id. at 7.
Based on the record, a prima facie case of obviousness has been established.
For the foregoing reasons, Appellant has not persuaded us of error in
the rejection of claims 13 and 14.
DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C.
§
References Affirmed Reversed
1, 2, 15, 16,
18, 20, 21,
26, 27
103 Thornton,
Zavracky, Lee,
Piner
1, 2, 15, 16,
18, 20, 21,
26, 27

12 103 Thornton,
Zavracky, Lee,
Piner,
Matthews
12
13, 14 103 Thornton,
Zavracky, Lee,
Piner, Seacrist
13, 14
Overall
Outcome
1, 2, 12–16,
18, 20, 21,
26, 27

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED