Mehul A. Shah et al.

Patent Trials and Appeals Board

Jan 9, 2020

14343010 - (D) (P.T.A.B. Jan. 9, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/343,010 03/05/2014 Mehul A. Shah 83789137 5149
56436 7590 01/09/2020
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
EXAMINER
BRAGDON, REGINALD GLENWOOD
ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
01/09/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
chris.mania@hpe.com
hpe.ip.mail@hpe.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE PATENT TRIAL AND APPEAL BOARD

Ex parte MEHUL A. SHAH, SLAVROS HARTZOPOULOS,
ARIF A. MERCHANT, and MOHIT SAXENA

Appeal 2018-008980
Application 14/343,010
Technology Center 2100

Before ERIC S. FRAHM, JOHN A. EVANS, and JUSTIN BUSCH,
Administrative Patent Judges.

BUSCH, Administrative Patent Judge.

DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–15, which constitute all the claims
pending in this Application. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42(a). Appellant identifies the real parties in interest as Hewlett Packard
Enterprise Development LP, a wholly-owned affiliate of Hewlett Packard
Enterprise. Appeal Br. 3.
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CLAIMED SUBJECT MATTER
Appellant’s disclosure generally relates to systems and methods for
“imparting durability to a transactional memory system.” Spec. ¶ 7. The
claimed invention relates to a transactional memory system using “volatile
memory as primary storage for transactions” and selectively storing data “in
a non-volatile memory to impart durability to the transactional memory
system to allow the transactional memory system to be restored to a
consistent state in the event of data loss to the volatile memory.” Spec.,
Abstract. Claims 1, 8, and 9 are independent claims. Claim 12 is reproduced
below:
1. A method comprising:
a transactional memory system instilling properties of
atomicity, consistency and isolation for transactions associated
with a plurality of processing entities that share a memory of the
transactional memory system;
using a volatile memory as primary storage for the
transactions; and
selectively storing data in a non-volatile memory to impart
durability to the transactional memory system to allow the
transactional memory system to be restored to a consistent state
in the event of data loss to the volatile memory.

2 Given the breadth of claim 1 (as well as claims 8 and 9), should this matter
undergo further prosecution, the Examiner may wish to consider whether
these claims meet the requirements of 35 U.S.C. § 112(a). Specifically, the
Examiner may wish to evaluate whether the written description supports and
enables the full scope of the independent claims, which are not limited to the
particular embodiment using checkpoints and partition logging disclosed in
the Specification.
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REJECTIONS
Claims 1, 7–9, and 14 stand rejected under 35 U.S.C. § 103 as obvious
in view of Lee (US 2007/0011416 A1; Jan. 11, 2007) and Wu (US
2008/0126755 A1; May 29, 2008). Final Act. 2–3.
Claims 2 and 10 stand rejected under 35 U.S.C. § 103 as obvious in
view of Lee, Wu, and Busaba (US 9,298,469 B2; Mar. 29, 2016). Final
Act. 4.
Claims 3, 5, 6, 11, and 13 stand rejected under 35 U.S.C. § 103 as
obvious in view of Lee, Wu, and Kern (US 2009/0193193 A1; July 30,
2009). Final Act. 4–6.
Claims 4 and 11 stand rejected under 35 U.S.C. § 103 as obvious in
view of Lee, Wu, and Assad (US 2011/0219208 A1; Sept. 8, 2011). Final
Act. 6–7.
Claim 15 stands rejected under 35 U.S.C. § 103 as obvious in view of
Lee, Wu, and Patil (US 8,806,096 B1; Aug. 12, 2014). Final Act. 7–8.
ANALYSIS
The Examiner finds a combination of Wu and Lee teaches or suggests
every limitation recited in independent claims 1, 8, and 9. Final Act. 2–3.
More specifically, the Examiner finds Lee teaches or suggests a memory
system using volatile memory as primary storage and selectively storing data
to non-volatile memory (as a backup) to impart durability to the memory
system. Final Act. 2–3 citing Lee ¶¶ 7, 20, 21, Fig. 2. The Examiner further
finds Lee teaches a transactional memory system instilling the properties
(i.e., atomicity, consistency, and isolation) of such a memory system. Final
Act. 3 (citing Wu ¶¶ 5, 17, 21, Fig. 4). The Examiner determines a person of
ordinary skill in the art would have combined modified Lee to include Wu’s
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transactional memory system properties (i.e., atomicity, consistency, and
isolation) to “increase parallel performance.” Final Act. 3 (citing Wu ¶ 4);
see also Ans. 4 (“If a system is equipped to run a transaction to modify to
run multiple transactions will increase its performance to run them in
parallel as set forth in the rejection.”).
Appellant argues it is unclear how a transactional memory system,
such as Wu’s memory system, would be implemented on Lee’s smart card or
how the proposed combination would result in a transactional memory
system in which data is selectively stored in non-volatile memory to impart
durability to the transactional memory system. Appeal Br. 9. Appellant
asserts that, without impermissible hindsight, Lee’s disclosure of a non-
volatile backup memory does not suggest selectively storing data in a
transactional memory system to a non-volatile memory in a way that instills
durability because merely backing up memory from a volatile memory to a
non-volatile memory, as taught by Lee, would not instill durability in a
transactional memory system. Appeal Br. 10; see Reply Br. 1–2 (explaining
that Lee simply discloses storing data in a smart card, including a primary
storage area in volatile memory and a backup storage area in non-volatile
memory, but does not contemplate storing data in a transactional memory
system and distinguishing transactional memory system “in flight”
transactions from mere data storage). Appellant argues a person of ordinary
skill in the art therefore would not have modified Lee in light of Wu’s
transactional memory system to impart durability to the transactional
memory system. Appeal Br. 10.
Appellant further argues “it is entirely unclear why such a
transactional memory system would even be implemented on a smart card.”
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Appeal Br. 10; see also Appeal Br. 10 (arguing “Lee’s smart card does not
include a plurality of processing entities,” but the Examiner has not provided
a plausible reason “why one of ordinary skill in the art in possession of Lee
and Wu would have derived a smart card having parallel processing, absent
improper hindsight gleaned solely from the instant application”). Appellant
also contends it is unclear “why one of ordinary skill in the art would desire
a multiprocessing smart card, and the Examiner’s Answer still fails to
explain the motivation.” from Reply 2–3.
According to Wu, transactional memory systems provide increased
parallel performance as compared to conventional lock-based systems. Wu
¶¶ 2–5. Therefore, Wu’s invention addresses “converting the lock-based
instruction construct [in legacy programs] to a transactional instruction
construct . . . using a translator.” Wu ¶ 6; see also Wu ¶ 1 (describing the
invention as generally relating “to methods and apparatus to translate a
source instruction construct to form a transactional objective instruction
construct”).
Lee relates to “a source/destination memory, a non-volatile backup
memory, and a transaction management module . . . adapted to erase a
plurality of memory location[s] in backup memory upon initialization of the
apparatus or following a primary data transaction.” Lee, Abstract. “More
particularly, embodiments of the invention relate to a data storage apparatus
and method capable of reducing the time required to store (or back up) data
in a non-volatile memory.” Lee ¶ 2. Lee’s invention is directed to data
storage apparatus and methods to “reduce the amount of time required to
implement data backup safeguards in mobile data storage system, such as a
smart card.” Lee ¶ 10. Lee accomplishes this improvement by
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simultaneously erasing the backup area as opposed to erasing each
individual memory location separately prior to writing to that memory
location. Lee ¶¶ 29–33.
Appellant notes, and the only evidence of record supports, that a
“transactional memory system” is a known term in the art. Appeal Br. 9
(citing Spec. ¶ 7 (“a ‘transactional memory system’ is a system that allows
multiple processing entities (threads, for example) to share a memory while
providing isolation among the threads for accesses to the memory.”)); Wu
¶¶ 2–5. It is also undisputed that Lee does not teach a transactional memory
system. Final Act. 3 (“Lee does not explicitly teach instilling properties of
atomicity, consistency and isolation for transactions associated with the
transactional memory system”); Appeal Br. 9.
We agree with Appellant that the Examiner’s rationale for combining
Lee’s and Wu’s teachings is problematic. It is undisputed on this record that
Lee relates to smart card memory, not a transactional memory system.3 The
Examiner’s reason for modifying Lee is to increase parallel performance in
Lee’s smart card. Final Act. 3 (citing Wu ¶ 4). This reason, however, simply
captures Wu’s explanation of known benefits of a transactional memory
system without providing any rational underpinning regarding why one of
ordinary skill in the art would have added such a transactional memory
system to Lee’s systems and methods for backing up data in a smart card.
Importantly, the Examiner’s rationale lacks a reasonable underpinning
because the Examiner provides insufficient explanation as to why a person of

3 Given the well-known nature of transactional memory systems, Lee’s
smart card memory management techniques do not seem to be the most
relevant prior art to the claimed invention.
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ordinary skill in the art would have combined a transactional memory
system with Lee’s smart card. See KSR Int’l Co. v. Teleflex Inc., 550 U.S.
398, 418 (2007).
Accordingly, we are constrained by this record to reverse the
Examiner’s rejection of independent claims 1, 8, and 9 under 35 U.S.C.
§ 103 as obvious in view of Lee and Wu. Claims 7 and 14 depend directly
from, and incorporate the limitations of, claims 1 and 9, respectively.
Therefore, for the same reasons, we also reverse the Examiner’s rejection of
dependent claims 7 and 14 under 35 U.S.C. § 103 as obvious in view of Lee
and Wu. Claims 2–6 depend directly from claim 1 and incorporate claim 1’s
limitations. Claims 10–13 and 15 depend directly from claim 9 and
incorporate claim 9’s limitations. The Examiner does not find any of
Busaba, Kern, Assad, and Patil, cited in the rejections of claims 2–6, 10–13,
and 15, cure the deficiency identified with respect to claims 1 and 9.
Therefore, we also reverse the Examiner’s rejection of claims 2–6, 10–13,
and 15 under 353 U.S.C. § 103 as obvious in view of Lee and Wu in
combination with one of Busaba, Kern, Assad, and Patil.
CONCLUSION
The Examiner’s rejections of claims 1–15 under 35 U.S.C. § 103 are
reversed.
DECISION SUMMARY
In summary:
Claims Rejected 35 U.S.C. § Basis Affirmed Reversed
1, 7–9, 14 103 Lee, Wu 1, 7–9, 14
2, 10 103 Lee, Wu, Busaba 2, 10
3, 5, 6, 11, 13 103 Lee, Wu, Kern 3, 5, 6, 11, 13
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Claims Rejected 35 U.S.C. § Basis Affirmed Reversed
4, 12 103 Lee, Wu, Assad 4, 12
15 103 Lee, Wu, Patil 15
Overall Outcome 1–15
REVERSED