LG Electronics, Inc.v.Advanced Micro Devices, Inc.

Patent Trial and Appeal Board

May 23, 2016

09798176 (P.T.A.B. May. 23, 2016)

Trials@uspto.gov Paper 39
571-272-7822 Entered: May 23, 2016

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

LG ELECTRONICS, INC.,
Petitioner,

v.

ADVANCED MICRO DEVICES, INC.,
Patent Owner.
____________

Case IPR2015-00324
Patent 6,895,520 B1
____________

Before JONI Y. CHANG, BRIAN J. McNAMARA, and
RAMA G. ELLURU, Administrative Patent Judges.

CHANG, Administrative Patent Judge.

FINAL WRITTEN DECISION
35 U.S.C. § 318(a) and 37 C.F.R. § 42.73

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I. INTRODUCTION
LG Electronics, Inc. (“LG”) filed a Petition requesting an inter partes
review of claims 16–18 and 20–23 of U.S. Patent No. 6,895,520 B1
(Ex. 1001, “the ’520 patent”). Paper 2 (“Pet.”). Patent Owner, Advanced
Micro Devices, Inc. (“AMD”), filed a Preliminary Response. Paper 12
(“Prelim. Resp.”). Upon consideration of the Petition and Preliminary
Response, we instituted this trial as to claims 16–18 and 20–23 of the ’520
patent on June 15, 2015. Paper 13 (“Dec.”).
Subsequent to institution, AMD filed a Patent Owner Response
(Paper 21, “PO Resp.”) and LG filed a Reply to the Patent Owner Response
(Paper 25 “Reply”). An oral hearing was held on February 10, 2016.1
We have jurisdiction under 35 U.S.C. § 6(c). This Final Written
Decision is issued pursuant to 35 U.S.C. § 318(a). For the reasons discussed
herein, we determine that LG has shown by a preponderance of the evidence
that claims 16–18 and 20–23 of the ’520 patent are unpatentable.
A. Related Matter
The ’520 patent is asserted in Advanced Micro Devices, Inc. v. LG
Electronics, Inc., No. 3:14-cv-01012-SI (N.D. Cal.). Pet. 1.

1 A transcript of the oral hearing has entered in the record as Paper 36
(“Tr.”).
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B. The ’520 patent
The ’520 patent is titled “Performance and Power Optimization via
Block Oriented Performance Measurement and Control.” Ex. 1001, at [54].
The ’520 patent describes a system for monitoring the utilization of the
functional blocks in an integrated circuit and for optimizing the power
consumption and performance levels of each block. Id. at 1:62–65.
C. Illustrative Claim
Of the challenged claims, claims 16 and 23 are the only independent
claims. Claims 17, 18, and 20–22 depend ultimately from claim 16.
Claim 16, reproduced below, is illustrative of the claimed subject matter.
16. An integrated circuit comprising:
a plurality of functional blocks;
utilization circuits respectively associated with the functional
blocks coupled to provide block utilization information of the
functional blocks; and wherein
the integrated circuit is responsive to the block utilization
information to independently adjust power consumption levels of
the functional blocks to match respective block utilization levels.
Ex. 1001, 9:14–22 (emphases added).
D. Prior Art Relied Upon
LG relies upon the following prior art references:
Bertin US 6,345,362 B1 Feb. 5, 2002 (Ex. 1003)
(filed Apr. 6, 1999)
Gunther US 5,781,783 July 14, 1998 (Ex. 1004)
Matsuzaki US 5,418,969 May 23, 1995 (Ex. 1005)
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ADVANCED CONFIGURATION AND POWER INTERFACE SPECIFICATION,
INTEL, MICROSOFT, TOSHIBA, Rev. 1.0b (Feb. 2, 1999) (Ex. 1006, “ACPIS”).
Whether the ACPIS is a Printed Publication
LG asserts that ACPIS qualifies as prior art under 35 U.S.C. § 1022
because it was published on February 2, 1999, before the filing date of the
’520 patent, March 2, 2001. Pet. 9. AMD, however, disagrees, arguing that
the “February 2, 1999” date on the first page of the ACPIS, the copyright
dates (“Copyright © 1996, 1997, 1998, 1999 Intel Corporation, Microsoft
Corporation, Toshiba Corp.”) on the second page, and the “February 1999”
revision history date on the third page, do not demonstrate that the interested
public was able to access the document on any of those dates. PO Resp. 57–
58; Ex. 1006, 1–3.
Having reviewed the evidence in this record, we are not persuaded by
AMD’s arguments. Rather, we determine that LG has provided sufficient
evidence to support that the ACPIS was publicly accessible before the filing
date of the ’520 patent.
The determination of whether a given reference qualifies as a prior art
“printed publication” involves a case-by-case inquiry into the facts and
circumstances surrounding the reference’s disclosure to members of the
public. In re Klopfenstein, 380 F.3d 1345, 1350 (Fed. Cir. 2004). “Because
there are many ways in which a reference may be disseminated to the

2 Because the ’520 patent was filed before the enactment of the Leahy-Smith
America Invents Act, Pub. L. No. 112-29, 125 Stat. 284 (2011) (“AIA”), the
pre-AIA version of 35 U.S.C. §§ 102 and 103 applies in this trial.
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interested public, ‘public accessibility’ has been called the touchstone in
determining whether a reference constitutes a ‘printed publication’ bar under
35 U.S.C. § 102(b).” In re Hall, 781 F.2d 897, 898–99 (Fed. Cir. 1986).
To qualify as a prior art printed publication, the reference must have been
disseminated or otherwise made accessible to persons interested and
ordinarily skilled in the subject matter to which the document relates prior to
the critical date. Kyocera Wireless Corp. v. Int’l Trade Comm’n, 545 F.3d
1340, 1350 (Fed. Cir. 2008).
Here, LG’s expert witness, Dr. Paul Min, testifies that he is familiar
with the normal practices of standard setting groups in the computer
industry, including the Advanced Configuration and Power Interface
(“ACPI”) group, which allegedly published the ACPIS, and the United
Extensible Firmware Interface (“UEFI”) group, which is the successor
organization to the ACPI group. Ex. 1035 ¶¶ 95, 100. Dr. Min also testifies
that the ACPIS was promulgated by Microsoft, Intel, and Toshiba with the
intention of obtaining support by a wide array of hardware manufacturers
and software developers. Id. at ¶ 98. Dr. Min further notes that the ACPIS
does not have any “DRAFT” or “INTERNAL” markings, and that the dates
on the ACPIS are listed in the standard format, supporting his assessment
that it was accessible to the public on or around February 2, 1999. Id. at
¶¶ 96–99. More importantly, Dr. Min testifies that he verified the
documentation from UEFI, including a printout of its webpage
(www.uefi.org/acpi/specs), which maintains older versions of the ACPI
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specifications and their publication dates, confirming that the ACPIS has a
publication date of February 8, 1999. Id. at ¶¶ 100–03; Ex. 1013; Ex. 1014.
In addition, LG maintains that at least 10 different patent application
publications and technical publications, from 1999 to 2000, cited to the
ACPIS, reflecting the authors’ understanding that the ACPIS was publicly
accessible and could be accessed by the readers of their publications.
Reply 24 (citing, e.g., Exs. 1010–12, 1020, 1022–25). As support, Dr. Diana
Marculescu testifies that she is the author of several technical publications
dated from 1999 to 2000 (Exs. 1011, 1022, 1023), citing the ACPIS with an
Internet address from which the ACPIS could be downloaded. Ex. 1036
¶¶ 10–12. Dr. Marculescu also testifies that she downloaded the ACPIS,
freely without any restriction, from the ACPI website before October 31,
1999, when she submitted a technical paper (Ex. 1011) for publication.
Ex. 1036 ¶ 13.
LG further points out that AMD filed a patent application on May 31,
2000, that incorporated by reference the ACPIS, confirming that AMD
considered the ACPIS to have been publicly released on its “February 2,
1999” date.3 Reply 24. Indeed, AMD’s patent application issued as U.S.
Patent No. 7,039,755 B1 states that “[v]arious power management and

3 As a practice note, counsel for AMD is reminded that “a party must serve
relevant information that is inconsistent with a position advanced by the
party during the proceeding concurrent with the filing of the documents or
things that contains the inconsistency.” 37 C.F.R. § 42.51(b)(1)(iii); see also
37 C.F.R. §§ 42.1(b), 42.12(a)(2).
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configuration mechanisms are defined by the Advanced Configuration and
Power Interface (ACPI) specification, Revision 1.0b, dated Feb. 2, 1999,
which is incorporated herein by reference.” Ex. 10324, 1:15–22.
For the foregoing reasons, the evidence in this record sufficiently
supports that the ACPIS was available publicly before the filing date of the
’520 patent. We determine that LG has shown by a preponderance of the
evidence that the ACPIS is a printed publication under § 102. Therefore, LG
may rely upon the ACPIS for its asserted ground of unpatentability under
§ 103(a).
E. Instituted Grounds of Unpatentability
We instituted the instant trial based on the following grounds of
unpatentability (Dec. 23):
Challenged Claims Basis References
16–18 and 20 § 102(e) Bertin
21–23 § 103(a) Bertin
16–18 and 20 § 102(b) Gunther
21–23 § 103(a) Gunther and ACPIS

4 U.S. Patent No. 7,039,755 B1 listed AMD as the assignee. Ex. 1032,
at [73].
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II. ANALYSIS
A. Claim Construction
In an inter partes review, claim terms in an unexpired patent are given
their broadest reasonable construction in light of the specification of the
patent in which they appear. 37 C.F.R. § 42.100(b). Under the broadest
reasonable interpretation standard, claim terms are given their ordinary and
customary meaning as would be understood by one of ordinary skill in the
art in the context of the entire disclosure. In re Translogic Tech., Inc., 504
F.3d 1249, 1257 (Fed. Cir. 2007). An inventor may rebut that presumption
by providing a definition of the term in the specification with reasonable
clarity, deliberateness, and precision. In re Paulsen, 30 F.3d 1475, 1480
(Fed. Cir. 1994). In the absence of such a definition, limitations are not to
be read from the specification into the claims. In re Van Geuns, 988 F.2d
1181, 1184 (Fed. Cir. 1993).
We construe the terms recited in the claims at issue in accordance
with the above-stated principles, and address below each of the claim terms
identified by the parties.
“register” and “utilization circuit”
LG proposes constructions for the following claim terms: “register”
and “utilization circuit.” Pet. 7. AMD does not dispute LG’s proposed
constructions for “register” and “utilization circuit.” PO Resp. 10–24. We
have reviewed LG’s proposed constructions for these terms and determine
that they are consistent with the broadest reasonable construction.
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Therefore, we adopt the following claim constructions for purposes of this
Decision:
Claim Term Construction
register a circuit or circuit element that stores a value
utilization circuit a circuit or circuit element that provides utilization information for a functional block

“block utilization information”
The term “block utilization information” appears in claims 16, 20, 22,
and 23. For example, claim 16 recites “utilization circuits respectively
associated with the functional blocks coupled to provide block utilization
information of the functional blocks.” Ex. 1001, 9:16–18 (emphasis added).
AMD proposes to construe “block utilization information” to mean
“an amount of block usage over a period of time.” PO Resp. 11–16.
Significantly, AMD’s proposed claim construction would exclude other
information that indicates block usage, including current usage demands or
usage information based on a current task or request for using a block to
execute an instruction or application. See id. at 25 (arguing that Bertin does
not determine “block utilization information” because “Bertin manages
power consumption levels on an instruction-by-instruction basis; that is,
based on a current instruction received by Bertin’s system”). As support,
AMD relies upon a Declaration of Dr. Marc E. Levitt (Ex. 2002) and a
dictionary definition (Ex. 2001, 4). PO Resp. 11–16.
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Having considered the Specification in its entirety, we are not
persuaded by AMD’s arguments and expert testimony that the claim term
“block utilization information” is limited to usage rates—“an amount of
block usage over a period of time”—excluding all other block utilization
information. PO Resp. 25; Ex. 2002 ¶¶ 39–47, 59–60. We agree that the
claim term “block utilization information” may encompass a usage rate,
including a percentage of time that the block was used or the number of
cache accesses that occurred over a period of time. Ex. 1001, 3:12–20.
Nevertheless, nothing in the Specification or claims suggests that the term
“block utilization information” excludes current usage demands of the block
or usage information based on a current task or request for using the block
from an instruction, as alleged by AMD.
In fact, the Specification broadly states that the functional block
“generates information indicating the utilization of the block,” and that the
“utilization information can be generated in a number of ways.” Ex. 1001,
3:12–18 (emphasis added). According to the “Summary of the Invention”
section of the Specification, “utilization information may be kept on a task
basis,” and “[w]hen a functional block is heavily loaded by an application,
the performance level and power consumption of that particular functional
block can be increased.” Id. at 1:65–2:1, 2:17–18 (emphases added). The
Specification further provides a specific example that utilization information
of various functional blocks can be compiled per task, so that when the
operating system switches the processor to executing a task, the power
management controller in conjunction with the operating system sets the
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appropriate power management parameters to correspond to the particular
task. Id. at 6:49–60.
The Specification also sets forth another specific example that a block
utilization information may include a request for using the functional block
from a current instruction—the “floating point [unit] (FPU) utilization may
be determined by detecting when the FPU is requested to perform a floating
point operation.” Id. at 3:22–24. Although this example provides another
alternative to determine FPU utilization, we are not persuaded by AMD’s
argument and expert testimony that, for this example, the number of FPU
requests must be counted over a period of time to determine the FPU
utilization. PO Resp. 13; Ex. 2002 ¶ 45. As the Specification explicitly
states, the “number of FPU requests may be counted over a period of time to
determine utilization.” Ex. 1001, 3:24–26 (emphasis added). We decline to
read “may” as “must” or to ignore the sentence—“floating point [unit]
(FPU) utilization may be determined by detecting when the FPU is requested
to perform a floating point operation” (id. at 3:22–24)—as suggested by
AMD. Accordingly, we are not persuaded that AMD’s proposed claim
construction is consistent with the Specification, or the plain and ordinary
meaning of the claim term as would be understood by an ordinarily skilled
artisan in the context of the Specification.
AMD’s arguments and expert testimony also are predicated on an
overly narrow dictionary definition, which defines the term “utilization” to
mean “a ratio representing the amount of time a system or component is
busy divided by the time it is available.” Ex. 2001, 4; PO Resp. 11–16;
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Ex. 2002 ¶¶ 38, 45. That definition improperly limits the term “utilization”
to a usage rate, and does not take into account the teachings in the
Specification. In fact, the Specification uses the term “utilization” to
describe a usage of a functional block, and not a usage rate. See, e.g.,
Ex. 1001, 3:33–37 (“That detection causes a utilization counter 205 to
increment a count value to indicate that a utilization occurred.”), 5:61–65
(“The cache utilization, i.e. the hit and miss data is determined by utilization
detect circuit 203 . . . .”). Significantly, when the Specification describes a
usage rate, it expressly uses the phrase “a utilization per unit time,” and not
just “utilization” by itself. Id. at 4:32–34 (“[T]he value in the utilization
counter can be divided by the cycle counter to obtain a utilization per unit
time.”). Additionally, AMD’s dictionary definition of the term “utilization”
measures the amount of time when a system or component is busy, whereas,
in several preferred embodiments, the Specification determines block
utilization based on the number of instructions, requests, or utilization
events. Compare Ex. 2001, 1170, with, e.g., Ex. 1001, 3:24–35.
Consequently, AMD’s reliance on a dictionary definition divorced from the
Specification of the ’520 patent is misplaced. Phillips v. AWH Corp., 415
F.3d 1303, 1321 (Fed. Cir. 2005) (en banc) (noting that “heavy reliance on
the dictionary divorced from the intrinsic evidence risks transforming the
meaning of the claim term to the artisan into the meaning of the term in the
abstract, out of its particular context, which is the specification”).
Furthermore, Dr. Levitt’s testimony that “[e]ach of the block
utilization information examples above represents an amount of block usage
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over a period of time,” and that the “specification does not describe ‘block
utilization information’ in any other way” (Ex. 2002 ¶ 39) is not supported
by the Specification. For example, as discussed above, the Specification
provides that block utilization information may be kept on a task basis or
determined by detecting when a block is requested to perform an operation.
Ex. 1001, 1:62–2:1, 2:17–18, 3:22–24, 3:33–37, 4:32–34, 5:44–46, 5:61–65,
6:49–60. Therefore, we give little, if any, weight to AMD’s expert
testimony in that regard. See 37 C.F.R. § 42.65(a).
Moreover, AMD’s arguments and expert testimony also narrowly
focus on several specific examples described in the Specification. PO Resp.
11–16; Ex. 2002 ¶¶ 39–47. Our reviewing court, however, “has repeatedly
cautioned against limiting the claimed invention to preferred embodiments
or specific examples in the specification.” Williamson v. Citrix Online, LLC,
792 F.3d 1339, 1346–47 (Fed. Cir. 2015) (emphasis added). “[I]t is the
claims, not the written description, which define the scope of the patent
right.” Id.; see also Laitram Corp. v. NEC Corp., 163 F.3d 1342, 1347 (Fed.
Cir. 1998) (“[A] court may not import limitations from the written
description into the claims.”). “Even when the specification describes only a
single embodiment, the claims of the patent will not be read restrictively
unless the patentee has demonstrated a clear intention to limit the claim
scope using words or expressions of manifest exclusion or restriction.”
Hill-Rom Servs., Inc. v. Stryker Corp., 755 F.3d 1367, 1372–73 (Fed. Cir.
2014); Gemstar-TV Guide Int’l, Inc. v. Int’l Trade Comm’n, 383 F.3d 1352,
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1366 (Fed. Cir. 2004); In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359,
1369 (Fed. Cir. 2004).
In light of the Specification, we determine that the claim term “block
utilization information” encompasses not only “an amount of block usage
over a period of time,” but also other information that indicates block usage,
including current usage demands of a block or usage information based on a
current task or request for using the block from an instruction or application.
“block utilization level”
Claim 16 recites “the integrated circuit is responsive to the block
utilization information to independently adjust power consumption levels of
the functional blocks to match respective block utilization levels.” Ex. 1001,
9:21–23 (emphasis added). Claim 23 also recites a similar limitation. Id. at
10:11–15.
AMD urges us to construe the claim term “block utilization level” as
“a magnitude or quantity indicative of block utilization information.” PO
Resp. 16–18 (emphasis added); Ex. 2002 ¶¶ 48–50; Ex. 2001, 578. Similar
to its arguments made in connection with the claim term “block utilization
information,” AMD argues that the claim term “block utilization levels”
cannot be based on current usage demands or a request for using a functional
block for executing a current instruction. PO Resp. 25–27.
We likewise decline to adopt AMD’s proposed construction for the
claim term “block utilization levels” for the same reasons that we reject
AMD’s proposed construction for the claim term “block utilization
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information.” We further note that both “block utilization information” and
“block utilization level” are based on the utilization of a functional block,
which includes usage of a functional block for executing a current
instruction. See, e.g., Ex. 1001, 3:22–34, 6:49–60. Moreover, we agree with
LG that the claims do not require that the block utilization level be the same
as the block utilization information or even that one be derived from the
other because the claims merely require that, in response to the block
utilization information, the integrated circuit adjust the power consumption
levels to match the respective block utilization levels. Ex. 1001, 9:20–22;
Reply 5–7; Ex. 1035 ¶¶ 15–17.
As noted by LG, claim 27 recites an “adjusting power” claim element
in greater detail, which reads:
wherein the independently managing power of the respective
block functional blocks to match respective block utilization
levels comprises:
increasing power consumption levels for those functional blocks
with utilization information that indicates increased utilization;
and
decreasing power consumption levels for those functional blocks
with utilization information that indicates decreased utilization.
Ex. 1001, 10:36–44 (emphases added).
Although claim 27 is not challenged by LG in the instant proceeding,
we review the “adjusting power” claim feature in this claim because “claim
terms are normally used consistently throughout the patent, the usage of a
term in one claim can often illuminate the meaning of the same term in other
claims.” Phillips, 415 F.3d at 1314. We note that even claim 27 does not
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require that the “block utilization level” to be the same as the “block
utilization information” or that one be derived from the other.
Accordingly, we construe the claim term “block utilization level” as
“a magnitude or quantity indicative of block utilization,” consistent with the
claim term’s ordinary and customary meaning in the context of the
Specification.
“adjust power consumption levels of the functional blocks to match
respective block utilization levels”
Each of claims 16 and 23 recites “adjust[ing] power consumption
levels of the functional blocks to match respective block utilization levels.”
Ex. 1001, 9:20–23, 10:12–15. AMD proposes to construe this claim
limitation as “adjust[ing] the power consumption of each functional block to
correspond to its respective block utilization level for two or more
operational states of the block.” PO Resp. 18–24 (emphasis added).
We decline to adopt AMD’s proposed claim construction in light of
the Specification. Once again, AMD improperly attempts to import a
limitation—“for two or more operational states of the block”—from a
specific example in the Specification into the claims. See Williamson, 792
F.3d at 1346–47.
There is a “heavy presumption” that a claim term carries its ordinary
and customary meaning. CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d
1359, 1366 (Fed. Cir. 2002). This presumption may be rebutted: (1) when a
patentee sets out a definition and acts as his own lexicographer; or (2) when
the patentee disavows the full scope of a claim term either in the
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specification or during prosecution. Vitronics Corp. v. Conceptronic, Inc.,
90 F.3d 1576, 1582 (Fed. Cir. 1996). “Mere criticism of a particular
embodiment encompassed in the plain meaning of a claim term is not
sufficient to rise to the level of clear disavowal.” Thorner v. Sony Computer
Entm’t Am. LLC, 669 F.3d 1362, 1366–67 (Fed. Cir. 2012); see also Epistar
Corp. v. Int’l Trade Comm’n, 566 F.3d 1321, 1335 (Fed. Cir. 2009) (holding
that even a direct criticism of a particular technique did not rise to the level
of clear disavowal); Spine Solutions, Inc. v. Medtronic Sofamor Danek USA,
Inc., 620 F.3d 1305, 1315 (Fed. Cir. 2010) (explaining that even where a
particular structure makes it “particularly difficult” to obtain certain benefits
of the claimed invention, this does not rise to the level of disavowal of the
structure). “To constitute disclaimer, there must be a clear and unmistakable
disclaimer.” Thorner, 669 F.3d at 1366–67.
Here, nothing in claims 16 and 23 requires the power consumption
level be adjusted “for two or more operational states of the block.”
Ex. 1001, 9:20–23, 10:12–15. AMD does not allege, nor do we discern, that
there is a definition set forth in the Specification of the ’520 patent to give
the claim terms recited in claims 16 and 23 a special meaning.
We also are not persuaded by AMD’s argument and expert testimony
that the ’520 patent disavows adjusting a power consumption level by
turning off or on the functional block to match the block utilization level.
PO Resp. 19; Ex. 2002 ¶ 52. As noted by LG, the Specification of the ’520
patent merely criticizes the prior art for its inability to determine block
utilization level of the individual functional block, not the usage of on-and-
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off power levels. Ex. 1001, 1:34–59 (noting that “current designs generally
do not provide information about utilization of the individual functional
blocks, and power consumption is not tuned to match the loading of the
individual functional blocks.”); Reply 8.
In fact, the Specification discloses a preferred embodiment of turning
off the clocks of a functional block—“If a particular functional unit is
unused or very lightly used, its clocks may even be turned off for a period of
time.” Ex. 1001, 4:12–14 (emphases added). In another preferred
embodiment, the Specification also describes that “the clocks can be turned
off while operations directed to a particular functional unit accumulate,” and
“[o]nce a sufficient number have accumulated, the clocks can be turned back
on and the accumulated operations can be executed in a burst mode, and
then the clocks can be turned off again.” Id. at 7:44–50 (emphases added).
The Specification clearly does not suggest that the patentee intended a
narrower meaning to exclude adjusting a power consumption level by
turning off or on the functional block to match the block utilization level. In
light of the Specification, we do not find that the ’520 patent disavows
turning off or on the block to match the block utilization levels, as alleged by
AMD.
We further are not persuaded by AMD’s argument and expert
testimony that the statement in the Specification—“[i]f a particular
functional unit is unused or very lightly used, its clocks may even be turned
off for a period of time” (id. at 4:12–14, emphases added)—is not related to
the “adjusting power” claim element, but instead only an optional feature
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because it uses the words “may even.” PO Resp. 21–22; Ex. 2001 ¶ 55. In
fact, AMD and its expert testimony acknowledge that “unused or very
lightly used” is a block utilization level, and that turning off the clocks of a
functional block will adjust the power consumption level. PO Resp. 22–23;
Ex. 2001 ¶ 57. Moreover, as discussed above, the Specification explicitly
teaches turning off or on the clocks of the functional unit to match the block
utilization level as one of the preferred embodiments. Ex. 1001, 4:12–14,
7:44–50. We decline to ignore this teaching in the Specification. We also
note that other preferred embodiments include optional wording “may” or
“can” and, therefore, we will not ignore this teaching in the Specification
merely because it includes “may even,” as urged by AMD. PO Resp. 22;
Ex. 2001 ¶ 55.
In addition, we are not persuaded by AMD’s argument and expert
testimony that we should import the limitation “for two or more operational
states of the block” into the claims because the ’520 patent discloses that
power consumption levels can be adjusted to match a wide range of block
utilization levels, ranging from a heavily-loaded block to a lightly-loaded
block or an unused/very lightly loaded block. PO Resp. 19–24; Ex. 2001
¶ 57. “We do not read limitations from the specification into claims; we do
not redefine words,” even when “the only embodiments, or all of the
embodiments, contain a particular limitation.” Thorner, 669 F.3d at 1366.
In light of the Specification and claim language, we note that the “adjusting
power” claim element requires no more than adjusting the power
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consumption level of each functional block to match its respective block
utilization level in response to the block utilization information.
For the foregoing reasons, we decline to adopt AMD’s proposed
claim construction. Rather, we construe the aforementioned “adjusting
power” limitation as “adjusting the power consumption of each functional
block to correspond to its respective block utilization level” consistent with
the claim term’s ordinary and customary meaning in the context of the
Specification.
B. Principles of Law
To establish anticipation, each and every element in a claim, arranged
as recited in the claim, must be found in a single prior art reference. Net
MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008).
While the elements must be arranged or combined in the same way as in the
claim, “the reference need not satisfy an ipsissimis verbis test,” i.e., identity
of terminology is not required. In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir.
2009). “A reference anticipates a claim if it discloses the claimed invention
such that a skilled artisan could take its teachings in combination with his
own knowledge of the particular art and be in possession of the invention.”
In re Graves, 69 F.3d 1147, 1152 (Fed. Cir. 1995). Moreover, “it is proper
to take into account not only specific teachings of the reference but also the
inferences which one skilled in the art would reasonably be expected to draw
therefrom.” In re Preda, 401 F.2d 825, 826 (CCPA 1968).
A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
differences between the claimed subject matter and the prior art are such that
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the subject matter, as a whole, would have been obvious at the time the
invention was made to a person having ordinary skill in the art to which said
subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
(2007). The question of obviousness is resolved on the basis of underlying
factual determinations including: (1) the scope and content of the prior art;
(2) any differences between the claimed subject matter and the prior art;
(3) the level of ordinary skill in the art; and (4) objective evidence of
nonobviousness. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
An obviousness analysis “need not seek out precise teachings directed
to the specific subject matter of the challenged claim, for a court can take
account of the inferences and creative steps that a person of ordinary skill in
the art would employ.” KSR, 550 U.S. at 418. Here, the level of ordinary
skill in the art is reflected by the prior art of record. See Okajima v.
Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001); In re GPAC Inc.,
57 F.3d 1573, 1579 (Fed. Cir. 1995).
C. Anticipation by Bertin
LG asserts that claims 16–18 and 20 are unpatentable under 35 U.S.C.
§ 102(e) as anticipated by Bertin. Pet. 10–19. In support of its contentions,
LG provides detailed explanations as to how Bertin describes each claim
limitation. Id. LG also relies upon a Declaration of Dr. Min. Ex. 1002.
AMD counters that Bertin does not describe certain claim limitations.
PO Resp. 24–40. In particular, AMD argues that Bertin does not describe
“block utilization information,” “block utilization levels,” and “adjust[ing]
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power consumption levels of the functional blocks to match respective block
utilization levels,” as recited by claim 16. Id. AMD also argues that Bertin
does not describe “the power consumption levels of the functional blocks are
determined at least in part by independent adjustable clock frequencies of
respective clocks being supplied to the functional blocks,” as recited in
claim 17. Id. As support, AMD directs our attention to a Declaration of
Dr. Levitt. Ex. 2002.
We begin our discussion with a brief summary of Bertin, and then we
address the parties’ contentions.
Bertin
Bertin describes a system for optimizing the performance and power
consumption of an integrated circuit that has a plurality of functional units.
Ex. 1003, 1:57–2:27. Each functional unit can be operated at one of a
plurality of power levels—e.g., a high power state, lower power state, and
lowest power state. Id. at 2:28–43, 3:28–37. For example, when executing
an application program that involves a remote file transfer, but no floating
point operations, the performance and power consumption can be optimized
by decreasing the power level of the floating point arithmetic functional unit
to a minimum, and increasing the power level of the modem-related units.
Id. at 2:12–42.
Figure 1A of Bertin illustrates an exemplary integrated circuit, and is
reproduced below.
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As shown in Figure 1A of Bertin, integrated circuit chip 100 includes:
(1) CPU 20, which has intelligent power management control 10, (2) power
management unit 30, which sets the power levels for functional units 1–N
and responds to commands from CPU 20; and (3) a plurality of functional
units 1–N, which perform different functions and are capable of operating at
different threshold voltages. Id. at 4:44–49. Intelligent power control 10
monitors the instruction stream for an indication of what functions need to
be performed, and creates commands to adjust power consumption of the
various functional units to optimize operations and power consumption. Id.
at 5:13–19. The power consumption levels of the functional units are
controlled to optimize operation of the chip as a whole. Id. at 4:51–5:12.
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Figure 1B of Bertin, reproduced below, illustrates an exemplary
intelligent power management control.

As shown in Figure 1B of Bertin, intelligent power management control 10
includes a requirement table and status table that: (1) identify which
functional unit is required to execute an instruction, and (2) reflects the
present power status of each functional unit. Id. at 5:23–29. Using the
utilization information, logic 208 determines whether the power requirement
and power status for each functional unit are in agreement. Id. at 5:32–37.
In the event that a power adjustment is necessary, execution unit 207 either
reduces the process clock or adjusts the performance level of the particular
functional unit. Id. at 5:45–50.
Adjusting power consumption levels
Claim 16 recites “wherein the integrated circuit is responsive to the
block utilization information to independently adjust power consumption
levels of the functional blocks to match respective block utilization levels.”
Ex. 1001, 9:20–23 (emphases added).
LG takes the position that Bertin describes all of the limitations of
claim 16 including the aforementioned “adjusting power” limitation.
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Pet. 10–15. Specifically, LG asserts that Bertin discloses the “block
utilization information” and “block utilization levels” claim features because
Bertin’s logic element of the intelligent power management control receives
utilization information regarding each instruction that needs to be executed–
–namely, signals from a requirements table and status table that identify:
(1) which functional unit is required to execute the instruction, and (2) the
present power status of each functional unit. Id. at 10, 12–13 (citing
Ex. 1003, 2:53–3:2, 5:23–29, 6:41–57). LG further points out that, in
response to the inputs from the requirement and status tables, Bertin’s logic
element determines whether the power consumption level for each
functional unit needs to be adjusted to match the utilization level for
executing the instruction. Id. at 13–14 (citing Ex. 1003, 3:61–63, 5:23–50,
6:41–57, Figs 1B, 3).
AMD counters that Bertin does not disclose the aforementioned
“adjusting power” claim limitation. PO Resp. 25–32. In particular, AMD
argues that Bertin does not disclose “block utilization information” because
Bertin does not determine an amount of block usage over a period of time, as
required by AMD’s proposed claim construction. Id. AMD also alleges that
Bertin does not disclose “block utilization level” because, under AMD’s
proposed claim construction, the claim term “block utilization level” means
“a magnitude or quantity indicative of block utilization information,” and the
claim term “block utilization information” means an “amount of block usage
over a period of time.” Id. AMD further contends that Bertin manages
power consumption levels on an instruction-by-instruction bases, adjusting
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power consumption levels based on a current instruction received by the
system. Id. As support, AMD directs our attention to Dr. Levitt’s
testimony. Ex. 2002 ¶¶ 59, 61–74.
AMD’s argument and expert testimony, however, are predicated on
AMD’s proposed claim constructions. PO Resp. 25–32; Ex. 2002 ¶¶ 59, 61–
74. As we discuss above in the claim construction section of this Decision,
we decline to adopt those proposed constructions. Rather, in light of the
Specification including the claims, we construe the claim term “block
utilization information” to encompass information that indicates block
usage, including current usage demands or usage information based on
a current task or request for using a block to execute an instruction or
application. And we construe the claim term “block utilization level” as
“a magnitude or quantity indicative of block utilization.” Applying the
proper claim constructions, we determine that LG has demonstrated
sufficiently that Bertin describes every claim limitation of claim 16,
including the “block utilization information,” “block utilization levels” and
“adjusting power” claim limitations.
As LG points out in its Petition (Pet. 10–15), Bertin’s power
management system includes a logic element that receives utilization
information of each functional block within an integrated circuit. Ex. 1003,
6:41–57. Specifically, Bertin discloses that the CPU on the integrated circuit
chip includes an intelligent power management control that monitors the
instruction stream for an indication of what functions need to be performed
and what instructions are to be executed and creates commands to adjust
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power consumption of the various functional units to optimize operations.
Id. at 5:7–19. Each functional unit on an integrated circuit chip is optimized
to operate at one of a plurality of power levels based on the demands placed
on the integrated circuit chip. Id. at 1:63–2:11. For example, when
executing an application program that involves a remote file transfer, but no
floating point operations, the performance and power consumption can be
optimized by decreasing the power level of the floating point arithmetic
functional unit to a minimum, and increasing the power level of the
modem-related functional units to a high power state. Id. at 2:12–42.
Additionally, the intelligent power management control includes two
tables: a requirements table and a status table. Id. at 5:23–24. The
requirements table identifies, for each instruction, which functional units are
required to execute the instruction. Id. at 5:24–27. The requirement table
indicates whether a high power state is required for the functional unit to
execute the instruction. Id. at 6:7–13. The status table reflects the present
power status of each functional unit on the chip. Id. at 5:27–29. The
corresponding outputs of the requirements table and status table are
combined in a logic within the intelligent power management control. Id. at
5:32–34. The logic comprises a number of logic elements, one logic
element per functional unit on the chip. Id. at 6:41–42. The logic element
for each functional unit determines whether the power requirement and
power status for the functional unit are in agreement. Id. at 5:34–37. The
logic element will indicate to the power management unit whether the
functional unit should be at a higher power state or at a lower power state,
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and the power management unit will adjust the power consumption level of
the functional unit to match the utilization level. Id. at 6:47–57.
Based on the evidence in this record, we are persuaded that LG has
shown that Bertin describes all of the limitations of claim 16, including the
“adjusting power” limitation—an “integrated circuit is responsive to the
block utilization information to independently adjust power consumption
levels of the functional blocks to match respective block utilization levels.”
Adjusting clock frequencies being supplied to the functional blocks
Claim 17 depends from claim 16, and further recites “wherein at the
power consumption levels of the functional blocks are determined at least in
part by independently adjustable clock frequencies of respective clocks
being supplied to the functional blocks.” Ex. 1001, 9:24–28 (emphases
added). In this regard, the parties’ dispute centers on whether Bertin’s
power management system adjusts the clock frequency being supplied to a
functional block. Pet. 11, 15–17; PO Resp. 32–40. LG asserts that Bertin
discloses the limitation recited in claim 17 because Bertin discloses that the
clock frequency being supplied to the functional unit can be manipulated
using a clock delay to reduce the frequency “in the event the functional unit
is not at the appropriate higher powered operating condition.” Pet. 11, 15–
17 (citing Ex. 1003, Abs., 3:15–17, 4:44–49, 5:7–12, 5:44–49, 8:44–9:12;
Ex. 1002 ¶¶ 110, 111, 146). AMD counters that Bertin’s clock delay
element provides an input to a clock gating function when presenting a clock
signal to the functional unit, but it does not change the frequency of the
clock signal. PO Resp. 32–40.
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Based on the evidence before us, we do not agree with AMD’s
position. Rather, we are persuaded by LG’s showing that Bertin’s intelligent
power management control adjusts the clock frequency being supplied to a
functional block, as required by claim 17.
As discussed above, Bertin’s intelligent power management control
monitors the instruction stream and, in response to the utilization
information, creates commands to adjust the power consumption levels of
the functional blocks, if needed, to match the block utilization levels.
Ex. 1003, 3:61–63, 5:23–50, 6:41–57, Figs. 1B, 3. If power adjustment is
needed, the execution unit of the intelligent power management control can
either reduce the process clock or adjust the performance level of the
particular functional unit. Id. at 5:46–50. Similar to the ’520 patent
(Ex. 1001, 7:16–20), Bertin recognizes that functional units are capable of
operating at different threshold voltages: a higher threshold voltage
represents a lower power consumption, but at a slower speed of operation,
and; a lower threshold voltage represents a higher power consumption, but
higher operating speed. Ex. 1003, 4:44–49.
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Figure 6A of Bertin illustrates the execute unit for each functional
unit, and is reproduced below with yellow highlights added:

As shown in Figure 6A of Bertin, each of execute units 207A–1, 207A–2,
207A–3 includes AND gate 20M, delay 20L (highlighted in yellow), OR
gate 20N, clock CLK (highlighted in yellow), and AND gate 20K.
Ex. 1003, 8:44–9:12. When a functional unit is required for executing an
instruction and that unit is in a higher powered state, OR gate 20N will be
enabled so that AND gate 20K will pass clock pulses (highlighted in yellow)
to the functional unit to enable normal operation. Id. On the other hand, if a
functional unit is required for executing an instruction, but that unit is not in
a higher powered state, AND gate 20M will be enabled, asserting an input to
delay 20L. Id. After an appropriate time, the output of delay 20L will be
asserted, and output of OR gate 20N will go high, enabling clock pulses
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(highlighted in yellow) to the functional unit. Id. Thus, the process clock to
the functional unit will be delayed. Id.
LG’s expert, Dr. Min, explains that the clock signal is delayed, thus
“effectively reducing the frequency of that unit because the number of clock
pulses over the same period is reduced.” Ex. 1002 ¶ 111. Dr. Min also
testifies that “a delayed clock signal would effectively reduce the clock
frequency of the functional block to which it was delivered” because a
“functional block receiving a delayed clock signal would encounter a lower
number of clock pulses over a particular amount of time.” Id. at ¶ 146.
Dr. Min’s testimony in that regard is consistent with the general
understanding of an ordinarily skilled artisan in the context of the ’520
patent. See THE AUTHORITATIVE DICTIONARY OF IEEE STANDARDS TERMS,
(7th ed. 2000) (defining the term “frequency” as “the number of periods per
unit time” (general) or “the number of periods, or specified fraction of
periods, per unit time” (automatic control)) (Ex. 3001, 3, “IEEE Standard
Dictionary”)5; Ex. 1001, 5:22–26; 6:20–23.
In support of AMD’s arguments, Dr. Levitt testifies that “Bertin
merely discloses the same clock, at the same frequency, but arriving at the
functional block some period of time later than it otherwise would.”
Ex. 2002 ¶ 75 (emphasis in the original). According to Dr. Levitt, the

5 This is the same dictionary used by AMD (see Ex. 2001, IEEE STANDARD
DICTIONARY (6th ed. 1996)), except the 7th Edition of IEEE STANDARD
DICTIONARY (2000) has a date that is closer to the filing date of the ’520
patent, March 2, 2001.
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functional unit effectively has no clock during this period of time. Id.
Dr. Levitt testifies that the delay element “simply provides an input to a
clock gating function when presenting clock signal CLK to the functional
unit,” and that “it does not change the frequency of clock signal CLK nor the
derived output clock from AND gate 20K for register 151, e.g., the gated
clock.” Id. at ¶ 76. Dr. Levitt maintains that adjusting clock frequency is
different from clock gating. Id. at ¶¶ 78–79.
Figure 4 from Dr. Levitt’s Declaration (id. at ¶ 80) illustrates an
example of the clock signals at the input and output of AND gate 20K of
Bertin, and is reproduced below with a yellow highlight added.

As shown in Dr. Levitt’s Figure 4 above, Dr. Levitt defines the term “clock
frequency” as “the inverse of the clock period (f = 1 / T).” Id. According to
Dr. Levitt, the difference between the two clock signals is a “missing” clock
pulse at the beginning of the clock signal at the output of AND gate 20K
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(highlighted in yellow), but both waveforms have the same clock frequency.
Id.
Dr. Levitt’s analysis, however, is predicated on the notion that the
frequency must be adjusted at the clock, which is not consistent with the
claim language “adjusting the clock frequency being supplied to the
functional clocks,” as recited in claim 17, and the Specification of the ’520
patent. See, e.g., Ex. 1001, 5:22–26; 9:26–28. As the Specification
explains, power management “parameters can be adjusted by software
writing to a clock control register to control the clock frequency being
supplied to the functional unit in a manner known in the art.” Id. at 5:22–25
(emphasis added). The Specification suggests that adjusting the frequency at
the clock is only one example known in the art for adjusting the clock
frequency being supplied to the functional unit. Id. at 5:25–26. In fact,
Dr. Levitt acknowledges that there are a number of methods for achieving a
power saving within a functional block and that clock gating is a known
method of reducing power consumption. Ex. 2002 ¶ 78 (citing Ex. 1004,
10:62–11:2). Moreover, the Specification discloses a preferred embodiment
that uses clock gating. Ex. 1001, 6:20–23 (“The feedback in the illustrated
embodiment is accomplished ANDing together clock signal 409 and the
output from XOR gate 407 to provide a gated clock signal 410 to the
counter.” (emphasis added)).
Additionally, Dr. Levitt’s definition of the term “frequency” is not
consistent with the general understanding of an ordinarily skilled artisan in
the context of the ’520 patent Specification. See Ex. 3001, 3; Ex. 1001,
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5:22–26; 6:20–23. As Dr. Min testifies, clock gating “will necessarily
reduce the frequency of the clock signal.” Ex. 1035 ¶¶ 56–62. Citing to
Huang6 as support, Dr. Min explains that “gating of particular pulses reduces
the overall number of pulses per unit time, thus reducing the frequency.” Id.
at ¶¶ 59–60 (citing Ex. 1031, 1:66–2:10). Indeed, Huang teaches that “[t]he
gating circuit responses to the throttling signal to gate out some clock cycles
of an integrated circuit the digital clock throttling means implants in,
therefore, changing the frequency of the clock signal as well as controlling
the power consumption and thermal production.” Ex. 1031, 1:66–2:10
(emphasis added). We agree with Dr. Min that the definition of the term
“clock frequency” is not limited to only “the inverse of the clock period
(f = 1 / T),” as asserted by Dr. Levitt, but rather encompasses “a number of
occurrences per unit time,” consistent with the general understanding of an
ordinarily skilled artisan in the context of the claim language and
Specification of the ’520 patent. Ex. 1035 ¶ 58; Ex. 3001, 3. Applying Dr.
Min’s definition to Dr. Levitt’s Figure 4 (reproduced above), the clock
signal at the input of AND gate 20K has 4 pulses, whereas the output clock
signal to the functional unit has 3 pulses over the same time period, and,
consequently, the clock frequency being supplied to the functional block is
reduced. See Ex. 1002 ¶ 111, 146; Ex. 1035 ¶¶ 56–62.
Based on the evidence before us, we credit the testimony of Dr. Min
(Ex. 1002 ¶¶ 111, 146; Ex. 1035 ¶¶ 56–62) over that of Dr. Levitt (Ex. 2002

6 U.S. Patent No. 6,407,595, issued on June 18, 2002. Ex. 1031 (“Huang”).
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¶¶ 75–84). See Yorkey v. Diab, 601 F.3d 1279, 1284 (Fed. Cir. 2010)
(holding that Board has discretion to give more weight to one item of
evidence over another “unless no reasonable trier of fact could have done
so”). We find Dr. Min’s testimony in that regard to be more consistent with
the prior art of record, claim language, and Specification of the ’520 patent.
See, e.g., Ex. 1001, 5:22–26; 6:20–23; Ex. 1003, 8:44–9:12; Ex. 1031, 1:66–
2:10; Ex. 3001, 3.
For the foregoing reasons, we are persuaded that LG has demonstrated
sufficiently that Bertin describes the limitation “the power consumption
levels of the functional blocks are determined at least in part by
independently adjustable clock frequencies of respective clocks being
supplied to the functional blocks,” as recited in claim 17.
Conclusion on anticipation based on Bertin
AMD presents no arguments regarding the additional limitations
recited in dependent claims 18 and 20. PO Resp. 40. Having considered
LG’s analysis and supporting evidence, we agree with LG’s showing and
adopt it as our own that Bertin describes the claimed features recited in
claims 18 and 20. See, e.g., Pet. 10–19; Ex. 1003, Abs., 1:65–2:11 (“[T]he
integrated circuit is designed with discrete functional units . . . where each of
the functional units has an independently controllable body voltage or
threshold voltage.”), 3:19–22, 4:44–49, 5:7–37, 6:24–28, 9:50–51, Figs. 4A,
4B; Ex. 1002 ¶¶ 106–09, 148–49. For the foregoing reasons, we determine
that LG has demonstrated by a preponderance of the evidence that
claims 16–18 and 20 are unpatentable as anticipated by Bertin.
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D. Obviousness over Bertin
LG asserts that claims 21–23 are unpatentable under § 103(a) as
obvious over Bertin standing alone. Pet. 19–27. Claims 21–23 additionally
require that the utilization circuits are software accessible and/or the
integrated circuit allows software to control the power consumption levels of
the functional blocks.
In support of this asserted ground, LG provides detailed explanations
as to how the combination of Bertin’s technical features meets each claim
limitation. Id. For instance, LG notes that Bertin’s utilization circuits
measure the utilization of each functional block, and in response to the
detected utilization, Bertin’s logic controls the power consumption of the
functional block to match the utilization level. Id. at 20 (citing Ex. 1003,
2:53–3:2, 5:23–36, 6:41–57). LG further points out that Bertin discloses that
“application software” can control and access an override register which sets
a maximum speed for the processor. Id. at 19 (citing Ex. 1003, 7:8–16). LG
contends that, because the power management features are accessible by
software, one with ordinary skill in the art would have understood Bertin’s
system to be operating in a computer system. Id. at 20. LG also alleges that,
to the extent that Bertin does not disclose software access to utilization
circuits, it would have been obvious to combine Bertin’s disclosure of
software control of power management and its disclosure of utilization
circuits so that its utilization circuits can be accessible to software. Id. LG
further maintains that such a solution would not require hardware
replacement and it would be more flexible and durable. Id.
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As to claims 21 and 22, which depend from claim 16, AMD contends
that Bertin does not disclose the elements of claim 16. PO Resp. 40. AMD
makes no arguments regarding the additional limitations recited in claims 21
and 22. Id. With respect to claim 23, AMD argues that Bertin does not
disclose “block utilization information,” “block utilization levels,” or
“adjusting power” claim limitations, which are similarly recited in claim 16.
Id. Essentially, for claims 21–23, AMD relies on the same arguments
presented in connection with claim 16. Id. We have addressed those
arguments in our anticipation analysis above as to claims 16–18 and 20, and
conclude that those argument are likewise unavailing here.
Citing to its expert testimony for support, AMD also argues that
software access to Bertin’s utilization circuits would impede Bertin’s goal of
real-time processing of instructions because the software access would
consume additional clock cycles and require using of additional processor
registers. Id. at 40–43; Ex. 2002 ¶¶ 88–91.
Based on the evidence before us, we are not persuaded by AMD’s
argument and expert testimony. As explained in the Petition, LG relies upon
the combination of Bertin’s software disclosure with Bertin’s utilization
circuit disclosure to teach or suggest accessing the utilization circuits
through software, and allowing software to control the power consumption
of the functional unit. Pet. 19–27. Dr. Min testifies that, because Bertin’s
override register is part of the intelligent power management control and it is
accessible, programmable, and controllable by software, it would have been
obvious to introduce Bertin’s software accessibility to other areas of Bertin’s
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power management control system, including the utilization circuits.
Ex. 1002 ¶ 154 (citing Ex. 1003, 7:8–16). Dr. Min further testifies that one
with ordinary skill in the art would have recognized the advantage of
combining Bertin’s circuit with software that controls and adjusts its power
consumption level so that it would not require hardware replacement and it
would be more flexible and durable. Id. ¶ 155.
Although implementing software access and control in Bertin’s
system may increase some processing burden, such disadvantages are not
dispositive of non-obviousness, especially in view of the advantages as
articulated by Dr. Min. See Medichem, S.A. v. Rolabo, S.L., 437 F.3d 1157,
1165 (Fed. Cir. 2006) (“[G]iven course of action often has simultaneous
advantages and disadvantages, and this does not necessarily obviate
motivation to combine.”); see also Winner Int’l Royalty Corp. v. Wang, 202
F.3d 1340, 1349 n.8 (Fed. Cir. 2000) (“The fact that the motivating benefit
comes at the expense of another benefit, however, should not nullify its use
as a basis to modify the disclosure of one reference with the teachings of
another. Instead, the benefits, both lost and gained, should be weighed
against one another.”).
As Dr. Min explains, the amount of resources necessary to monitor
Bertin’s status signal SVT and utilization information RVT data fields and
adjust voltage, if necessary, is extremely small because the processing
burden of adjusting Bertin’s system can be configured as needed. Ex. 1035
¶¶ 68–70. Indeed, Bertin discloses that once a functional unit has been
raised to a higher performance level, the unit will remain at the level for a
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selected period and then, in the absence of further instruction which require
high performance from the unit, the performance level of the unit will be
returned to a lower power state. Ex. 1003, 4:65–5:6. Moreover, Dr. Min
testifies that registers can be defined by application software, without being
limited by the physical quantity defined by the processor architecture, and
that “one of ordinary skill in the art would have been easily able to
implement such features in a way to make them software accessible.”
Ex. 1035 ¶ 69. Therefore, we agree with Dr. Min that the processing burden
would be minimized and would not discourage a relevant artisan from
adding software access and control to Bertin’s system. Id. at ¶ 67. We give
Dr. Min’s testimony substantial weight in that regard as it is supported by
the disclosures of Bertin. See, e.g., Ex. 1003, 2:53–3:2, 4:65–5:6, 5:23–36,
6:41–57, 7:8–16.
Given the evidence before us, we determine that LG has articulated a
sufficient rationale to combine Bertin’s software disclosure and Bertin’s
utilization circuit disclosure, implementing software accessibility and
control to other portions of Bertin’s power management control system,
allowing quicker and more efficient updates. See KSR, 550 U.S. at 417
(“[I]f a technique has been used to improve one device, and a person of
ordinary skill in the art would recognize that it would improve similar
devices in the same way, using the technique is obvious unless its actual
application is beyond his or her skill.”). For the foregoing reasons, we
determine that LG has demonstrated by the preponderance of the evidence
that claims 21–23 are unpatentable as obvious over Bertin.
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E. Anticipation by Gunther
LG asserts that claims 16–18 and 20 are unpatentable under § 102(b)
as anticipated by Gunther. Pet. 27–36. AMD counters that Gunther does
not disclose certain claim limitations. PO Resp. 43–52. We begin our
discussion with a brief summary of Gunther, and then we address the
parties’ contentions.
Gunther
Gunther discloses a method and apparatus for dynamically adjusting
the power consumption of circuit blocks within an integrated circuit.
Ex. 1004, Abstract. In particular, Gunther discloses an integrated circuit that
includes a plurality of circuit blocks. Id. at 4:49–54, 6:29–64. Gunther’s
system powers a circuit block down when it is anticipated that the circuit
block will not be required to function in the near future, or powers the circuit
block up when it is anticipated that the block will be required to function in
the near future. Id. at 4:63–5:1.
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Figure 3 of Gunther is reproduced below.

As shown in Figure 3 of Gunther, bus interface unit 32—one of the circuit
blocks—has associated power control circuit 60 that includes circuit block
activity monitoring logic 62, for monitoring activity of the block, and
provides block utilization information. Id. at 6:65–7:6. The power
consumption level of each block is adjusted dynamically based on the
utilization information. Id. at 9:34–10:22.
Adjusting power consumption levels
LG relies upon Gunther to describe all of the limitations of claim 16,
including the limitation for adjusting power consumption levels of the
functional blocks of an integrated circuit to match respective block
utilization levels. Pet. 27–32. According to LG, each of Gunther’s circuit
blocks has a block activity monitoring logic for providing utilization
information, and Gunther’s power control circuit places the block in a
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powered-up state (for a highly utilized circuit block) or a powered-down
state (for a less utilized circuit block) to match the block utilization level.
Id.
AMD counters that Gunther does not disclose adjusting “power
consumption levels of the functional blocks to match respective block
utilization levels for two or more operational states of the block.” PO Resp.
44–50 (emphasis added). In particular, citing to its expert testimony for
support, AMD argues that Gunther’s power management system has only
one operational state, turning on and off the functional blocks as necessary to
accommodate inactivity or data flow. Id. According to AMD, Gunther only
toggles the power consumption levels between two states: (1) a non-
operational, powered down state, and (2) an operational, powered up state.
Id.; Ex. 2002 ¶¶ 93–103. AMD also alleges that Gunther does not adjust the
power consumption level of a functional block to match its own block
utilization level. PO Resp. 48–50.
AMD’s arguments and expert testimony, however, are not
commensurate with the scope of the claims, predicated on AMD’s proposed
claim construction that requires adjusting the power consumption level of
each functional block to match the respective block utilization level for two
or more operational states of the block. PO Resp. 44–50; Ex. 2002 ¶¶ 93–
103. As we discussed previously in the claim construction section of this
Decision, we decline to adopt AMD’s proposed claim construction, as it
would import a limitation—“for two or more operational states of the
block”—from the Specification into the claims. Applying the proper claim
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construction, we are persuaded that LG has demonstrated sufficiently that
Gunther describes the “adjusting power” limitation recited in claim 16.
As LG points out in its Petition (Pet. 27–33, 56–60), Gunther
discloses an integrated circuit capable of adjusting dynamically the power
consumption of multiple functional blocks within the integrated circuit.
Ex. 1004, Abs., 1:7–11, 3:29–32, 4:49–53, Fig. 2. The power control circuit
that is associated with each block measures the utilization of the block. Id.
at 7:30–39, 12:4–40. The power control circuit uses the block utilization
information to adjust the power consumption level of each block to match
the block utilization level. Id. at 1:9–11, 4:63–5:1, 5:29–39, 7:23–67. More
specifically, Gunther describes reducing the clock frequencies being
supplied to the functional blocks for matching the power consumption levels
to the respective block utilization levels. Id. at 10:62–11:8 (“For example,
the frequency of the clock signal to the circuit block could be reduced.”).
We also are not persuaded by AMD’s argument and expert testimony
that Gunther does not adjust the power consumption level of a functional
block to match the respective block utilization level. PO Resp. 48–50.
AMD’s argument and expert testimony narrowly focus on only one of
Gunther’s embodiments, and do not consider the portions or embodiments of
Gunther that are relied upon by LG. Id.; Ex. 2002 ¶¶ 99–103; Pet. 32–33
(citing Ex. 1004, 1:9–11, 4:63–5:1, 5:29–39, 9:32–62, 10:56–61). Notably,
as LG notes in its Petition, Gunther explicitly discloses that its system
“allows a circuit block to be powered down when it is speculatively
anticipated that the relevant circuit block will not be required to function in
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the near future, or to be powered up when it is speculatively anticipated that
the relevant circuit block will be required to function in the near future.”
Pet. 32–33; Ex. 1004, 4:63–5:1. As such, we determine that LG has
established adequately that Gunther adjusts the power consumption level of
a functional block to match the respective block utilization level.
Based on the evidence in this record, we determine that LG has shown
sufficiently that Gunther describes all of the limitations of claim 16,
including the “adjusting power” limitation.
Adjustable clock frequencies and controllable voltages
Claim 17 depends from claim 16, and further recites “wherein at the
power consumption levels of the functional blocks are determined at least in
part by independently adjustable clock frequencies of respective clocks
being supplied to the functional blocks.” Ex. 1001, 9:24–28 (emphasis
added). Claim 18 depends from claim 17, and further recites “wherein the
power consumption levels of the functional blocks are determined at least in
part according to independently controllable voltages being supplied to
respective ones of the functional blocks.” Id. at 9:29–33 (emphasis added).
In that regard, the parties’ dispute centers on whether Gunther describes the
limitations required by claim 18.
LG alleges that Gunther describes these limitations because “Gunther
discloses that the power consumption levels of the circuit blocks can be
controlled by adjusting clock frequencies and/or operating supply voltage.”
Pet. 28; Ex. 1002 ¶¶ 116, 166 (citing Ex. 1004, 5:47–54, 7:45–52, 10:62–
11:8). AMD opposes, arguing that Gunther does not disclose a power
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control circuit having both controllable voltages and adjustable clock
frequencies, as required by claim 18. PO Resp. 50–52.
Upon review of the evidence before us, we agree with AMD’s
position. By virtue of its dependency from claims 16 and 17, claim 18
requires both “independently controllable voltages” and “independently
adjustable clock frequencies of respective clocks.” Ex. 1001, 9:29–33.
As AMD notes, Gunther discloses a power control circuit that has either
removable voltages or adjustable block frequencies, but not both, for
adjusting the power consumption level of a functional block to match the
block utilization level in response to the block utilization information.
Ex. 1004, 10:62–11:8.
In its Reply, LG argues that Gunther does not support AMD’s position
that the voltage reduction and clock control operations of Gunther are
intended to be exclusive alternatives. Reply 20–22. LG also contends that
claim 18 only requires a circuit that is capable of modifying voltage and
capable of modifying clock speed, not that it performs both methods
simultaneously. Id. As support, LG directs our attention to portions of
Gunther (Ex. 1004, 5:54–61, 10:62–11:8), Dr. Min’s Second Declaration
(Ex. 1035 ¶¶ 80–87), and Dr. Levitt’s cross-examination testimony
(Ex. 1034, 85:11–24).
We are not persuaded by LG’s arguments and supporting evidence.
LG fails to show that Gunther describes a power control circuit having both
controllable voltages and adjustable clock frequencies, as required by
claim 18. Even the portions of Gunther relied upon by LG and its expert
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testimony do not contain such a disclosure. See Ex. 1004, 5:54–61, 10:62–
11:8. In fact, these portions of Gunther make clear that reducing the clock
frequency and removing the operating supply voltage are alternative
methods:
It should furthermore be noted that, while gating a clock signal
to a circuit block provides one method of powering down the
relevant circuit block, the invention is not limited to this method.
For example, it is possible to shut off each circuit block’s clock
or to perform other powering down operations unique to the
circuit block to achieve the power down state. Examples of such
further techniques will be discussed below.
Id. at 5:54–61 (emphases added by LG).
While the above discussions have related primarily to gating a
dedicated clock signal as a method of reducing power
consumption within a circuit block, it will be appreciated by
those skilled in the art that any one of a number of alternative
measures could be implemented to achieve a power savings
within the relevant circuit block. For example, the frequency of
the clock signal to the circuit block could be reduced.
Alternatively, the operating supply voltage could be removed
from the circuit block, or input and output signals (other than the
clock signal) from the circuit block could be prevented from
transitioning (or toggling). In another embodiment, the output
load of the circuit block could be decoupled to achieve a
reduction in power consumption.
Id. at 10:62–11:8 (emphases added).
Merely disclosing alternative methods does not necessarily describe a
single power control circuit having both controllable voltage and adjustable
clock frequencies. More importantly, LG has not shown sufficiently that
these alternative methods are performed by a single integrated circuit for
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adjusting power consumption level of a functional block to match the block
utilization level in response to the block utilization information. Pet. 28–29,
34–35; Reply 20–22. Nor does LG demonstrate adequately that the
necessary structural features for performing these alternative methods are
implemented in a single integrated circuit. See Net MoneyIN, 545 F.3d at
1371.
The cited portions of Gunther also do not support Dr. Min’s testimony
that “Gunther makes clear that a single circuit may have the structural
features necessary to utilize different mechanisms to control power
consumption.” Ex. 1035 ¶ 84. Nothing in Gunther describes a single circuit
having the necessary structural features to utilize both modifying the clock
frequency and modifying the voltage for adjusting the power consumption
level. See, e.g., Ex. 1004, 10:62–11:8. Dr. Min also does not explain
sufficiently why one of ordinary skill in the art would have understood that
“even if none of the above control mechanisms are applied to a particular
functional unit at any given time, the disclosed system has the structural
capacity to utilize either mechanism.” Ex. 1035 ¶ 85 (emphasis added);
Ex. 1002 ¶¶ 116, 166. Dr. Min’s testimony (Ex. 1002 ¶¶ 116, 166; Ex. 1035
¶¶ 80–85) in that regard is conclusory and thus, is entitled little, if any,
weight. See Rohm and Hass Co. v. Brotech Corp., 127 F.3d 1089, 1092
(Fed. Cir. 1997) (“Nothing in the rules or in our jurisprudence requires the
fact finder to credit the unsupported assertions of an expert witness.”).
LG also argues that Dr. Levitt, during cross-examination, admitted
that one of ordinary skill in the art would have understood that “even if none
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of the above control mechanisms are applied to a particular functional unit at
any given time, each functional unit has the structural capacity to utilize
both mechanisms.” Reply 21–22 (emphases in the original). We do not
agree with LG’s characterization of Dr. Levitt’s cross-examination
testimony. The portions of Dr. Levitt’s cross-examination testimony cited
by LG is reproduced below:
Q. So, for example, a given circuit block might be
capable of having its voltage reduced or its clock frequency
reduced, but Gunther doesn’t teach doing both of those at the
same time, correct?
A. That is correct, based on his statement there. He says,
you know, one way to implement the lower power state, the
power down state, which was shown was equivalent to clock
gating based on the cache and the figures is, you know, you can
do clock gating or you could do removing the operating supply
voltage from the circuit block or you could, you know, freeze the
input signals type of situation.
Ex. 1034, 85:11–24 (emphases added).
Dr. Levitt merely agreed that the power may be adjusted by gating the
clock or removing the operating supply voltage. As discussed above, merely
disclosing alternative methods does not necessarily describe an integrated
circuit having both controllable voltage and adjustable clock frequencies for
adjusting the power consumption level of each functional block to match the
block utilization level in response to the block utilization information, as
required by claim 18.
For the foregoing reasons, we determine that LG fails to demonstrate
by a preponderance of the evidence that Gunther anticipates claim 18.
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Conclusion on anticipation based on Gunther
With respect to dependent claims 17 and 20, AMD does not raise any
additional arguments other than those presented in connection with claim 16.
We have addressed those arguments in our analysis above and determine
that they are likewise unavailing here. Upon consideration of LG’s analysis
and supporting evidence, we agree with LG’s showing as to claims 17 and
20, and adopt it as our own, that Gunther describes the claimed features
recited in claims 17 and 20. See, e.g., Pet. 28–29, 33–36; Ex. 1002 ¶¶ 116,
165–67; Ex. 1004, 5:47–54, 7:14–22, 7:45–52, 9:39–41, 9:49–55, 10:62–
11:8. For example, Gunther discloses adjusting the power consumption
level of a functional block to match the block utilization level in response to
the block utilization information by adjusting the clock frequency being
supplied to the functional block, as required by claim 17. Ex. 1004, 5:47–
54, 7:45–52, 10:62–11:8.
For the foregoing reasons, we conclude that LG has shown by
preponderance of the evidence that claims 16, 17, and 20 are anticipated by
Gunther. As discussed above, however, we determine that LG has not
shown by preponderance of the evidence that claim 18 is anticipated by
Gunther.
F. Obviousness over Gunther and ACPIS
LG asserts that claims 21–23 are unpatentable under § 103(a) as
obvious over the combination of Gunther and ACPIS. Pet. 36–42.
AMD opposes, arguing that the combination of Gunther and ACPIS
does not disclose the elements of independent claim 16 and the “adjusting
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power” limitation of independent claim 23, which is similar to the “adjusting
power” limitation of claim 16. PO Resp. 43–57. Essentially, AMD relies
upon the same arguments presented in connection with claim 16. Id. at 55.
We have addressed those arguments in our anticipation analysis above, and
determine that those arguments are likewise unavailing here. As discussed
above, we determine that LG has shown sufficiently that Gunther describes
all of the limitations of claim 16, including the “adjusting power” limitation.
AMD also argues that the ACPIS is not a printed publication. Id. at
57–58. For the reasons stated in our analysis above under the section
heading “Whether the ACPIS is a Printed Publication” in this Decision, we
determine that LG has demonstrated sufficiently that the ACPIS is a printed
publication under § 102, and therefore, LG may rely upon the ACPIS for its
asserted ground of unpatentability under § 103(a).
ACPIS discloses a system for software control and monitoring of
processor power management in a computer system. Ex. 1006, 15–16. In
particular, ACPIS discloses that software can access the operating level of a
CPU and control power consumption of the CPU. Id.
LG asserts that it would have been obvious to modify Gunther to
include an integrated circuit having software accessible power management
features and software that monitors the circuit and adjusts power
consumption, as required by claims 21–23. Pet. 36. As support, LG directs
our attention to ACPIS, which discloses software control and monitoring of
processor power consumption in a computer system. Id. at 37 (citing
Ex. 1006, 1, 27, 86, 265; Ex. 1002 ¶¶ 123–24, 126–31, 173–75). LG further
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contends that one of ordinary skill in the art would have combined ACPIS’s
software features with Gunther’s disclosure of functional block monitoring
and control. Id.
AMD counters that one of ordinary skill in the art would not have
combined ACPIS with Gunther because ACPIS operates differently from
Gunther’s power management system. PO Resp. 52–56. In particular, citing
to Dr. Levitt’s testimony (Ex. 2002 ¶¶ 114–19), AMD alleges that ACPIS
throttles down a processor’s clock frequency when the system utilization
increases, and that this is in contrast to Gunther’s power management system
that increases power consumption levels to match increases in block
utilization levels. PO Resp. 52–56 (citing Ex. 1006, 83, 86, Figs. 4–13).
AMD also contends that the resulting combination would not have worked
for its intended purpose—to adjust power consumption levels to match the
respective block utilization levels. Id. at 56.
AMD’s arguments and expert testimony, however, narrowly focus on
the physical differences between the prior art systems, and improperly
attempt to bodily incorporate one system into the other. “It is
well-established that a determination of obviousness based on teachings
from multiple references does not require an actual, physical substitution of
elements.” In re Mouttet, 686 F.3d 1322, 1332 (Fed. Cir. 2012); In re Etter,
756 F.2d 852, 859 (Fed. Cir. 1985) (en banc) (noting that the criterion for
obviousness is not whether the references can be combined physically, but
whether the claimed invention is rendered obvious by the teachings of the
prior art as a whole). In that regard, one with ordinary skill in the art is not
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compelled to follow blindly the teaching of one prior art reference over the
other without the exercise of independent judgment. Lear Siegler, Inc. v.
Aeroquip Corp., 733 F.2d 881, 889 (Fed. Cir. 1984); see also KSR, 550 U.S.
at 420–21 (stating that a person with ordinary skill in the art is “a person of
ordinary creativity, not an automaton,” and “in many cases . . . will be able
to fit the teachings of multiple patents together like pieces of a puzzle”).
Here, LG does not rely on the ACPIS for its power management
scheme, but rather its ability for software to access utilization and control
power consumption. Pet. 36–42. As discussed above, Gunther discloses an
integrated circuit that measures functional block utilization, and adjusts
power consumption levels of the functional blocks in response to the block
utilization information to match the respective block utilization levels.
Ex. 1004, 1:9–11, 4:63–5:1, 5:29–39, 7:45–52, 9:36–62, 10:56–11:8.
As Dr. Min explains, ACPIS, in fact, discloses embodiments where power
consumption is increased in response to expected high utilization and
decreased in response to expected low utilization. Ex. 1002 ¶ 130; Ex. 1006,
38–39. In support of LG’s Petition, Dr. Min testifies that an ordinarily
skilled artisan would have combined ACPIS’s software teachings with
Gunther’s power management system, in view of the benefits from the
software’s flexibility in managing power control features, merging widely
used software features with an integrated circuit, to achieve a processor with
software accessible utilization circuits and software control of power
consumption. Ex. 1002 ¶ 174. Dr. Min further notes that ACPIS provides
software access for both “throttling” and utilization-based power
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management schemes showing that a relevant artisan would have understood
that the software accessibility features could be used for difference power
management schemes. Ex. 1035 ¶ 93. Therefore, in light of ACPIS’s
teaching, implementing software access and control features with Gunther’s
power control management system would not be “uniquely challenging or
difficult for one of ordinary skill in the art.” Leapfrog Enters., Inc. v.
Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007). Moreover, such a
combination would not change Gunther’s intended purpose for adjusting
power consumption levels to match the respective block utilization levels.
Based on the evidence before us, we credit the testimony of Dr. Min
in that regard (Ex. 1002 ¶¶ 130, 174; Ex. 1035 ¶¶ 91–93) over that of
Dr. Levitt (Ex. 2002 ¶¶ 114–19). See Yorkey, 601 F.3d at 1284. We find
Dr. Min’s testimony to be more consistent with the prior art of record. See,
e.g., Ex. 1006, 38–39. In light of the foregoing, we determine that LG has
articulated a sufficient rationale why one of ordinary skill in the art would
have modified Gunther’s power management system, in light of ACPIS, to
include software accessibility, monitoring, and control features so that it
would provide flexibility and efficient updates. See KSR, 550 U.S. at 417.
For the foregoing reasons, we determine that LG has demonstrated by
a preponderance of the evidence that claims 21–23 are unpatentable as
obvious over the combination of Gunther and ACPIS.

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III. CONCLUSION
In sum, we determine that LG has established by a preponderance of
the evidence that claims 16–18 and 20–23 of the ’520 patent are
unpatentable based on the following grounds:
Challenged Claims Basis References
16–18 and 20 § 102(e) Bertin
21–23 § 103(a) Bertin
16, 17, and 20 § 102(b) Gunther
21–23 § 103(a) Gunther and ACPIS

We, however, determine that LG has not established by a
preponderance of the evidence that claim 18 is anticipated by Gunther.
IV. ORDER
In consideration of the foregoing, it is:
ORDERED that claims 16–18 and 20 of the ’520 patent are held
unpatentable; and
FURTHER ORDERED that, because this is a Final Written Decision,
parties to the proceeding seeking judicial review of the decision must
comply with the notice and service requirements of 37 C.F.R. § 90.2.

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PETITIONER:

Robert G. Pluta
Bryon Wasserman
Amanda K. Streff
Jamie B. Beaber
Cliff A. Maier
MAYER BROWN LLP
rpluta@mayerbrown.com
bwasserman@mayerbrown.com
astreff@mayerbrown.com
jbeaber@mayerbrown.com
cmaier@mayerbrown.com
AMDIPR@mayerbrown.com

PATENT OWNER:

Michael D. Specht
Michael B. Ray
Donald Featherstone
Christian Camarce
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
mspecht-PTAB@skgf.com
mray-PTAB@skgf.com
donf-PTAB@skgf.com
ccamarce-PTAB@skgf.com