LG Display Co., Ltd.Download PDFPatent Trials and Appeals BoardApr 1, 202014701097 - (D) (P.T.A.B. Apr. 1, 2020) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/701,097 04/30/2015 Yong-Ho JANG 29273-29394/US 8608 138354 7590 04/01/2020 LG Display/FENWICK 801 California Street Mountain View, CA 94041 EXAMINER LAM, TUAN THIEU ART UNIT PAPER NUMBER 2842 NOTIFICATION DATE DELIVERY MODE 04/01/2020 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): FWLGDisplayPatents@fenwick.com ptoc@fenwick.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte YONG-HO JANG ___________ Appeal 2018-006226 Application 14/701,097 Technology Center 2800 ____________ Before ERIC B. CHEN, NORMAN H. BEAMER, and JOYCE CRAIG, Administrative Patent Judges. CHEN, Administrative Patent Judge. DECISION ON APPEAL Appeal 2018-006226 Application 14/701,097 2 STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 10, 21, 22, 24, and 28–30. Claims 1–9, 11–15, 17–20, and 25–27 have been cancelled. An oral hearing scheduled for February 19, 2020 was waived. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. CLAIMED SUBJECT MATTER The claims are directed to a shift register capable of preventing leakage current. (Abstract.) Claim 10, reproduced below, is illustrative of the claimed subject matter, with disputed limitations in italics: 10. A shift register comprising a plurality of stages, the shift register configured to drive gate lines of a display device, wherein each of the plurality of stages includes: an output unit configured to output any one input clock of a plurality of clocks or a gate off voltage in response to logic states of a first control node and a second control node; a noise cleaner configured to connect a previous output for a current stage and the first control node in response to a previous clock used in a previous stage as a previous output for the current stage at any one of previous stages, wherein a pulse of the previous clock partially overlaps a pulse of the any one input clock at a same logic level so that the noise cleaner 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as LG Display Co., Ltd. (Appeal Br. 2.) Appeal 2018-006226 Application 14/701,097 3 eliminates noise of the first control node occurred by coupling of the any one input clock; and a controller configured to control the second control node to have a logic state opposite to the logic state of the first control node in some periods, and wherein the noise cleaner includes: first and second transistors connected between the first control node and the previous output for the current stage in series to connect the first control node and the previous output for the current stage in response to a logic state of the previous clock for the current stage, and a third transistor configured to supply an offset voltage to a first connection node between the first and second transistors in response to the logic state of the first control node, the offset voltage being a different voltage than a first predetermined voltage and a second predetermined voltage corresponding to logic states of the second control node, wherein the offset voltage is greater than the second predetermined voltage, and wherein the controller includes an inverter configured to supply said any one input clock to the second control node in some periods, except an output period which the output unit outputs said any one input clock. REFERENCES Name Reference Date Chan et al. US 2010/0245300 Al Sept. 30, 2010 Kim et al. US 2014/0354655 A1 Dec. 4, 2014 Tan et al. US 2015/0043703 Al Feb. 12, 2015 Yao et al. US 9,368,230 B2 June 14, 2016 REJECTION Claims 10, 21, 22, 24, and 28–30 stand rejected under 35 U.S.C. § 103 as being unpatentable over Yao, Kim, Tan, and Chan. Appeal 2018-006226 Application 14/701,097 4 OPINION We are persuaded by Appellant’s arguments (Appeal Br. 13; see also Reply Br. 6) that the combination of Yao, Kim, Tan, and Chan would not have rendered obvious independent claim 10, which includes the limitation “the offset voltage being a different voltage than a first predetermined voltage and a second predetermined voltage corresponding to logic states of the second control node, wherein the offset voltage is greater than the second predetermined voltage.” The Examiner found that the row driver circuit module of Kim, in particular, n-type metal-oxide-semiconductor (NMOS) transistors M1 1205, M2 1210, and FB1 1255, as illustrated in Figure 12, corresponds to the limitation “a third transistor configured to supply an offset voltage to a first connection node between the first and second transistors in response to the logic state of the first control node.” (Final Act. 3–4.) The Examiner further found that Figure 7 of Kim, which illustrates transfer curve for Id (drain current) vs. Vgs (gate-to-source voltage) for an exemplary NMOS, including Vgs at -1 V (i.e., point 740), corresponds to the limitation “the offset voltage being a different voltage than a first predetermined voltage and a second predetermined voltage corresponding to logic states of the second control node, wherein the offset voltage is greater than the second predetermined voltage.” (Id. at 4; see also Ans. 2.) The Examiner concluded that “one skilled in the art would have readily recognized that the leakage current occurs in the transistor M2 1210 can be minimized by having the feedback transistor coupled to a voltage value of VDD being as low as 1 V.” (Ans. 2– 3.) We do not agree with the Examiner’s findings and conclusions. Appeal 2018-006226 Application 14/701,097 5 Kim “relates to reducing leakage currents in circuits for electromechanical systems and devices.” (¶ 1.) Figure 12 of Kim illustrates a circuit schematic of a row driver circuit module having twelve NMOS transistors, including transistor M1 1205, transistor M2 1210, and feedback transistor FB1 1255 (¶ 98), such that “transistors M1 1205 and M2 1210 may be coupled together to define a feedback node 1275” (¶ 101.) Figure 7 of Kim illustrates “transfer curve for Id (drain current) vs. Vgs (gate-to-source voltage) for an exemplary NMOS transistor.” (¶ 76.) In reference to Figure 7, Kim explains that “biasing the Vgs of an NMOS transistor lower may reduce the sub-threshold leakage,” for example “biasing Vgs at point 740, or any lower Vgs value, rather than point 730 at 0 V Vgs, reduces the Id sub-threshold leakage.” (¶ 79.) Kim further explains the following: The gate to transistor M2 1210 is CK2, which is low during the bootstrap phase at time 1020. Therefore, transistor M2 1210 is turned off. As such, transistor M2 1210’s Vgs is negative. For example, if VDD is 5 V and CK2 is 0 V, then Vgs is -5 V. As previously discussed, a lower Vgs provides a lower Id. Accordingly, the leakage current at transistor M2 1210 is reduced by lowering the Vgs. Thus, the discharge of charge node Q 1265 is reduced. Leakage is also reduced at transistor M21 1245 through a similar technique. (¶ 103.) Thus, Figure 12 of Kim illustrates a row driver circuit module with twelve separate MNOS transistors (¶ 98) and Kim explains that “[l]eakage is also reduced at transistor M21 1245 through a similar technique” by lowering the Vgs (¶ 103). Although the Examiner proposes to modify transistor M2 1210 of Figure 12, such that Vgs is negative, the Examiner has not provided an articulated reasoning with some rational underpinning as to Appeal 2018-006226 Application 14/701,097 6 why one of ordinary skill in the art would only select transistor M2 1210 from among the twelve NMOS transistors in Figure 12, such that Vgs is negative. See In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006) (“[R]ejections on obviousness grounds cannot be sustained by mere conclusory statements; instead, there must be some articulated reasoning with some rational underpinning to support the legal conclusion of obviousness”); see also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). Accordingly, we are persuaded by Appellant’s arguments, as follows: Further, Kim at [0103] describes that leakage “is also reduced at transistor M21 1245 through a similar technique” and also shows a similar configuration where transistor FB2 is configured to supply the same VDD to a node 1280. Thus, Kim teaches a technique to reduce leakage in which a feedback transistor is configured to supply VDD to a feedback node. This VDD is the same VDD that can be supplied to the QB node of Kim. In short, there is nothing in Kim that suggests that the VDD supplied to node 1275 must be different from the VDD supplied to node QB and Kim discloses quite the opposite that the same VDD is used. (Appeal Br. 13.) The examiner does not explain why a VDD connected to FB 1 that is configured to supply VDD to node 1275 must necessarily be different than the VDD connected to MB 1240 that is configured to supply VDD to QB. (Reply Br. 6 (emphasis omitted).) Thus, we do not agree with the Examiner that the combination of Yao, Kim, Tan, and Chan would have rendered obvious independent claim 10, which includes the limitation “the offset voltage being a different voltage than a first predetermined voltage and a second predetermined voltage Appeal 2018-006226 Application 14/701,097 7 corresponding to logic states of the second control node, wherein the offset voltage is greater than the second predetermined voltage.” Accordingly, we do not sustain the rejection of independent claim 10 under 35 U.S.C. § 103. Claims 28 and 30 depend from claim 10. We do not sustain the rejection of claims 28 and 30 under 35 U.S.C. § 103 for the same reasons discussed with respect to claim 10. Independent claim 21 recites limitations similar to those discussed with respect to claim 10. We do not sustain the rejection of claim 21, as well as dependent claims 22, 24, and 29, for the same reasons discussed with respect to claim 10. CONCLUSION The Examiner’s decision rejecting claims 10, 21, 22, 24, and 28–30 under 35 U.S.C. § 103 is reversed. DECISION In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 10, 21, 22, 24, 28–30 103 Yao, Kim, Tan, and Chan 10, 21, 22, 24, 28–30 REVERSED Copy with citationCopy as parenthetical citation