Lemke, Marko

Patent Trials and Appeals Board

Jan 14, 2020

14843484 - (D) (P.T.A.B. Jan. 14, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/843,484 09/02/2015 Marko Lemke 1012-1168 /
2014P51142 US
6938
57579 7590 01/14/2020
MURPHY, BILAK & HOMILLER/INFINEON TECHNOLOGIES
1255 CRESCENT GREEN
SUITE 200
CARY, NC 27518
EXAMINER
KING, DOUGLAS
ART UNIT PAPER NUMBER
2824
NOTIFICATION DATE DELIVERY MODE
01/14/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
official@mbhiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MARKO LEMKE
Appeal 2019-000646
Application 14/843,484
Technology Center 2800
Before KAREN M. HASTINGS, JAMES C. HOUSEL, and LILAN REN,
Administrative Patent Judges.
REN, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–3, 5–19, and 21. See Final Act. 2, 7,
8. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.

1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42. Appellant identifies the real party in interest as “INFINEON
TECHNOLOGIES AG, a German company.” Appeal Br. 2.
Appeal 2019-000646
Application 14/843,484

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CLAIMED SUBJECT MATTER
The claims are “relate to information storage devices and in particular
to memory circuits and a method for forming a memory circuit.” Spec. ¶ 2.
Independent claims 1, 19, and 21, reproduced below, are illustrative of the
claimed subject matter:
1. A memory circuit, comprising:
a memory element comprising a first electrode layer
comprising lithium formed over a substrate, a second electrode
layer and a solid-state electrolyte layer arranged between the first
electrode layer and the second electrode layer;
a contact via extending through the first electrode layer,
the solid-state electrolyte layer and the second electrode layer to
provide electrical contact with the substrate; and
a memory access circuit configured to determine a
memory state of the memory element, wherein the memory
element is configured to switch to one of at least three predefined
memory states based on a transport of ions to the first electrode
layer or the second electrode layer via the solid-state electrolyte
layer.
19. A method for forming a memory circuit, the
method comprising:
forming a first electrode layer comprising lithium over a
substrate surface;
forming a solid-state electrolyte layer over the first
electrode layer;
forming a second electrode layer over the solid state
electrolyte;
etching the second electrode layer and the solid-state
electrolyte layer so that at least one memory element stack of a
memory element remains, wherein the memory element stack
comprises at least part of the solid-state electrolyte layer and the
second electrode layer; and
forming a contact via that extends through the first
electrode layer, the solid-state electrolyte layer and the second
electrode layer to provide electrical contact with the substrate.
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21. A method for determining a memory state of a
memory element, the method comprising:
programing a memory element to switch to one of at least
three predefined memory states based on a predefined bias
voltage applied between a first electrode layer and a second
electrode layer of the memory element based on a transport of
ions to the first electrode layer or the second electrode layer via
a solid-state electrolyte layer, wherein the solid-state electrolyte
layer is arranged between the first and second electrode layers,
and wherein the first electrode layer comprises lithium;
applying the predefined bias voltage between the first
electrode layer and the second electrode layer to switch the
memory element to one of the at least three predefined memory
states; and
determining a predefined memory state of the memory
element with a memory access circuit based on a measurement
of a memory stage voltage between the first and second
electrode layers.

Claims Appendix (emphases added).
REFERENCES
The prior art references relied upon by the Examiner are:
Name Reference Date
Ishii
Mandell
Ho
Bloch
Meyer
Yazami
Singh
US 2002/0068222 A1
US 2006/0038169 A1
US 2007/0161186 A1
US 2008/0043515 A1
US 2008/0106929 A1
US 2009/0029237 A1
US 2011/0281173 A1
June 6, 2002
Feb. 23, 2006
July 12, 2007
Feb. 21, 2008
May 8, 2008
Jan. 29, 2009
Nov. 17, 2011

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Application 14/843,484

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REJECTIONS
The Examiner rejects claims 1–3, 5, 6, 9, 13, 18, 19, and 21 under
35 U.S.C. § 103 as obvious over Bloch in view of Mandell and Ho. Final
Act. 2.2
The Examiner rejects claim 7 under 35 U.S.C. § 103 as being
unpatentable over Bloch in view of Mandell, Ho, and Singh. Final Act. 7.
The Examiner rejects claim 8 under 35 U.S.C. § 103 as being
unpatentable over Bloch in view of Mandell, Ho, and Yazami. Final Act. 7.
The Examiner rejects claim 10 under 35 U.S.C. § 103 as being
unpatentable over Bloch in view of Mandell, Ho, and Ishii. Final Act. 8.
The Examiner rejects claim 11, 12, and 14–17 under 35 U.S.C. § 103
as being unpatentable over Bloch in view of Mandell, Ho, and Meyer. Final
Act. 8.
OPINION
Claims 1 & 19
In rejecting claim 1, the Examiner finds Bloch teaches a memory
circuit having the recited layers whereas Ho teaches a “contact via extending
through the first electrode layer, the solid-state electrolyte layer and the
second electrode layer” as recited. Final Act. 3, 4. The Examiner specifically
finds that Figure 2 of Ho teaches memory layers 58 and 60 and a contact via
78 which is “formed through the layers.” Id. at 4. In the Examiner’s Answer,
the Examiner further elaborates that contact via 78 of Ho “is formed by
removing portions of memory layers and placing the contact layer in their

2 In the Final Rejection, the Examiner states that the claims are rejected
under “35 U.S.C. 102(a)(1) as obvious” over the three references. Final Act.
2. We understand the rejection to be under section 103.
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place along with some intervening materials.” Ans. 3. The Examiner
provides a comparison between Figure 2 of Ho and Figure 2A of the pending
application to support the finding. Id. at 7. The comparison is reproduced
below as Fig. 1:

Fig. 1. Examiner’s Annotated Comparison between Claim 1 and Ho
Appellant, on the other hand, argues that the Examiner reversibly
erred because Figure 2 of Ho does not show the prior art contact via 78
extending through the three recited layers – that is, Ho’s contact via 78 does
not extend “to directly enter and exit the claimed first, second and third
layers.” Appeal Br. 13 (citing a definition of the term “through” from the
Oxford Dictionary).
Based on the record before us, we are persuaded that the Examiner
reversibly erred in this aspect of the obviousness analysis. From the outset,
the Examiner’s finding that Figure 2 of Ho teaches a contact via 78 which is
“formed through the layers” (Final Act. 4) does not sufficiently explain why
the process in which the contact via is formed teaches the recited
configuration of the “contact via extending through” the layers. “As
Appellant contends, Ho’s contact via 78 extends through dielectric layers 70,
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74, rather than the memory layers 58, 60, 62. See Ho, Fig. 9; see also Ans. 3
(finding that that contact via 78 of Ho “is formed by removing portions of
memory layers and placing the contact layer in their place along with some
intervening materials” without sufficiently explaining why the process in
which the contact via is formed supports the teaching of the recited
limitation). We do not sustain the rejection of claim 1 on this basis. The
rejections of the claims dependent from claim 1 are not sustained based on
their dependency from claim 1.
Moreover, the Examiner reasons that claim 1 requires the three layers
to be part of the recited “memory element” and “not just layers placed
anywhere in the device.” Ans. 6. This reasoning, however, does not
sufficiently explain why Figure 2 of Ho teaches or suggests the relevant
limitations of claim 19 which requires only that “the memory element stack
comprises at least part of the solid-state electrolyte layer and the second
electrode layer” and that the “contact via extends through” the recited three
layers. We do not sustain the rejection of claim 19 as a result.
Claim 21
Unlike claims 1 and 19, claim 21 does not recite “a contact via.” The
dispositive issue in the rejection of claim 21 is the Examiner’s finding that
Bloch teaches or suggests a method step of “programing a memory element
to switch to one of at least three predefined memory states based on a
predefined bias voltage applied between a first electrode layer and a second
electrode layer of the memory element based on a transport of ions to the
first electrode layer or the second electrode layer via a solid-state electrolyte
layer . . . .” Appeal Br. 18 (arguing that the “feature of ‘three predefined
memory states’ is not an obvious modification of Bloch”).
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The Examiner finds that Bloch paragraph 42 teaches “at least two
distinct states” of a memory cell. Final Act. 3. The Examiner also finds that
Bloch paragraph 42 teaches an “‘ON’ state for which the first active layer
102 and the second active layer 104 have given compositions of ionic
species” as well as an “‘OFF’ state for which the compositions of ionic
species in the first active layer 102 and the second active layer 104 are
different from said given compositions.” Bloch ¶ 42 (cited in Final Act. 3).
Citing paragraph 44 of Mandell for the proposition that it is “common
practice in the art to increase memory density,” the Examiner finds that a
skilled artisan would have found it obvious to modify Bloch for the recited
“at least three predefined memory states.” Final Act. 4.
Appellant’s sole argument with regard to paragraph 42 of Bloch is
that Bloch is not enabling as to the recited “at least three predefined memory
states” because Bloch “does not provide any detail as to how such a device
configuration might be achieved.” Appeal Br. 17.3 This argument does not
identify reversible error because claim 21 is a method claim without
requiring any particular configuration of an apparatus. In any event, “a prior
art publication cited by an Examiner is presumptively enabling barring any

3 We have considered Appellant’s other arguments but find them
unpersuasive, because they do not address paragraph 42 of Bloch and do not
address the limitations of claim 21. See Appeal Br. 16 (arguing that the
recited “at least three predefined states” is a structural feature which is not at
issue in the rejection of process claim 21 and arguing that “Bloch is certainly
not suggesting that any of the depicted voltage values represent discrete
states that can be stored within the memory device” which is not recited in
claim 21); see id. at 17–18 (arguing the Examiner reversibly erred because
the rationale to combine “overlooks the precise way in which the claimed
device is configured” which is not recited in the steps of process claim 21).
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showing to the contrary by a patent applicant.” In re Antor Media Corp., 689
F.3d 1282, 1288 (Fed. Cir. 2012). Appellant makes no showing that Bloch is
non-enabling for its teaching of “at least two distinct states” of a memory
cell, which encompasses the recited “at least three predefined memory
states.” No reversible error has therefore been identified.
We are also not persuaded by the argument that the Examiner
reversibly erred in combining Mandell and Bloch. Appeal Br. 18. Appellant
argues that “Mandell’s device has an appreciably different structure than
Bloch’s” and that Mandell “provides no pertinent teaching as to how to
modify Bloch in a way that meets the claimed requirement.” Id. Process
claim 21, however, only requires a teaching or suggestion of the recited
steps. Moreover, we note that the Examiner’s rejection is not based on
incorporating the Mandell structure into that of Bloch, but rather based on
Mandell’s teaching of a “common practice in the art to increase memory
density” such that a skilled artisan would have found it obvious to modify
Bloch for the recited “at least three predefined memory states.” Final Act. 4.
We accordingly affirm the rejection of claim 21.
CONCLUSION
The Examiner’s rejections are affirmed in part.
More specifically,
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DECISION SUMMARY
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1–3, 5, 6, 9,
13, 18, 19,
21
103 Bloch, Mandell, Ho 21 1–3, 5, 6,
9, 13, 18,
19
7 103 Bloch, Mandell, Ho,
Singh
7
8 103 Bloch, Mandell, Ho,
Yazami
8
10 103 Bloch, Mandell, Ho,
Ishii
10
11, 12, 14–
17
103 Bloch, Mandell, Ho,
Meyer
11, 12, 14–
17
Overall
Outcome:
21 1–3, 5–19

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED-IN-PART