International Business Machines Corporation

Patent Trials and Appeals Board

May 25, 2021

2020002834 (P.T.A.B. May. 25, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/965,957 12/11/2015 Jeffrey C. Brownscheidle AUS920140515US1 2459
11432 7590 05/25/2021
IBM Corporation - Patent Center
1701 North Street
B/256-3
Endicott, NY 13760
EXAMINER
LINDLOF, JOHN M
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
05/25/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
edciplaw@us.ibm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE

___________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD

___________________

Ex parte JEFFREY C. BROWNSCHEIDLE, SUNDEEP CHADHA,
MAUREEN A. DELANEY, and DUNG Q. NGUYEN

____________________

Appeal 2020-002834
Application 14/965,957
Technology Center 2100

____________________

Before MICHAEL R. ZECHER, JUSTIN T. ARBES, and
BARBARA A. BENOIT, Administrative Patent Judges.

ZECHER, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2020-002834
Application 14/965,957

2
I. STATEMENT OF THE CASE
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
Final Action2 rejecting claims 1–20. Appeal Br. 5. We have jurisdiction
under 35 U.S.C. § 6.
We reverse.
Appellant’s Invention
Appellant’s purported invention generally relates to “processor
microarchitecture” and, in particular, “to the scheduling and issuing of
instructions to execution units in a processor.” Spec. ¶ 1. According to
Appellant, in conventional “computer architectures,” “issue queue logic is
usually optimized for speed and consequently can consume significant
amounts of energy during its operation.” Id. ¶ 3. “Techniques that can
decrease the energy consumed by issue queue logic while maintaining its
speed are highly valued and are an active area of research.” Id. Appellant
addresses this concern regarding energy consumption in computer
architectures by providing “a method, [computer] program product, and
system for . . . decreasing a rate of logic voltage level transitions in a
multiplexor.” Id. ¶ 4.
Figure 7, reproduced below, illustrates a flowchart that represents “the
major operations performed in an embodiment of the present invention to
reduce transitions on the output of a multiplexor . . . by reducing changes to
the select input to the multiplexor.” Spec. ¶ 38.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. According to Appellant, the real party in interest is
International Business Machines Corporation. Appeal Br. 3.
2 All references to the Final Action refer to the Final Action mailed on
March 28, 2019.
Appeal 2020-002834
Application 14/965,957

3

Figure 7, reproduced above, illustrates a flowchart that begins with
generating a select input to the multiplexor at step 701. Id. At step 702, a
determination is made as to whether the select input is valid. Id. If the
select input is not valid, “the select input to the multiplexor remains the
same and the process ends” at step 706. Id. ¶ 39. At step 703, if the select
input is valid, “a determination is made as to whether the value of the select
input has the same value as the last latched select input.” Id. ¶ 38. “If the
value of the select input has the same value as the last [latched] select input,
. . . the select input to the multiplexor remains the same and the process
ends” at step 706. Id. ¶ 39. However, “[i]f the value of the select input does
not have the same value as the last [latched] select input,” the multiplexor
Appeal 2020-002834
Application 14/965,957

4
applies the select input at step 704, latches the value of the select input so
that it becomes the last latched select input at step 705, and the process ends
at step 706. Id. ¶ 38.
Illustrative Claim
Claims 1, 8, and 15 are independent claims. Independent claim 1 is
directed to “[a] method for decreasing a rate of logic voltage level transitions
in a multiplexor,” independent claim 8 is directed to “[a] computer program
product for selecting and issuing an oldest ready instruction in an issue
queue,” and independent claim 15 is directed to “[a] computer system
product” for performing the same functions as independent claim 8.
Appeal Br. 18–21 (Claims Appendix). Claims 2–7 directly or indirectly
depend from independent claim 1, claims 9–14 directly or indirectly depend
from independent claim 8, and claims 16–20 directly or indirectly depend
from independent claim 15. Independent claim 1 is illustrative of the
disclosed invention and this claim is reproduced below:
1. A method for decreasing a rate of logic voltage level
transitions in a multiplexor, the method comprising:
selecting, by one or more processors, one of a plurality of
inputs to a multiplexor with a first multiplexor select value at a
first clock, wherein each input to the multiplexor is identified as
one of i) valid and ii) invalid and the first multiplexor select value
is latched in a latch until the first multiplexor select value is
replaced by a second multiplexor select value;
determining, by one or more processors, the second
multiplexor select value;
comparing, by one or more processors, the second
multiplexor select value and the first multiplexor select value;
in response to the second multiplexor select value being
the same as the first multiplexor select value, maintaining, by one
or more processors, the first multiplexor select value at a second
Appeal 2020-002834
Application 14/965,957

5
clock, wherein (i) the multiplexor does not change the selection
from the plurality of inputs and (ii) the second clock occurs after
the first clock;
in response to (a) the second multiplexor select value is
different from the first multiplexor select value and (b) the
second multiplexor select value selects a valid input, applying,
by one or more processors, the second multiplexor select value
to the multiplexor at the second clock, wherein the second clock
occurs after the first clock; and
subsequent to applying the second multiplexor select
value, latching, by one or more processors, the second
multiplexor value in the latch.
Id. at 18 (Claims Appendix).
Prior Art Relied Upon
Inventor3 Patent or Publication No. Relevant Dates
Ventrone U.S. Patent No. 6,054,877 issued Apr. 25, 2000;
filed June 3, 1998
Jacobson U.S. Patent Application
Publication No. 2003/0043665
A1
published Mar. 6, 2003;
filed Aug. 20, 2001
Doing U.S. Patent Application
Publication No. 2010/0257340
A1
published Oct. 7, 2010;
filed Apr. 3, 2009
Rejections on Appeal4
References 35 U.S.C. § Claim(s) Rejected
Ventrone, Jacobson 103 1
Ventrone, Jacobson, Doing 103 2–20

3 For clarity and ease of reference, we only list the first named inventor.
4 The Examiner withdrew the rejection of claims 1–20 under 35 U.S.C.
§ 112(a) as failing to comply with the written description requirement.
Ans. 3; Advisory Action mailed June 28, 2019.
Appeal 2020-002834
Application 14/965,957

6
Examiner’s Findings and Conclusions
The Examiner finds that Ventrone’s multiplexor that provides output
data signal transitions only for valid input data signals teaches all the
limitations of independent claim 1, except “comparing, by one or more
processors, the second multiplexor select value and the first multiplexor
select value.” Final Act. 3–5 (citing Ventrone, 1:24–27, 3:20–46, Fig. 4).
The Examiner turns to Jacobson’s logic that only switches when the tag
valid signal changes value to teach this limitation. Id. at 5 (citing Jacobson
¶ 97). According to the Examiner, it would have been obvious to a person
of ordinary skill in the art to combine the teachings of Ventrone with those
of Jacobson to perform “comparing, by one or more processors, the second
multiplexor select value and the first multiplexor select value” because it
“would have provided power savings benefits such as discussed by
Jacobson.” Id. (citing Jacobson ¶ 97). Although the Examiner relies on the
teachings of Doing to account for certain limitations of claims 2–20, we
understand the Examiner to rely on essentially the same findings and
conclusion to support the obviousness rejection of independent claims 8 and
15 based on the combined teachings of Ventrone and Jacobson. Compare
Final Act. 7, with id. at 3–5.
Appellant’s Contentions
Appellant contends that, at best, Ventrone’s multiplexer keeps a select
value until it receives a new valid input data signal, but Ventrone does not
teach that the multiplexer compares the current select value to the last
latched select value, let alone applying a new select value if the multiplexer
detects a difference between the two, as required by independent claims 1, 8,
and 15. Appeal Br. 12–13 (citing Ventrone 3:40–43). Appellant further
Appeal 2020-002834
Application 14/965,957

7
contends that, even assuming that Jacobson’s tag bits amount to the “select
values” required by independent claims 1, 8, and 15, Jacobson is silent with
respect to determining a difference in value between two tag bits. Id. at 13–
14 (citing Jacobson ¶¶ 18, 97). Instead, Appellant asserts that Jacobson only
teaches determining and subsequent handling of the tag bits when there is a
change in validity—not a change in value. Id. at 14; see also Reply Br. 5
(arguing that independent claims 1, 8, and 15 “are directed towards the
comparison of select values” and not just identifying the validity of select
values).
II. ISSUE
Based on the record before us, the dispositive issue is whether
Ventrone and Jacobson, either individually or collectively, teach
“comparing, by one or more processors, the second multiplexor select value
and the first multiplexor select value,” as recited in independent claim 1, and
similarly recited in independent claims 8 and 15?
III. ANALYSIS
Obviousness Rejection Over Ventrone and Jacobson
Claim 1
Based on the record before us, we discern error in the Examiner’s
obviousness rejection of independent claim 1, which recites, in relevant part,
“comparing, by one or more processors, the second multiplexor select value
and the first multiplexor select value.”
At the outset, it is unclear to us what extent, if any, the Examiner
relies on Ventrone to teach “comparing, by one or more processors, the
second multiplexor select value and the first multiplexor select value.”
Although it initially appears that the Examiner does not rely on Ventrone in
Appeal 2020-002834
Application 14/965,957

8
the Final Action under appeal to teach this limitation (see Final Act. 4–5; see
also Ans. 4 (arguing that Ventrone was not relied on to teach the
“comparing” step)), the Examiner nonetheless creates uncertainty through
the responsive arguments in the Answer by finding that a person of ordinary
skill in the art would have understood that applying a new select value due
to a change in select signal is a “basic and essential” function of Ventrone’s
multiplexor (Ans. 4–5).
To the extent the Examiner relies on Ventrone’s multiplexor in any
respect to teach “comparing, by one or more processors, the second
multiplexor select value and the first multiplexor select value,” we do not
agree with the Examiner for two reasons. First, as Appellant correctly notes
in its Appeal Brief, Ventrone’s multiplexer merely keeps a select value until
it receives a new valid input data signal. Ventrone, 3:20–39. According to
Ventrone, by preventing false transitions between valid and invalid data, the
multiplexor provides power savings. Id. at 2:22–23, 3:40–46. Appellant
does not direct us to, nor are we aware of, a disclosure that indicates
Ventrone’s multiplexor prevents false transitions between valid and invalid
data by comparing the select values of two valid input data signals.
Second, the Examiner’s finding that a person of ordinary skill in the
art would have understood that applying a new select value due to a change
in select signal is a “basic and essential” function of Ventrone’s multiplexor
tells us little, if anything, as to what specific operations are performed by the
multiplexor to make the new selection. See Ans. 4–5. Absent further
explanation from the Examiner as to how the “basic and essential”
functionality of Ventrone’s multiplexor results in a new selection by
comparing select values of two valid input data signals, we are not
Appeal 2020-002834
Application 14/965,957

9
persuaded that the Examiner provides sufficient evidence to support a
finding that Ventrone’s multiplexor functions in a manner that properly
accounts for the disputed limitation.
Turning to the Examiner’s reliance on Jacobson, we are not persuaded
that Jacobson’s logic that only switches when the tag valid signal changes
value teaches “comparing, by one or more processors, the second
multiplexor select value and the first multiplexor select value.” Even
assuming that Jacobson’s tag bits amount to the claimed “select values,”
Jacobson discloses that changing the value of the tag valid signal is
dependent on whether the tag signal is valid or invalid. Jacobson ¶¶ 18, 97;
see also Reply 4 (stating that “[m]ultiplexors are essentially a large bank of
switches”). The Examiner, however, does not explain how changing the
value of the tag valid signal encompasses comparing the values of two tag
signals.
It follows that the Examiner has erred in determining that the
combined teachings of Ventrone and Jacobson render the subject matter of
independent claim 1 obvious.
Obviousness Over Ventrone, Jacobson, and Doing
Claims 8 and 15
Similar to independent claim 1, each of independent claims 8 and 15
recite “program instructions to compare the second multiplexor select value
and the first multiplexor select value.” Appeal Br. 19–20 (Claims
Appendix). As applied by the Examiner, Doing does not remedy the
deficiencies in the combined teachings of Ventrone and Jacobson discussed
above. See Final Act. 7. Therefore, for the same reasons discussed above
with respect to independent claim 1, the Examiner has erred in determining
Appeal 2020-002834
Application 14/965,957

10
that the combined teachings of Ventrone, Jacobson, and Doing render the
subject matter of independent claims 8 and 15 obvious.
Claims 2–7, 9–14, and 16–20
By virtue of their dependency, dependent claims 2–7, 9–14, and 16–
20 include the same limitations as at least one of independent claims 1, 8,
and 15. See Appeal Br. 23; Reply Br. 5. When rejecting each of these
dependent claims, the Examiner relies on the same findings to explain how
Ventrone and Jacobson, either individually or collectively, teach
“comparing, by one or more processors, the second multiplexor select value
and the first multiplexor select value,” as recited in independent claim 1, and
similarly recited in independent claims 8 and 15. See Final Act. 6–7;
Ans. 4–5. Therefore, for the same reasons set forth above in our discussion
of independent claim 1, the Examiner has erred in determining that the
combined teachings of Ventrone, Jacobson, and Doing render the subject
matter of dependent claims 2–7, 9–14, and 16–20 obvious.
IV. CONCLUSION
For the foregoing reasons, the Examiner has erred in rejecting
(1) claim 1 as unpatentable under § 103 as obvious over the combined
teachings of Ventrone and Jacobson; and (2) claims 2–20 as unpatentable
under § 103 as obvious over the combined teachings of Ventrone, Jacobson,
and Doing. Accordingly, we reverse the Examiner’s decision to reject these
claims.
Appeal 2020-002834
Application 14/965,957

11
V. DECISION SUMMARY
In summary:
Claim(s)
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1 103 Ventrone, Jacobson 1
2–20 103 Ventrone, Jacobson,
Doing
2–20
Overall
Outcome
1–20

REVERSED