Intel Corporation

Patent Trials and Appeals Board

Mar 10, 2022

2020006316 (P.T.A.B. Mar. 10, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 16/271,572 02/08/2019 Aliasgar S. Madraswala P95846-C1 3345 75343 7590 03/10/2022 Hanley, Flight & Zimmerman, LLC (Intel) 150 S. Wacker Dr. Suite 2200 Chicago, IL 60606 EXAMINER WEI, JANE ART UNIT PAPER NUMBER 2139 NOTIFICATION DATE DELIVERY MODE 03/10/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docketing@hfzlaw.com jflight@hfzlaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte ALIASGAR S. MADRASWALA, YOGESH B. WAKCHAURE, CAMILA JARAMILLO, and TRUPTI BEMALKHEDKAR Appeal 2020-006316 Application 16/271,572 Technology Center 2100 Before BRADLEY W. BAUMEISTER, MINN CHUNG, and DAVID J. CUTITTA II, Administrative Patent Judges. CUTITTA, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1-22. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42(a) (2022). Appellant identifies Intel Corporation, as the real party in interest. Appeal Brief filed October 15, 2020 (“Appeal Br.”) at 2. Appeal 2020-006316 Application 16/271,572 2 CLAIMED SUBJECT MATTER Summary Appellant describes the subject matter of their application as relating generally to “perform[ing] erase-suspend operations in memory devices.” Spec. ¶ 1.2 According to Appellant: [b]y suspending an erase operation before its completion, one or more other memory operations requested by a memory host controller can be performed by the memory device without the memory host controller needing to wait for the memory device to complete the erase operation before the memory host controller can request the memory device to perform another memory operation. In this manner, examples disclosed herein can significantly increase throughput of memory devices by allowing other memory operations to be performed without needing to stall those memory operations until completion of an ongoing erase operation. Id. ¶ 18. The Specification explains that two conditions must be met before suspending an erase operation: “[w]hen a suspend point 232 (FIG. 2) is reached and the erase segment duration value 108 is satisfied by an elapsed length of time during which the memory device 104 performs the portion of the erase operation, the memory device 104 suspends the erase operation.” Id. ¶ 51. 2 In addition to the above-noted Appeal Brief, throughout this Decision we refer to: (1) Appellant’s Specification filed February 8, 2019 (“Spec.”); (2) the Final Office Action (“Final Act.”) mailed December 11, 2019; (3) the Examiner’s Answer (“Ans.”) mailed July 9, 2020; and (4) the Reply Brief filed September 9, 2020 (“Reply Br.”). Appeal 2020-006316 Application 16/271,572 3 Illustrative Claim Claim 1, reproduced below with dispositive limitation at issue italicized, illustrates the claimed subject matter: 1. An apparatus to use an erase-suspend feature on a memory device, the apparatus comprising: a host interface to receive a first erase command to perform an erase operation; and a control circuit to: based on the erase-suspend feature being enabled at the memory device, suspend the erase operation based on determining that (a) a length of time equal to an erase segment duration value has elapsed and (b) the erase operation has reached one of a plurality of suspend points associated with a block of memory to be erased, the length of time elapsed being relative to a start of an erase segment, and the erase segment duration value specified in a configuration parameter for the erase- suspend feature; perform a second memory operation when the erase operation is suspended; and after the second memory operation is complete, resume the erase operation based on receiving a second erase command. Appeal Br. 19 (Claims Appendix). REFERENCES AND REJECTIONS The Examiner rejects claims 1-4, 7-12, 15-19, and 22 under 35 U.S.C. § 102(a)(2) as anticipated by Hyun et al. (US 2016/0210050 A1, published July 21, 2016) (“Hyun”). Final Act. 3-14. Appeal 2020-006316 Application 16/271,572 4 The Examiner rejects claims 5, 13, and 20 under 35 U.S.C. § 103 as unpatentable over the combined teachings of Hyun and Aritome (US 2007/0047315 A1, published March 1, 2007). Id. at 14-15. The Examiner rejects claims 6, 14, and 21 under 35 U.S.C. § 103 as unpatentable over the combined teachings of Hyun and Sheffler et al. (US 2012/0117317 A1, published May 10, 2012) (“Sheffler”). Id. at 16-17. OPINION We review the appealed rejections for error based upon the issues identified by Appellant and in view of Appellant’s arguments and evidence. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential). 35 U.S.C. § 102 Rejection The Examiner finds Hyun discloses each of the limitations of claim 1. Final Act. 3-6. The Examiner relies on Hyun’s discussion of storage operation interrupt module 150 periodically interrupting an erase operation, to disclose “suspend the erase operation based on determining that (a) a length of time equal to an erase segment duration value has elapsed and (b) the erase operation has reached one of a plurality of suspend points associated with a block of memory to be erased,” as recited in claim 1. Id. at 4-5 (citing Hyun ¶¶ 32, 82, 84, 85, Figs. 1, 3). Appellant argues the Examiner errs in rejecting claim 1 as anticipated by Hyun because claim 1 requires that both events (a) and (b) must occur to suspend an erase operation and Hyun does “not teach using two separate conditions of ‘a length of time equal to an erase segment duration value’ and reaching ‘one of a plurality of suspend points associated with a block of memory to be erased,’ as set forth in claim 1, to suspend an erase operation.” Appeal 2020-006316 Application 16/271,572 5 Appeal Br. 14. According to Appellant, the “Examiner points to phases described at paragraph [0082] of Hyun et al. However, such phases of Hyun et al. are merely a result of interrupting a storage operation at a periodic interval” and therefore Hyun does not teach that both conditions (a) and (b) must occur before suspending of the erase operation occurs. Id. In response, the Examiner finds that “Hyun’s ‘predefined periodic interval’ reads on the claimed element of ‘(a) a length of time equal to an erase segment duration value.’” Ans. 4 (citing Hyun ¶ 32). The Examiner further finds that “Hyun describes a frequency module may have a frequency for pausing a storage operation such that phases have a length corresponding to the frequency for pausing a storage operation” and that these phases disclose (b) the erase operation has reached one of a plurality of suspend points. Id. (citing Hyun ¶ 82). We agree with Appellant that the Examiner errs in finding Hyun anticipates claim 1 and, thus, we do not sustain the rejection of claim 1 and of claims 9 and 16, which recite a similar limitation. As an initial matter, we agree with Appellant that claim 1, in view of Appellant’s Specification, requires two distinct events must occur before the erase operation may be suspended: (a) a predetermined time must elapse and (b) the erase operation must reach a suspend point. Appeal Br. 12. Notably, the Specification discloses that “[w]hen a suspend point 232 (FIG. 2) is reached and the erase segment duration value 108 is satisfied by an elapsed length of time during which the memory device 104 performs the portion of the erase operation, the memory device 104 suspends the erase operation.” Spec. ¶ 51 (emphasis added). Thus, as Appellant points out, “claim 1 sets Appeal 2020-006316 Application 16/271,572 6 forth a two condition test for determining when to suspend an erase operation.” Appeal Br. 12. The Examiner relies on Hyun’s discussion of storage operation interrupt module 150 (Hyun ¶¶ 31-34) to teach condition (a) and Hyun’s discussion of frequency module 302 (Hyun ¶¶ 82-85) to teach condition (b). Final Act. 4-5; Ans. 4. We agree with Appellant, however, that each of the portions of Hyun cited by the Examiner describe the same functionality and therefore Hyun teaches only a single condition. Hyun explains that frequency module 302, along with interrupt module 304, are functional components of storage operation interrupt module 150. Hyun, Fig. 3. Hyun discloses that frequency module 302 “may identify an interval or frequency at which the interrupt module 304, described below, may . . . electively interrupt an executing storage operation.” Hyun ¶ 78. Thus, in storage operation interrupt module 150, frequency module 302 alone determines the frequency or periodic interval that interrupt module 150 will then employ before pausing or interrupting a storage operation. Hyun explains, “the storage operation interrupt module 150 may interrupt an operation, such as an erase operation, periodically each 5 pulses, each 500 microseconds, or the like, segmenting the operation into multiple phases so that pending operations may execute between phases.” Hyun ¶ 34. Thus, the frequency or periodic interval determined by frequency module 302 may be alternatively measured in time or pulses. Hyun further discloses that frequency module 302: is configured to determine a frequency for pausing a storage operation. As used herein, a “frequency for pausing a storage operation” refers to an indicator of how often a storage operation is to be or may be interrupted, paused, divided, suspended, or the Appeal 2020-006316 Application 16/271,572 7 like. In certain embodiments, a frequency for pausing a storage operation may be a mandatory frequency or interval at which a storage operation is interrupted regardless of other pending operations or other factors. Hyun ¶ 78 (emphasis added). Thus, the portions of Hyun relied upon by the Examiner simply describe alternative ways that frequency module 302 of interrupt module 150 may define an interrupt interval or frequency, namely by time or number of pulses, each of which may constitute a phase. Hyun ¶ 34. In view of the discussion above, we agree with Appellant that in Hyun, “the predefined periodic interval and phases are the same thing, unlike the two separate conditions, set forth in claim 1, as ‘(a) a length of time equal to an erase segment duration value has elapsed and (b) the erase operation has reached one of a plurality of suspend points,’” Therefore, the cited portions of Hyun disclose one condition or event, rather than two, and because “claim 1 sets forth a two condition test for determining when to suspend an erase operation,” on this record, the Examiner does not demonstrate that Hyun discloses all the limitations of independent claim 1. Appeal Br. 12. Accordingly, we do not sustain the anticipation rejection of claim 1. Because we agree with at least one of the dispositive arguments advanced by Appellant, we need not reach the merits of Appellant’s other arguments with respect to the rejection of claim 1. We also do not sustain the anticipation rejection of independent claims 9 and 16 and of claims 2-4, 7, 8, 10-12, 15, 17-19, and 22, which variously depend from claims 1, 9, and 16. Appeal 2020-006316 Application 16/271,572 8 35 U.S.C. § 103 Rejection Because the Examiner does not rely on Aritome or Sheffler, alone or in combination, to cure the deficiency in the anticipation rejection of Hyun discussed above, we also do not sustain the obviousness rejections of dependent claims 5, 6, 13, 14, 20, and 21. DECISION SUMMARY In summary: REVERSED Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1-4, 7-12, 15-19, 22 102(a)(2) Hyun 1-4, 7-12, 15-19, 22 5, 13, 20 103 Hyun, Aritome 5, 13, 20 6, 14, 21 103 Hyun, Sheffler 6, 14, 21 Overall Outcome 1-22