Intel Corporation

Patent Trials and Appeals Board

Mar 1, 2022

2020005002 (P.T.A.B. Mar. 1, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/832,195 12/05/2017 Linden Cornett P18443X3XC3-C1 6339 120376 7590 03/01/2022 Compass IP Law PC 4804 NW Bethany Blvd, Ste. I-2 #237 Portland, OR 97229 EXAMINER AHMED, ABDULLAHI ART UNIT PAPER NUMBER 2472 NOTIFICATION DATE DELIVERY MODE 03/01/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): admin@compassiplaw.com eofficeaction@appcoll.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte LINDEN CORNETT, DAVID B. MINTURN, SUJOY SEN, HEMAL V. SHAH, ANSHUMAN THAKUR, GARY Y. TSAO, and ANIL VASUDEVAN, Appeal 2020-005002 Application 15/832,195 Technology Center 2400 Before ALLEN R. MacDONALD, MICHAEL J. STRAUSS, and GREGG I. ANDERSON, Administrative Patent Judges. ANDERSON, Administrative Patent Judge. DECISION ON APPEAL Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1-20 and 22-24. Final Act.2 2. 1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as Intel Corporation. Appeal Br. 1. 2 We use “Spec.” to refer to the Specification filed December 5, 2017; “Final Act.” to refer to the Final Office Action mailed August 6, 2019; “Appeal Br.” to refer to the Appeal Brief filed January 10, 2020; “Ans.” to refer to the Examiner’s Answer filed March 31, 2020; and “Reply Br.” to refer to the Reply Brief filed June 1, 2020. Appeal 2020-005002 Application 15/832,195 2 Appellant appeals the rejection of claims 1-20 and 22-24. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. CLAIMED SUBJECT MATTER The invention is directed to a network having a plurality of nodes where each “communicatively coupled” in that the nodes are capable of communicating with each other via over a communication medium, which can be wired or wireless. Spec. ¶ 21. The communication between nodes may include transmitting and receiving encoded packets over the communication medium. Id. A packet is “a sequence of one or more symbols and/or values that may be encoded by one or more signals transmitted from at least one sender to at least one receiver.” Spec. ¶ 22. The packets are split into “a header portion and a payload portion.” Id. ¶ 34. “The header and payload may be stored in separate locations (e.g., first and second buffers).” Id. Drivers “may perform accelerated processing,” and “may be referred to as a TCP-A (Transport Control Protocol - Accelerated) driver.” Spec. ¶ 28. TCP-A driver is any driver that may perform accelerated processing. Id. ¶ 29. Claims 1, 12, and 18 are respectively independent apparatus, method and system claims. Claims 2-11, 13-20 and 22-24 are dependent claims. Claim 1, reproduced below, illustrates the claimed subject matter: 1. An apparatus, comprising: a processor; Appeal 2020-005002 Application 15/832,195 3 an interface to receive a packet comprising a header of a particular protocol and a payload; and programmable logic to: split the packet to cause the header to be pushed, by a first driver, into a first portion of computer memory and the payload to be pushed, by a second driver different than the first driver, into a second, different portion of the computer memory; wherein the first portion of the computer memory comprises a cache of the processor. Appeal Br. 7 (Claims App.) (italicized language is at issue). REFERENCES The Examiner relies on the following references. Name3 Reference Date4 Laksono US 7,301,900 B1 May 24, 2001 Hayter US 2002/0174252 A1 Nov. 21, 2002 Pettey US 2003/0014544 A1 Jan. 16, 2003 Ono US 2005/0002350 A1 Jan. 6, 2005 REJECTION Claims 1-3, 5, 7-18, and 20 are rejected under 35 U.S.C. §102 as anticipated by Hayter. Final Act. 2-7. Claims 4 and 19 are rejected under 35 U.S.C. § 103 as obvious over Hayter and Ono. Id. at 7-8. Claim 6 is rejected under 35 U.S.C. § 103 as obvious over Hayter and Laksono. Id. at 8. Claims 22-24 are rejected under 35 U.S.C. § 103 as obvious over Hayter and Pettey. Id. at 9. 3 All reference citations are to the first named inventor only. 4 Publication dates except for Laksono which is the filing date. Appeal 2020-005002 Application 15/832,195 4 STANDARD OF REVIEW The Board conducts a limited de novo review of the appealed rejections for error based upon the issues identified by Appellant, and in light of the arguments and evidence produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential). Arguments not made are waived. See id.; 37 C.F.R. § 41.37(c)(1)(iv) (2019). CONTENTIONS AND ANALYSIS Issue: Are the “first and second drivers” as recited in claims 1, 12, and 18 disclosed in Hayter? The Examiner’s Findings The Examiner finds that the first and second drivers recited in claims 1, 12, and 18 are disclosed by paragraph 33 of Hayter. Final Act. 3 (claim 1), id. at 5-6 (claims 12 and 18). For claim 1, the entirety of the Examiner’s analysis is reproduced below: Paragraph 33, The OMA controller 38 may be configured, in one embodiment, to target a portion of a received packet for storage in the L2 cache 14. Specifically, it may be desirable for the header of a packet to be stored in the L2 cache 14, while the data payload may be stored in memory. The packet is split into two different portions, the header is stored in the cache memory and data directly stored in a memory[.] Final Act. 3. The Examiner further responds that Hayter discloses Different instructions (drivers) are issued to the packet interface circuit to store header in different location than the payload. These instructions are the drivers and since each instruction does different function i.e. instruction for storing header in L2 cache, therefore the instructions are different. (Figure 3)[.] Ans. 11-12. Appeal 2020-005002 Application 15/832,195 5 Appellant’s Contentions Appellant argues that: This cited portion of Hayter makes no mention of “split[ting] the packet to cause the header to be pushed, by a first driver, into a first portion of computer memory and the payload to be pushed, by a second driver different than the first driver, into a second, different portion of the computer memory” (emphasis added), and thus Hayter does not and cannot anticipate independent claim 1. Appeal Br. 5. Analysis “Before considering the rejections . . . we must first [determine the scope of] the claims.” In re Geerdes, 491 F.2d 1260, 1262 (CCPA 1974). All of the independent claims require both a first and second driver. The Specification describes drivers generally in the context of, for example, circuitry for performing “accelerated processing.” Spec. ¶¶ 28-29. Thus, we understand a driver to be circuitry to accelerate processing of the header and stored data. As noted above, in response to Appellant’s argument that the first and second drivers are not shown in Hayter, the Examiner cites Hayter5 Figure 3 as showing that “[d]ifferent instructions (drivers)” are issued to the packet interface circuit to store header in different location than the payload.” Ans. 11. Figure 3 of Hayter is reproduced below. 5 The Examiner references “Beale” instead of Hayter. However, it appears that Hayter was intended as Figure 3 of Hayter is reproduced at page 11 of the Answer. Ans. 11. Appeal 2020-005002 Application 15/832,195 6 Figure 3 is a diagram illustrating targeting of packet header data in the L2 cache. Hayter ¶ 14. Paragraph 33 of Hayter explains that “[i]f the header is stored in the L2 cache 14, the latency experienced by the processor 12A-12B in reading the header may be reduced.” Paragraph 33 of Hayter explains that “[t]he processor 12A-12B which processes the packet may typically be operating on the header information, and may not operate on the data payload.” Hayter ¶ 33, Fig. 3. We agree with the Examiner that circuitry shown in Figure 3 of Hayter provides different instructions for different drivers. Ans. 11-12 (citing Hayter Fig. 3). Specifically, the instructions are “issued to the packet interface circuit to store header in different location than the payload.” Id. at 11 (reproducing Hayter Fig. 3). The memory of Hayter shown in Figure 3 as described in Paragraph 60 is used to store data, thus “splitting” what type of data is stored into two separate parts of memory, the Cache 14 and Memory 26. Hayter Fig. 3; see also Hayter ¶ 60 (describing Figure 3). Appeal 2020-005002 Application 15/832,195 7 Appellant does not dispute the Examiner’s findings regarding Figure 3 of Hayter. The rejection of claim 1 as anticipated by Hayter is sustained. No separate argument is made as to the rejection of claims independent claims 12 and 18 as anticipated by Hayter is made and those rejections are sustained. The remaining obviousness rejections to dependent claims 4, 6, 19, and 22-24 are not separately argued and the rejections to those claims referenced above are sustained. CONCLUSION The Examiner’s decision to reject 1-20 and 22-24 is affirmed. DECISION SUMMARY In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1-3, 5, 7-18, 20 102 Hayter 1-3, 5, 7-18, 20 4, 19 103 Hayter, Ono 4, 19 6 103 Hayter, Laksono 6 22-24 103 Hayter, Pettey 22-24 Overall Outcome 1-20, 22-24 TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED