INTEL CORPORATION

Patent Trials and Appeals Board

Feb 28, 2022

2020006105 (P.T.A.B. Feb. 28, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/941,381 03/30/2018 Keith Underwood D148377-US 1637 57035 7590 02/28/2022 KACVINSKY DAISAK BLUNI PLLC 2601 Weston Parkway Suite 103 Cary, NC 27513 EXAMINER CHOWDHURY, MOHAMMED SHAMSUL ART UNIT PAPER NUMBER 2467 NOTIFICATION DATE DELIVERY MODE 02/28/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): INTEL@kdbfirm.com docketing@kdbfirm.com kpotts@kdbfirm.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte KEITH UNDERWOOD, KARL BRUMMEL, and JOHN GRETH _____________ Appeal 2020-006105 Application 15/941,381 Technology Center 2400 ____________ Before RICHARD M. LEBOVITZ, ST. JOHN COURTENAY III, and JENNIFER S. BISK, Administrative Patent Judges. COURTENAY, Administrative Patent Judge. DECISION ON APPEAL Appellant1 appeals under 35 U.S.C. § 134(a) from a final rejection of claims 1-25, which constitute all the claims pending in this application. We have jurisdiction over the pending claims under 35 U.S.C. § 6(b). We reverse. 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42(a) (2012). According to Appellant, the real party in interest in this appeal is “Intel Corporation.” See Appeal Br. 2. Appeal 2020-006105 Application 15/941,381 2 STATEMENT OF THE CASE2 Introduction Embodiments of Appellant’s claimed subject matter “are generally directed to communication between nodes of a multi-node network, and more particularly, to an end-point protocol to store the incoming packets, or a portion thereof, at a memory location provided by a host device.” See Spec. ¶ 2. Independent Claim 1 1. An apparatus, comprising: [L1] logic circuitry to couple with receive buffers to compare a first incoming packet to a first digest in a first entry of a primary array to determine whether the first incoming packet matches the first digest; [L2] when the first incoming packet matches the first digest, the logic circuitry to retrieve a first full entry from a secondary array, the first full entry to correspond to the first entry, and to compare the first full entry with the first incoming packet; [L3] when the first full entry matches the first incoming packet, the logic circuitry to store at least a portion of the first incoming packet at a first memory location, [L4] wherein entries in the secondary array comprise at least data and a memory location at which to store at least a portion of one of the incoming packets; and [L5] in absence of a match between the first incoming packet and the first digest or between the first incoming packet and the first full entry, the logic circuitry to compare the first incoming packet to subsequent entries in the primary array to identify a 2 We herein refer to the Final Office Action, mailed November 26, 2019 (“Final Act.”); the Appeal Brief, filed April 27, 2020 (“Appeal Br.”); the Examiner’s Answer, mailed June 25, 2020, and the Reply Brief, filed August 25, 2020 (“Reply Br.”). Appeal 2020-006105 Application 15/941,381 3 full entry in the secondary array that matches the first incoming packet. Appeal Br. 10 Claims App. (disputed claim limitations L1, L2, L3, and L4 bracketed and emphasized). Prior Art Evidence Relied Upon by the Examiner 3 Name Reference Date Aviles US 2010/0095064 A1 Apr. 15, 2010 Sabaa US 2014/0115182 A1 Apr. 24, 2014 Harlamert II US 2018/0359324 A1 Dec. 13, 2018 Singh US 2019/0149472 A1 May 16, 2019 Rejections Rejection Claims Rejected 35 U.S.C. § Reference(s)/Basis A 1-3, 7-13, 15-25 103 Aviles, Singh B 4-6 103 Aviles, Singh, Sabaa C 14 103 Aviles, Singh, Harlamert II ISSUES AND ANALYSIS We have considered all of Appellant’s arguments and any evidence presented. Throughout this opinion, we give the claim limitations the broadest reasonable interpretation (BRI) consistent with the Specification. 3 All reference citations are to the first-named inventor only. Appeal 2020-006105 Application 15/941,381 4 See In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). We highlight and address specific findings and arguments for emphasis in our analysis below. Rejection A of Independent Claim 1 At the outset, and based upon our review of the Final Action, we find the Examiner’s mappings of the disputed claim limitations to the corresponding features found in the cited references are sometimes unclear. Generally, the Examiner adopts a pattern of underlining some portion of the claim language, followed by reproduction of multiple copy-and-paste portions of the reference, which makes it difficult for the Board (and Appellant) to discern the Examiner’s intended mapping of specific claim limitations to the corresponding features found in the cited references.4 And because the Examiner has combined independent claims 1, 11, 16, and 21 into a single “composite” mapping, the lack of clarity in the Examiner’s findings is exacerbated by the merged form of the rejection. See e.g., Final Act. 3-9. Limitation L1 of Claim 1 [L1] logic circuitry to couple with receive buffers to compare a first incoming packet to a first digest in a first entry of a primary array to determine whether the first incoming packet matches the first digest; (emphasis added). 4 We note mapping rule requires: “When a reference is complex or shows or describes inventions other than that claimed by the applicant, the particular part relied on must be designated as nearly as practicable. The pertinence of each reference, if not apparent, must be clearly explained and each rejected claim specified.” 37 C.F.R. § 1.104(c)(2) (2019) (emphasis added). Appeal 2020-006105 Application 15/941,381 5 We note that limitation L1 of independent claim 1 is recited in similar form in each of remaining independent claims 11, 16, and 21. Regarding the disputed L1 limitation, Appellant understands the Examiner’s rejection as reading the claimed “primary array” on pattern memory 510, as depicted in Figure 5 of Aviles. See Appeal Br. 5. This reading of the claimed “primary array” on pattern memory 510 of Aviles (Figure 5) is confirmed by the Examiner in the Answer, who finds: pattern memory 510 (Primary array) stores a digest (where ‘digest’ refers to subset of the matching criteria of the full matching criteria as per [A]ppellant’s disclosures at least in [Spec.] ¶0020) in [Aviles’] local memory 522, indexed by the data structure pointer value 532 which corresponds to [a] pattern and an associated ID provided by the pattern memory 510 (Primary array). See further ¶0031-¶0033 & ¶0037, Aviles. Ans. 7 (emphasis added). See also Final Act. 4, last 6 lines on page. Appellant references Figure 5 of Aviles and contends: With respect to pattern memory 510, Aviles states “the pattern memory 510 that stores the ‘possible match’ patterns.” Aviles, Paragraph [0030]. Aviles further states “[a]t the pattern memory 510, the address 509 is applied as an index to retrieve, for each address, a corresponding pattern and an associated ID or data structure pointer value 532.” Aviles, Paragraph [0033]. Aviles makes clear, from these and other statements, that the pattern memory 510 stores a matching pattern. There is no mention in the cited portions of Aviles of the pattern memory 510 storing a digest for the matching pattern. Consequently, the “logic circuitry to couple with receive buffers to compare a first incoming packet to a first digest in a first entry of a primary array to determine whether the first incoming packet matches the first digest” as recited in claim 1 [limitation L1] cannot read on the pattern memory 510 of Aviles. Appeal 2020-006105 Application 15/941,381 6 Appeal Br. 5-6 (emphasis added). Claim Construction of the Claim Term “digest” As an initial matter of claim construction of the claim 1 term “digest” under its broadest reasonably interpretation (“BRI”), we must provide “an interpretation that corresponds with what and how the inventor describes his invention in the specification, i.e., an interpretation that is ‘consistent with the specification.’” In re Smith Int’l, Inc., 871 F.3d 1375, 1383 (Fed. Cir. 2017) (citations omitted). Because the term “digest” is defined in claim 1 according to its location (“in a first entry of a primary array”), instead being defined by its data content, we turn to the Specification for additional context: In general, embodiments may comprise search acceleration logic circuitry on a network interface, such as a NIC, to match incoming packets with arrays of entries that describe incoming packets and the memory locations at which to store data from the incoming packets. More specifically, embodiments may store an entry with a tag and some metadata in a primary array and a full entry with full matching criteria, or data, and a memory location for a buffer entry in a secondary array. Considering the cache is designed specifically to operate on linked lists, in some embodiments, the primary array may store the tag, the next pointer, and a subset of the matching criteria in the entry of the primary array. This subset of the matching criteria is a “digest” of the full matching criteria. In some embodiment, the digest may be more than just a subset of the full matching criteria and may include, for instance, combined portions of the full matching criteria to compress some of the bits in the full matching criteria. The full matching criteria may be impractical to store in the primary array because of the size (~32 bytes). Spec. ¶ 12 (emphasis added). Appeal 2020-006105 Application 15/941,381 7 The digest may comprise selected portions of the full matching criteria (or data) to identify one of the incoming packets 414, combined portions of the full matching criteria, a hash of at least a portion of the full matching criteria, an encoding of the full matching criteria, randomly-selected portions of the full matching criteria, a summary of bits of the full matching criteria, or a combination thereof. Spec. ¶ 35 (emphasis added). We find the supporting descriptions in the Specification to be non- limiting and exemplary. Given this context, and consistent with the Specification, we interpret the claim term “digest” under BRI as being any subset of packet data, or description of packet data (e.g., metadata), or hash of packet data that is used in any manner for comparing with incoming packets to discern matches (emphasis added). Turning to the evidence, we must be mindful there is no requirement in an obviousness analysis for the prior art to “contain a description of the subject matter of the appealed claim in ipsissimis verbis.” In re May, 574 F.2d 1082, 1090 (CCPA 1978). Thus, the Examiner is not required to show that the literal term “digest” is found in the cited references. Paragraph 30 of Aviles expressly describes that Figure 5 depicts “operation of a perfect hashing memory index inspection module 500 for rapidly inspecting incoming packets for matching patterns and specifying a memory location for any matching patterns that is used by the cache policy process/host processor 520 to make cache decisions.” (emphasis added). This is similar to Appellant’s dependent claim 5 which expressly incorporates a hash function: “wherein the first digest comprises at least one of combined portions of the data to identify the first incoming packet, selected portions of the data to identify the first incoming packet, a hash of Appeal 2020-006105 Application 15/941,381 8 at least a portion of the data to identify the first incoming packet, . . . .” (emphasis added). Given the evidence cited by the Examiner in Aviles, and given the absence of a limiting definition for the claim term “digest” in the claim or Specification, on this record we are not persuaded the Examiner erred regarding disputed limitation L1 of claim 1. See Final Act. 3-4. We reach the same conclusion for the similar language of commensurate scope recited in each of remaining independent claims 11, 16, and 21. Remaining Conditional Limitations L2-L5 of Claim 1 [L2] when the first incoming packet matches the first digest, the logic circuitry to retrieve a first full entry from a secondary array, the first full entry to correspond to the first entry, and to compare the first full entry with the first incoming packet; [L3] when the first full entry matches the first incoming packet, the logic circuitry to store at least a portion of the first incoming packet at a first memory location, [L4] wherein entries in the secondary array comprise at least data and a memory location at which to store at least a portion of one of the incoming packets; and [L5] in absence of a match between the first incoming packet and the first digest or between the first incoming packet and the first full entry, the logic circuitry to compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet. Claim 1 (emphasis added). Appeal 2020-006105 Application 15/941,381 9 The Examiner’s Mapping of Limitations L2-L5 of Claim 1 The Examiner appears to map the first recited “when” conditional limitation L2 of independent apparatus claim 1 to Aviles at paragraphs 18, 30, and 37, and Figure 5 (emphasis added). See Final Act. 4-5. Regarding the disputed L3 limitation “when the first full entry matches the first incoming packet” conditional function of claim 1, and the disputed “wherein” clause limitation L4 of claim 1, the Examiner appears to find limitations L3 and L4 are taught or suggested by Aviles, generally at paragraphs 12, 15, 18, 30, and Figures 3, 5, and 6 (emphasis added). See Final Act. 5-6. Regarding the disputed “in the absence of a match” clause L5 of independent claim 1, the Examiner finds this limitation is taught or suggested by Singh, at Figures 4, 5, 7 and paragraphs 47, 53, 60, and 69 (emphasis added). See Final Act. 7-8. Motivation to Combine the References For Rejection A of claim 1, the Examiner finds an artisan would have been motivated to modify the teachings of Aviles with the teachings of Singh “to facilitate [the] fast and reliable delivery of data, network packets, from one system to another.” Final Act. 9 (citing Singh Abstract, ¶ 2)). Independent Claims 1 and 16 Although Appellant disputes the Examiner’s factual findings regarding each of the claim 1 limitations L1-L5, based upon our review of Appeal 2020-006105 Application 15/941,381 10 the record, we find that “wherein” clause limitation L4 is dispositive for independent claims 1 and 16, for the reasons discussed infra. We focus our analysis on the disputed “wherein” clause limitation L4 of claim 1: [L4] wherein entries in the secondary array comprise at least data and a memory location at which to store at least a portion of one of the incoming packets; Claim 1 (emphasis added). We note that independent claim 16 recites identical “wherein” clause language corresponding to “wherein” clause L4 of claim 1. The Examiner reads the claimed “secondary array” on shift register 502, as depicted at the top of Figure 5 of Aviles. See Final Act. 4; Ans. 7. We note that limitation L4 of claim 1 expressly requires at least two things to be present for each entry in the secondary array: (1) “data” and (2) “a memory location at which to store at least a portion of one of the incoming packets.” (emphasis added). Thus, we interpret under BRI that “wherein” clause limitation L4 requires each entry in the claimed “secondary array” to store: (1) data, and (2) an address pointer that points to a memory location “to store at least a portion of one of the incoming packets.” Claim 1 (emphasis added). More specifically regarding “wherein” limitation L4 of claim 1, Appellant urges: In fact, Aviles fails to describe any of the memory structures in FIG. 5 (i.e., pattern memory 510 and local memory 522) as storing a memory location that is actually used to store incoming packet data 501 upon a match. Consequently, “when the first full entry matches the first incoming packet, the logic circuitry to store at least a portion of the first incoming packet Appeal 2020-006105 Application 15/941,381 11 at a first memory location, wherein entries in the secondary array comprise at least data and a memory location at which to store at least a portion of one of the incoming packets” as recited in claim 1 cannot read on the shift register 502 (or any other memory structure) of Aviles. Appeal Br. 7 (emphasis added). In support, Appellant contends: Aviles states that “each incoming packet data 501 is shifted into the serial-in parallel-out shift register 502.” Aviles, Paragraph [0030]. From this statement, it is clear that Aviles uses the shift register 502 to store bits from an incoming packet. The cited portions of Aviles do not indicate that the shift register 502 stores any other information except that from the incoming packet. It therefore follows that the shift register 502 does not store a memory location to store an incoming packet. Appeal Br. 7 (emphasis added). Based upon our review of the portions of Aviles cited by the Examiner for purportedly teaching or suggesting limitation L4 of claim 1, we find a preponderance of the evidence supports Appellant’s arguments. See Id. Nor has the Examiner fully developed the record to show that any portion of the secondary Singh references overcomes the deficiency of Aviles regarding at least the “wherein” clause limitation L4 of claim 1. We note the Examiner relies primarily upon Singh to teach or suggest limitation L5 of claim 1. Because independent claim 16 recites the “wherein” clause limitation L4 of claim 1 using identical language, we are constrained on this record to reverse Rejection A of independent claims 1 and 16 on appeal. Appeal 2020-006105 Application 15/941,381 12 Remaining independent claims 11 and 21 We note that independent claims 11 and 21 are silent regarding the “wherein” clause limitation recited in independent claims 1 and 16, as discussed above. However, both claims 11 and 21 recite a similar use of the claimed “secondary array:” when the first incoming packet matches the digest of the first entry in the primary array, retrieving, by the search acceleration logic circuitry, a first full entry from a secondary array, the first full entry to correspond to the first entry, and comparing the first full entry with the first incoming packet; when the first full entry matches the first incoming packet, storing, by the search acceleration logic circuitry, at least a portion of the first incoming packet at the first memory location; and Claim 11 (emphasis added). when the first incoming packet matches the digest of the first entry in the primary array, retrieving a first full entry from a secondary array, the first full entry to correspond to the first entry, and comparing the first full entry with the first incoming packet; when the first full entry matches the first incoming packet, storing at least a portion of the first incoming packet at the first memory location; Claim 21 (emphasis added). Based upon our review of the record, we find Appellant’s previous arguments are also applicable to independent claims 11 and 21, given that the Examiner reads the claimed “secondary array”’ on Aviles’ shift register 502, as depicted in Figure 5, and for the following argued reason: Appeal 2020-006105 Application 15/941,381 13 it is clear that Aviles uses the shift register 502 to store bits from an incoming packet. The cited portions of Aviles do not indicate that the shift register 502 stores any other information except that from the incoming packet. It therefore follows that the shift register 502 does not store a memory location to store an incoming packet. Appeal Br. 7 (emphasis added). However, regarding the argued “memory location to store an incoming packet” (id.) (which is alternatively referenced in claims 11 and 21 as “the first memory location”), we do not see any clear antecedent basis for the term “the first memory location,” as recited in independent claim 11 and independent claim 21. Therefore, in the event of further prosecution (including any review prior to allowance), we bring this lack of antecedent basis issue to the attention of the Examiner. Prior to allowance, the Examiner should consider whether independent claims 11 and 21 sufficiently apprise one of ordinary skill in the art of their scope, in the context of the notice function of 35 U.S.C. § 112(b), to provide clear warning to others as to what constitutes infringement. See Solomon v. Kimberly-Clark Corp., 216 F.3d 1372, 1379 (Fed. Cir. 2000). If the language of the claim is such that a person of ordinary skill in the art could not interpret the metes and bounds of the claims to avoid infringement, then a rejection of the claim under 35 U.S.C. § 112(b) is deemed appropriate. 5 See Morton Int’l, Inc. v. Cardinal Chemical Co., 5 F.3d 1464, 1470 (Fed. Cir. 1993). 5 Although the Board is authorized to reject claims under 37 C.F.R. § 41.50(b), no inference should be drawn when the Board elects not to do so. See Manual of Patent Examining Procedure (MPEP) § 1213.02 (9th ed. Rev. 10.2019, rev. June 2020). Appeal 2020-006105 Application 15/941,381 14 Although we are constrained on this record to reverse Rejection A of independent claims 11 and 21 on appeal, we nevertheless leave it to the Examiner to address the lack of antecedent basis identified above by making a new ground of rejection under 35 U.S.C. § 112(b), or by an Examiner’s amendment prior to allowance, as coordinated with Appellant. In reversing the Examiner’s rejection of all independent claims 1, 11, 16, and 21 under Rejection A, we have also considered the recited conditional limitations in the context of considering each claim as a whole. 6 We find the Examiner has not fully developed the record to show how the conditional limitations recited in each independent claim are taught or suggested by the cited combination of Aviles and Singh under Rejection A. We additionally note that independent claim 11 is a method claim that recites several conditional limitations. The limited holding of Schulhauser applies only to two specific categories of claims: method claims and means- plus-function claims, and each category is treated differently. See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential). 6 See Hockerson-Halberstadt, Inc. v. Converse Inc., 183 F.3d 1369, 1374 (Fed. Cir. 1999) (“proper claim construction ... demands interpretation of the entire claim in context, not a single element in isolation.”); ACTV, Inc. v. Walt Disney Co., 346 F.3d 1082, 1088 (Fed. Cir. 2003) (“While certain terms may be at the center of the claim construction debate, the context of the surrounding words of the claim also must be considered....”). Appeal 2020-006105 Application 15/941,381 15 Here, we find Schulhauser is inapplicable to independent method claim 11, because both possible outcomes (match or no match) of each recited condition precedent are positively recited. Rejections A, B, and C of Remaining Dependent Claims Regarding the remaining dependent claims 2-10, 12-15, 17-20, and 22-25, as rejected under Rejections A, B, and C, we find the Examiner has not shown how any of the additionally cited secondary references overcomes the aforementioned deficiencies of the base combination of Aviles and Singh, as discussed above regarding Rejection A of independent claims 1, 11, 16, and 21. Therefore, we are constrained on this record to also reverse Rejections A, B, and C of remaining dependent claims 2-10, 12-15, 17-20, and 22-25. CONCLUSION The Examiner erred in rejecting claims 1-25 under 35 U.S.C. § 103, over the collective teachings and suggestions of the cited references. Appeal 2020-006105 Application 15/941,381 16 DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1-3, 7-13, 15-25 103 Aviles, Singh 1-3, 7-13, 15-25 4-6 103 Aviles, Singh, Sabaa 4-6 14 103 Aviles, Singh, Harlamert II 14 Overall Outcome 1-25 REVERSED