2019002275 (P.T.A.B. Jul. 16, 2020)

INTEL CORPORATION

Patent Trials and Appeals BoardJul 16, 2020

2019002275 (P.T.A.B. Jul. 16, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/139,716 12/23/2013 JAMES M. HOLLAND P60140/1020P60140 6723 57035 7590 07/16/2020 KACVINSKY DAISAK BLUNI PLLC 2601 Weston Parkway Suite 103 Cary, NC 27513 EXAMINER WERNER, DAVID N ART UNIT PAPER NUMBER 2487 NOTIFICATION DATE DELIVERY MODE 07/16/2020 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docketing@kdbfirm.com intel@kdbfirm.com kpotts@kdbfirm.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte JAMES M. HOLLAND, ATTHAR H. MOHAMMED, and SRINIVASAN EMBAR RAGHUKRISHNAN Appeal 2019-002275 Application 14/139,716 Technology Center 2400 Before MAHSHID D. SAADAT, LINZY T. McCARTNEY, and JESSICA C. KAISER, Administrative Patent Judges. McCARTNEY, Administrative Patent Judge. DECISION ON APPEAL Appellant1 seeks review under 35 U.S.C. § 134(a) of the Examiner’s final rejection of claims 1–4, 7–16, and 18–25. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. 1 Appellant identifies the real party in interest as Intel Corporation. Appeal Brief 2, filed October 9, 2018 (Appeal Br.). Appeal 2019-002275 Application 14/139,716 2 BACKGROUND This patent application concerns “motion estimation of media that contain multiple image frames.” Specification ¶ 15, filed December 23, 2013. Claim 1 illustrates the claimed subject matter: 1. An apparatus, comprising: a memory to receive an image frame to encode; and a modular motion estimation engine to process the image frame, the modular motion estimation engine comprising: modular motion estimation circuitry comprising a multiplicity of individually addressable motion estimation circuits, the one or more motion estimation circuits to process the image frame by comparing a macroblock within the image frame to a block of a reference frame or reference frames using a block matching algorithm, the modular motion estimation circuitry comprising a multiplicity of individually addressed entry points to receive the macroblock and a multiplicity of exit points to generate motion estimation output for the macroblock; and a motion estimation kernel comprising instructions stored on a nontransitory computer-readable storage medium for execution on the modular motion estimation circuitry to send the image frame through one or more configurable execution pipelines that each executes motion estimation over one or more of the motion estimation circuits. Appeal Br. 14. Appeal 2019-002275 Application 14/139,716 3 REJECTION Claims 35 U.S.C. § References 1–4, 7–16, 18–25 103 Chou,2 Lu3 DISCUSSION Claim 1 recites “modular motion estimation circuitry comprising a multiplicity of individually addressable motion estimation circuits.” Appeal Br. 14. The Examiner found “the Chou reference to teach the claimed individually addressable circuits” because Chou discloses a “parallel embodiment in which the processing pipeline may be implemented in a multiplicity of parallel pipelines,” each pipeline component including a “macroblock motion estimation unit.” Examiner’s Answer 9, mailed November 23, 2018 (emphases and reference numbers omitted) (citing Chou ¶ 38); see also Final Office Action 6, mailed September 7, 2017. Appellant argues that the Examiner erred because the cited parts of Chou teach “that there may be multiple pipelines, that is, multiple whole pipelines that may be run in parallel. The reference does not describe that components of [the] whole pipeline may [be] individually addressed and/or run in parallel.” Reply Brief 4, filed January 23, 2019 (emphasis omitted). Appellant has persuaded us that the Examiner erred. As found by the Examiner, Chou teaches that “[e]mbodiments of the block processing methods and apparatus as described herein may be implemented in two or more parallel block processing pipelines.” Chou ¶ 38. But even assuming that Chou’s processing pipelines include “motion estimation circuits” as found by the Examiner, the Examiner has not adequately explained why 2 Chou et al. (US 2015/0092855 A1; April 2, 2015). 3 Lu et al. (US 2009/0168883 A1; July 2, 2009). Appeal 2019-002275 Application 14/139,716 4 processing these pipelines in parallel teaches or suggests that these circuits are “individually addressable” as required by the disputed limitation. That Chou’s pipelines can be implemented in parallel does not show that the components that make up the pipelines are “individually addressable.” We thus do not sustain the Examiner’s rejection of claim 1 and its dependent claims under § 103. Because the Examiner’s rejection of independent claims 14 and 21 and their respective dependent claims under § 103 has similar flaws, we also do not sustain this rejection. CONCLUSION The following table summarizes our decision for claims 1–4, 7–16, and 18–25, the claims before us on appeal: Claims Rejected 35 U.S.C. § References/Basis Affirmed Reversed 1–4, 7–16, 18– 25 103 Chou, Lu 1–4, 7–16, 18–25 REVERSED