2019004590 (P.T.A.B. Jan. 6, 2021)

Intel Corporation

Patent Trials and Appeals BoardJan 6, 2021

2019004590 (P.T.A.B. Jan. 6, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/408,222 01/17/2017 Ravishankar RAO P112270C 1098 131413 7590 01/06/2021 NDWE LLP/Intel 99 Almaden Boulevard, Suite 710 San Jose, CA 95113 EXAMINER MAMO, ELIAS ART UNIT PAPER NUMBER 2184 NOTIFICATION DATE DELIVERY MODE 01/06/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ndwe_docketing@cardinal-ip.com patent@ndwe.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte RAVISHANKAR RAO and NISHIT SHAH ____________ Appeal 2019-004590 Application 15/408,222 Technology Center 2100 ____________ Before KARA L. SZPONDOWSKI, SCOTT B. HOWARD, and STEVEN M. AMUNDSON, Administrative Patent Judges. SZPONDOWSKI, Administrative Patent Judge. DECISION ON APPEAL Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s Final Rejection of claims 1–7 and 15–24, which constitute all of the claims pending in this application. We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM. 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies the real party in interest as Intel Corporation. Appeal Br. 2. Appeal 2019-004590 Application 15/408,222 2 STATEMENT OF THE CASE Appellant’s invention relates generally to “microprocessor architecture,” and particularly “to the architecture of critical structures for microprocessors.” Spec. ¶ 2. Typically, microprocessors “have several small critical structures” that “are organized as set-associative structures with several levels of hierarchy for each structure.” Id. ¶ 3. The Specification explains that “a need exists for a method and apparatus for a more efficient and flexible processor architecture that reduces the penalty of accessing higher level structures and increases temporal locality within the lower level structures.” Id. ¶ 9. Appellant’s invention endeavors to “reduce[] the penalty of accessing higher level structures by implementing a transient buffer between a higher level structure, e.g., a L2 cache, and a lower level structure, e.g., a L1 cache to store entries that are incoming from the higher level structure.” Id. Claim 1, reproduced below, is representative of the claimed subject matter: 1. A method for preventing non-temporal entries from entering small critical structures, said method comprising: receiving data from a higher level memory structure at an intermediate buffer, the higher level memory structure having a higher latency relative to a processor than the intermediate buffer; determining an entry to be evicted from the intermediate buffer that has been frequently accessed, in response to receiving the data from the higher level memory; sending a value in the determined entry to a lower level memory structure, the lower level memory structure having a lower latency relative to the processor than the intermediate buffer; and Appeal 2019-004590 Application 15/408,222 3 storing the data in the determined entry of the intermediate buffer. REJECTIONS Claims 1–3, 6, 7, and 15–24 stand rejected under 35 U.S.C. § 103 as unpatentable over Jeddeloh (US 2002/0042863 A1; published Apr. 11, 2002), Balakrishnan et al. (US 2010/0274973 A1; published Oct. 28, 2010) (“Balakrishnan”), and Eddy et al. (US 2010/0064107 A1; published Mar. 11, 2010) (“Eddy”). Final Act. 2. Claims 4 and 5 stand rejected under 35 U.S.C. § 103 as unpatentable over Jeddeloh, Balakrishnan, and Eddy, and further in view of Official Notice. Final Act. 5–6. ANALYSIS Section 103 Rejections Independent Claims 1 and 15 Issue: Did the Examiner err in finding that the combination of Jeddeloh, Balakrishnan, and Eddy teaches or suggests “determining an entry to be evicted from the intermediate buffer that has been frequently accessed, in response to receiving the data from the higher level memory” and “sending a value in the determined entry to a lower level memory structure,” as recited in independent claim 1 and commensurately recited in independent claim 15? The Examiner relies on the combination of Balakrishnan and Eddy to teach the foregoing limitations. Final Act. 3. Appellant argues that Balakrishnan “swap[s] cache entries between banks so that they are closer to processors that are likely to request the respective cache entries.” Appeal Br. 5. Specifically, Appellant argues that Balakrishnan’s “cache banks . . . are not higher or lower levels of a hierarchy of a cache,” but rather “are Appeal 2019-004590 Application 15/408,222 4 lateral to one another, i.e., in the same level.” Id.; see also Appeal Br. 6–8. Appellant, therefore, argues that “Balakrishnan has not been shown to have any relevant disclosure related to eviction processes where cache lines are moved between levels of a memory hierarchy.” Id. at 8. With regard to Eddy, Appellant argues that “the cited sections of Eddy describe a process of evicting entries in the low level (L1) cache to be sent to the higher level (L2) cache. Id. at 6. We are not persuaded by Appellant’s arguments. Appellant’s arguments address Balakrishnan and Eddy in isolation, rather than as combined by the Examiner. One cannot show non-obviousness by attacking references individually, where the rejections are based on combinations of references. In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986); In re Keller, 642 F.2d 413, 425 (CCPA 1981). We agree with the Examiner’s findings that Balakrishnan teaches “installing cache entry into a . . . memory structure responsive to a determination that said entry is frequently accessed”; and that Eddy teaches “cache line eviction between higher (L2) and lower level (L1) memory.” Final Act. 3 (citing Balakrishnan ¶¶ 37, 53; Eddy ¶¶ 2, 22, 33); see also Ans. 4–5. Balakrishnan discloses “cache operations” including “eviction or replacement.” Balakrishnan ¶ 37. Balakrishnan further discloses that “cache controller” may “replace or evict cache data . . . to move more frequently accessed data/instructions to positions closer to a processor or core.” Id. As a result, in Balakrishnan, “each processor can access the block with reduced latency.” Id. Eddy discloses an “eviction engine . . . that manages cache line eviction operations from a lower level cache memory to a higher level cache memory in a cache memory hierarchy of the microprocessor 100.” Eddy ¶ 22. We, therefore, Appeal 2019-004590 Application 15/408,222 5 agree with the Examiner that Balakrishnan teaches determining an entry to be evicted that has been frequently accessed; and Eddy teaches evicting between different levels of cache memory. Appellant further argues that “none of the cited references have been shown to disclose a process where frequently accessed cache lines in an intermediate buffer are moved to a lower level, in response to receiving data from a higher level of a memory hierarchy.” Appeal Br. 7. Specifically, Appellant argues that “Eddy and Jeddeloh disclose systems that do the opposite [to what is claimed], moving evicted lines to higher levels and Balakrishnan discloses swaps within a level.” Appeal Br. 7. We are not persuaded by Appellant’s arguments. The Examiner finds that Eddy’s cache lines are moved from higher level cache to lower level cache. Ans. 5 (citing Eddy ¶ 43). As cited by the Examiner (Ans. 5), Eddy’s “lower level cache memory is an L1 cache data array and tag array,” and Eddy’s “higher level cache memory is an L2 cache data array and tag array.” Eddy ¶ 22. Eddy discloses that an allocation engine “allocates a cache line in the L1 cache . . . reads the missing cache line [] from the L2 cache . . . and writes the cache line [] to the L1 cache.” Id. ¶ 43. Appellant does not address these findings by the Examiner. Appellant also argues that “any combination of Balakrishnan, Eddy and Jeddeloh would alter the fundamental operating principle of the references and is not the simple combination of known elements.” Appeal Br. 8. Specifically, Appellant argues that the references “relate to different types of memory architectures,” which “are not equivalent or readily combinable.” Id. Appellant also argues that there is no “clearly articulate[d] Appeal 2019-004590 Application 15/408,222 6 rationale as to how or why one skilled in the art would combine the various elements” of the references. Id. We are not persuaded by Appellant’s arguments. Appellant’s argument is essentially an argument against the bodily incorporation of Eddy and Jeddeloh into Balakrishnan. However, the test for obviousness is not whether the features of one reference may be bodily incorporated into another reference. Rather, the relevant inquiry is whether the claimed subject matter would have been obvious to those of ordinary skill in the art in light of the combined teachings of those references. Keller, 642 F.2d at 425. As described above, Balakrishnan teaches determining an entry to be evicted that has been frequently accessed. See Balakrishnan ¶ 37. Eddy teaches managing cache line evictions between different levels of cache memory. See Eddy ¶ 22. The Examiner relies on Jeddeloh to teach storing data received from a cache memory in an intermediate buffer. See Final Act. 2–3 (citing Jeddeloh ¶¶ 17, 19). As proposed by the Examiner, the combination would result in utilizing Jeddeloh’s cast-out cache acting as an intermediate buffer; employing Balakrishnan’s method of determining an entry to be evicted based on frequency of access; and employing Eddy’s method of eviction between different levels of cache memory. See Final Act. 2–4; Ans. 4–5. The Examiner finds “[t]he motivation for [the combination] would have been [so] each processor can access a data block with reduced latency.” Final Act. 4; see also Ans. 7. We find the Examiner has articulated how the claimed features are met by the proposed combination of reference teachings with some rational underpinning consistent with the guidelines stated in KSR International Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). Appellant has not persuasively argued why Appeal 2019-004590 Application 15/408,222 7 the Examiner’s reasoning is in error. Nor has Appellant provided evidence that combining the teachings was “uniquely challenging or difficult for one of ordinary skill in the art,” or that such a combination “represented an unobvious step over the prior art.” Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007). Thus, we agree with the Examiner’s finding the combination of Jeddeloh, Balakrishnan, and Eddy teaches “determining an entry to be evicted from the intermediate buffer that has been frequently accessed, in response to receiving the data from the higher level memory” and “sending a value in the determined entry to a lower level memory structure, the lower level memory structure having a lower latency relative to the processor than the intermediate buffer,” as recited by claim 1. Claim 15 recites an apparatus that performs steps that are commensurate in scope to the limitations of claim 1 and includes “an intermediate buffer coupled to the low level memory structure . . . having a latency that is lower than the memory.” Appeal Br. 15, Claims App. Appellant argues that the cited references do not “disclose an intermediate buffer positioned as described” in claim 15. Appeal Br. 11. Specifically, Appellant argues that the claimed apparatus “sets forth [that] the intermediate buffer is positioned with a latency between that of the lower level memory and the (higher level) memory.” Id. We are not persuaded by Appellant’s arguments. The Examiner finds that Jeddeloh’s “intermediate buffer (i.e.[, ]cast-out-cache 202) is positioned with a latency between that of the lower level memory and the (higher level) memory (i.e.[, ]with a shorter latency than a full memory access).” Ans. 12 (citing Jeddeloh ¶ 17). Jeddeloh discloses “a memory buffer for the storage Appeal 2019-004590 Application 15/408,222 8 of cache lines flushed—cast out—from a processor’s L1 and/or L2 caches (hereinafter referred to as cast-out cache []).” Jeddeloh ¶ 17, code (57). Jeddeloh’s cast-out cache allows for “[s]ubsequent reads to cache lines stored in cast-out cache [to] be returned to the processor without incurring the latency associated with a full memory access.” Id. In other words, Jeddeloh’s cast-out cache is positioned to have latency lower than the memory. Appellant does not dispute the Examiner’s finding. Thus, on this record, we are not persuaded the Examiner erred in finding that Jeddeloh teaches “intermediate buffer coupled to the low level memory structure . . . having a latency that is lower than the memory,” as recited by claim 15. Accordingly, we sustain the Examiner’s § 103 rejection of independent claims 1 and 15. Dependent Claim 2 Claim 2 further recites “wherein the higher level memory structure is a Level 2 cache memory.” Appeal Br. 17, Claims App. Appellant argues that the Examiner’s reliance on Jeddeloh for claim 2 “is inconsistent with the other reliance on Jeddeloh where the cast-out cache 202 is equated with the intermediate buffer.” Appeal Br. 8–9. The Examiner finds that Jeddeloh’s teaching that a computer system “incorporates an L1 cache structure” and includes an “L2 cache unit,” as well as Eddy’s evicting cache lines between higher level L2 cache memory and lower level L1 cache memory, teaches or suggests the claimed higher level memory structure is a Level 2 cache memory. See Ans. 7–8 (citing Jeddeloh ¶ 22; Eddy ¶ 43); Final Act. 4. Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 2. Appeal 2019-004590 Application 15/408,222 9 Dependent Claim 3 Claim 3 further recites “wherein the lower level memory structure is any one of a L1 data cache memory, a L1 instruction cache memory and a conversation lookaside buffer.” Appeal Br. 17, Claims App. Appellant argues that the Examiner’s reliance on Jeddeloh for claim 3 “is inconsistent with the other reliance on Jeddeloh where the cast-out cache is equated with the intermediate buffer.” Appeal Br. 9. The Examiner finds that Jeddeloh’s teaching that a computer system “incorporates an L1 cache structure” and includes an “L2 cache unit,” as well as Eddy’s evicting cache lines between higher level L2 cache memory and lower level L1 cache memory, teaches or suggests the claimed lower level memory structure includes an L1 cache structure. See Ans. 8 (citing Jeddeloh ¶ 22; Eddy ¶ 43); Final Act. 4. Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 3. Dependent Claims 4 and 5 Appellant does not separately argue patentability for dependent claims 4 and 5. Therefore, we sustain the Examiner’s § 103 rejection of dependent claims 4 and 5. Dependent Claim 6 Claim 6 further recites “wherein the determining is based on a replacement policy, wherein the replacement policy is any one of an access counter based replacement policy, a least-recently used replacement policy and a random replacement policy.” Appeal Br. 18, Claims App. Appeal 2019-004590 Application 15/408,222 10 Appellant argues that the Examiner “has not identified the specific elements that are asserted to disclose each of the elements of this claim.” Appeal Br. 9. The Examiner finds that Jeddeloh’s “select[ing] cast-out cache entry [to] be flushed” when the cast-out cache is full, employing a “cache line replacement algorithm,” such as “a least recently used (LRU) algorithm” to “select that cast-out cache entry for removal []block” teaches the claimed limitation. Jeddeloh ¶ 19; see Ans. 9 (citing Jeddeloh ¶ 19); Final Act. 4. Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 6. Dependent Claim 7 Claim 7 further recites “discarding another entry in the intermediate buffer where an access count of the other entry is below a discard threshold.” Appeal Br. 18, Claims App. Appellant argues that the Examiner “has not identified the specific elements that are asserted to disclose each of the elements of this claim.” Appeal Br. 10. The Examiner finds that Balakrishnan’s “finding a pair of banks that may benefit from swapping data of the caches lines,” such as “benefit detection logic” and “data fill logic” working “to buffer the data of a cache line,” teaches the disputed claim limitation. Balakrishnan ¶ 38; see Ans. 10 (citing Balakrishnan ¶ 38); Final Act. 5. Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 7. Appeal 2019-004590 Application 15/408,222 11 Dependent Claim 16 Claim 16 further recites “Level 2 cache memory having a latency that is higher than the intermediate buffer and lower than the memory.” Appeal Br. 19, Claims App. Appellant argues that the Examiner’s reliance on Jeddeloh for claim 2 “is inconsistent with the other reliance on Jeddeloh where the cast-out cache is equated with the intermediate buffer.” Appeal Br. 11. The Examiner finds that Jeddeloh’s cast-out cache, as the intermediate buffer, “is positioned with a latency between that of the lower level memory and the (higher level) memory (i.e.[, ]with a shorter latency than a full memory access).” Ans. 13 (citing Jeddeloh ¶ 17, Fig. 5); Final Act. 5. Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 16. Dependent Claim 17 Claim 17 further recites “wherein the lower level memory structure is any one of a L1 data cache memory, a L1 instruction cache memory and a conversion lookaside buffer.” Appeal Br. 19, Claims App. Appellant argues that the Examiner’s reliance on Jeddeloh for claim 3 “is inconsistent with the other reliance on Jeddeloh where the cast-out cache is equated with the intermediate buffer.” Appeal Br. 11–12. The Examiner relies on Jeddeloh’s teaching that a computer system “incorporat[es] an L1 cache structure” and includes an “L2 cache unit,” as well as Eddy’s evicting cache lines between higher level L2 cache memory and lower level L1 cache memory, teaches or suggests the claimed lower level memory structure includes an L1 cache structure. Jeddeloh ¶ 22; see Ans. 14 (citing Jeddeloh ¶ 22; Eddy ¶ 43); Final Act. 5. Appeal 2019-004590 Application 15/408,222 12 Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 17. Dependent Claim 18 Claim 18 further recites “wherein said the intermediate buffer includes confidence logic to discard the second block responsive to a determination that the second block is not frequently accessed.” Appeal Br. 19, Claims App. Appellant argues that the Examiner “has not provided any specific citation to the cited references for these elements, specifically ‘confidence logic.’” Appeal Br. 12. The Examiner finds that Jeddeloh’s least recently used (LRU) algorithm teaches the claimed confidence logic to discard blocks that are not frequently accessed. See Ans. 14–15 (citing Jeddeloh ¶¶ 7, 19); Final Act. 5. Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 18. Dependent Claim 19 Claim 19 further recites “wherein the confidence logic compares an access counter of the second block to a threshold to move the second block to the lower level memory structure.” Appeal Br. 19, Claims App. Appellant argues that the Examiner “has not provided any specific citation to the cited references for these elements, specifically ‘confidence logic.’” Appeal Br. 12. The Examiner finds that the combination of Jeddeloh and Balakrishnan teaches confidence logic that considers “reorganiz[ing] data after a certain number of cache accesses,” and teaches or suggests the Appeal 2019-004590 Application 15/408,222 13 disputed limitation. Balakrishnan ¶ 67; see Ans. 15 (citing Balakrishnan ¶ 67); Ans. 14–15 (citing Jeddeloh ¶¶ 7, 19); Final Act. 5. Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 19. Dependent Claim 20 Claim 20 further recites “wherein the replacement logic is configured to determine the second block to be evicted based on a replacement policy, wherein the replacement policy is any one of an access counter based replacement policy, a least-recently used replacement policy and a random replacement policy.” Appeal Br. 19, Claims App. Appellant argues that the Examiner “has not provided any specific citation to the cited references for these elements, specifically ‘replacement logic.’” Appeal Br. 13. The Examiner finds that Jeddeloh’s least recently used (LRU) algorithm teaches the claimed replacement logic to evict blocks based on a least-recently used replacement policy, as required by the claim. See Ans. 16 (citing Jeddeloh ¶ 19); Ans. 14–15 (citing Jeddeloh ¶¶ 7, 19); Final Act. 5. Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 20. Dependent Claim 21 Claim 21 further recites “receiving a fetch at the intermediate buffer simultaneous to the fetch being processed at the lower level memory structure.” Appeal Br. 19, Claims App. Appeal 2019-004590 Application 15/408,222 14 Appellant argues that the Examiner “has not identified the specific elements that are asserted to disclose each of the elements of this claim.” Appeal Br. 10. The Examiner finds that Jeddeloh’s cast-out cache being “updated during memory write operations . . . when either a processor unit or an input- output (I/O) bus master device writes to memory” teaches or suggests the disputed claim limitation. Jeddeloh ¶ 21; see Ans. 10–11 (citing Jeddeloh ¶ 21); Final Act. 5. Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 21. Dependent Claim 22 Claim 22 further recites “sending an entry to the lower level memory structure in response to an access causing an access count to exceed a move threshold.” Appeal Br. 20, Claims App. Appellant argues that the Examiner “has not identified the specific elements that are asserted to disclose each of the elements of this claim.” Appeal Br. 10–11. The Examiner finds that Balakrishnan’s “reorganiz[ing] data after a certain number of cache accesses,” as well as Eddy’s cache line eviction between higher and lower level memory, where the lower level L1 cache memory is the fastest cache to access, teaches or suggests the disputed claim limitation. Balakrishnan ¶ 67; see Ans. 11–12 (citing Balakrishnan ¶ 67; Eddy ¶¶ 2, 22, 33, 43); Final Act. 5. Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 22. Appeal 2019-004590 Application 15/408,222 15 Dependent Claim 23 Claim 23 further recites “wherein the processor sends a fetch to the intermediate buffer simultaneous to the fetch being sent to the lower level memory structure.” Appeal Br. 20, Claims App. Appellant argues that the Examiner “has not identified the specific elements that are asserted to disclose each of the elements of this claim.” Appeal Br. 13. The Examiner finds that Jeddeloh teaches “receiving a fetch at the intermediate buffer (i.e.[, ]updating cast-out cache) simultaneous to the fetch being processed at the lower level memory structure (i.e.[, ]during/while memory write operations).” See Ans. 17 (citing Jeddeloh ¶ 21); Final Act. 5. Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 23. Dependent Claim 24 Claim 24 further recites “wherein the replacement logic and confidence logic are configured to send a third block to the lower level memory structure in response to an access of the third block causing an access count to exceed a move threshold.” Appeal Br. 20, Claims App. Appellant argues that the Examiner “has not identified the specific elements that are asserted to disclose each of the elements of this claim.” Appeal Br. 13–14. The Examiner finds the combination of Jeddeloh, Balakrishnan, and Eddy teaches confidence logic and replacement logic that considers “reorganiz[ing] data after a certain number of cache accesses,” and cache line eviction between a higher level memory and a lower level memory, as required by the claim. Balakrishnan ¶ 67; see Ans. 17–18 (citing Appeal 2019-004590 Application 15/408,222 16 Balakrishnan ¶ 67; Eddy ¶¶ 2, 22, 33, 43); Ans. 14–15 (citing Jeddeloh ¶¶ 7, 19); Final Act. 5. Appellant does not persuasively address the Examiner’s findings. Therefore, we sustain the Examiner’s § 103 rejection of dependent claim 24. CONCLUSION We affirm the Examiner’s rejections of claims 1–7 and 15–24 under 35 U.S.C. § 103. In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1–3, 6, 7, 15–24 103 Jeddeloh, Balakrishnan, Eddy 1–3, 6, 7, 15– 24 4, 5 103 Jeddeloh, Balakrishnan, Eddy, Official Notice 4, 5 Overall Outcome 1–7, 15–24 TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See 37 C.F.R. § 41.50(f) (2018). AFFIRMED