Intel Corporation

Patent Trials and Appeals Board

Jul 30, 2021

2020003811 (P.T.A.B. Jul. 30, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/387,106 12/21/2016 Eliezer Tamir P109027 6810
106448 7590 07/30/2021
PATENT CAPITAL GROUP
30 Flower Lane
Levittown, PA 19055
EXAMINER
METZGER, MICHAEL J
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
07/30/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PAIR_106448@patcapgroup.com
eofficeaction@appcoll.com
inteldocs_docketing@cpaglobal.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte ELIEZER TAMIR and BEN-ZION FRIEDMAN
____________

Appeal 2020-003811
Application 15/387,1061
Technology Center 2100
_______________

Before HUNG H. BUI, NABEEL U. KHAN, and DAVID J. CUTITTA II,
Administrative Patent Judges.

BUI, Administrative Patent Judge.

DECISION ON APPEAL
Appellant seeks our review under 35 U.S.C. § 134(a) from the
Examiner’s final rejection of claims 1–25, all of the pending claims. Appeal
Br. 10–14 (Claims App.). We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.2

1 “Appellant” refers to “applicant[(s)]” as defined in 37 C.F.R. § 1.42.
Appellant identifies Intel Corporation as the real party in interest. Appeal
Br. 1.
2 We refer to the Appellant’s Appeal Brief filed November 12, 2019
(“Appeal Br.”); Reply Brief filed April 24, 2020 (“Reply Br.”); Examiner’s
Answer mailed February 24, 2020 (“Ans.”); Final Office Action mailed June
4, 2019 (“Final Act.”); and Specification filed December 21, 2016 (“Spec.”).
Appeal 2020-003811
Application 15/387,106

2
STATEMENT OF THE CASE
Appellant’s invention relates to “systems and techniques for enabling
collaboration between processing devices (e.g., processing cores) having
different instruction set architectures (ISAs) into a single computing device.”
Spec. ¶ 23.
Claims 1, 11, and 17 are independent claims. Claim 1, reproduced
below with disputed limitations emphasized, is representative:
1. A computing device comprising:
a first processing core having a first instruction set
architecture (ISA);
a second processing core having a second ISA different
from the first ISA;
a data translation processing device, different from the
first processing core and the second processing core; and
a bus coupled to the first processing core, the second
processing core, and the data translation processing device;
wherein the data translation processing device is to
translate data structures compatible with the first ISA into data
structures compatible with the second ISA, the data structures
are part of data generated by a program during execution of the
program by the first processing core, and the translated data
structures are to be used during execution of the program by the
second processing core.

Appeal Br. 10 (Claims App.).

REJECTIONS AND REFERENCES
(1) Claims 1–12, 14–22, 24, and 25 stand rejected under 35 U.S.C.
§ 103 as obvious over the combined teachings of Asai et al. (US
Appeal 2020-003811
Application 15/387,106

3
2009/0144528 A1; published June 4, 2009; “Asai”) and Chen et al. (US
2016/0283438 A1; published Sept. 29, 2016; “Chen”). Final Act. 2–11.
(2) Claim 13 stands rejected under 35 U.S.C. § 103 as obvious over
the combined teachings of Asai, Chen, and Klein (US 2010/0153921 A1;
published June 17, 2010). Final Act. 11.
(3) Claim 23 stands rejected under 35 U.S.C. § 103 as obvious over
the combined teachings of Asai, Chen, and Zimmer et al. (US 2004/0268107
A1; published Dec. 30, 2004; “Zimmer”). Final Act. 11–12.

ANALYSIS
Claim 1 recites a computing device comprising, inter alia, the
disputed limitation:
wherein the data translation processing device is to translate
data structures compatible with the first ISA into data structures
compatible with the second ISA, the data structures are part of
data generated by a program during execution of the program
by the first processing core, and the translated data structures
are to be used during execution of the program by the second
processing core.

Appeal Br. 10 (Claims App.) (emphasis added). Claims 11 and 17 recite
similar limitations.
In support of the obviousness rejection of claim 1 and similarly,
claims 11 and 17, the Examiner finds Asai teaches most limitations of
Appellant’s claimed “computing device” including (1) “a first processing
core having a first instruction set architecture (ISA);” (2) “a second
processing core having a second ISA different from the first ISA;” and (3)
the disputed limitation re: “data translation processing device” “to translate
Appeal 2020-003811
Application 15/387,106

4
data structures compatible with the first ISA into data structures compatible
with the second ISA.” Final Act. 3 (citing Asai ¶¶ 8, 22, 27–31, 42–44, Fig.
3).
The Examiner finds Asai’s Figure 3 teaches Appellant’s claimed “data
structures” as reproduced below with additional markings for illustration.

Figure 3, as reproduced below, shows an example ContentData memory
object (“CDMO”) 150 employed in conjunction with context data 122 to
assign native code tasks to a different processor that executes a different
ISA. As shown in Figure 3, CDMO 150 includes context data 152, an
attribute section 154 (containing memory elements or attributes 158–164
associated with CDMO 150), and a method section 156 (containing
functions or methods that may be executed in conjunction with CDMO 150.
Asai ¶¶ 27–28. Typically, “a context is created for the native code” and
“includes any data necessary for [the] execution of the native code formatted
Appeal 2020-003811
Application 15/387,106

5
to meet the requirements of the target processor and the ISA of the target
processor.” Asai ¶ 9. “[B]oth the native code and the properly formatted
context [once created for a target processor] are transmitted to [a target]
processor.” Asai ¶ 44.
The Examiner acknowledges Asai does not teach “a bus coupled to
the first and second processing cores and the data translation device, or the
data translation device being different from the first processing core and
second processing core,” but relies on Chen for teaching these features to
support the conclusion of obviousness. Final Act. 3–4 (citing Chen ¶¶ 23,
33, 36–37, 42, Figs. 2A–2C).
Appellant presents two principal arguments against the Examiner’s
combination of Asai and Chen.
First, Appellant contends the combination of Asai and Chen does not
teach or suggest:
wherein the data translation processing device is to translate
data structures compatible with the first ISA into data structures
compatible with the second ISA, the data structures are part of
data generated by a program during execution of the program
by the first processing core, and the translated data structures
are to be used during execution of the program by the second
processing core

as recited in claim 1 (emphasis added). Appeal Br. 6–8. According to
Appellant,
[n]o portion of Asai discloses ‘translating’ any CDMOs 150 (the
alleged ‘data structures’) between different ISAs. Instead, Asai
discusses a system in which a different CDMO 150 is created,
stored, and used for each different ISA, without any discussion
of ‘translating’ a CDMO 150 for one ISA into a CDMO 150 for
a different ISA. See, e.g., Asai at paragraph [0027] (‘Context
data 122 could include multiple instantiations of CDMO 150,
Appeal 2020-003811
Application 15/387,106

6
each instantiation corresponding to a particular processor . . .[’])
and paragraph [0029] (‘Attribute section 152 [of a particular
CDMO 150] includes . . . an “ISAType” attribute 162 . . .’).

Appeal Br. 7. As such, “CDMOs 150 do not serve as the claimed ‘data
structures.’” Reply Br. 2.
Second, Appellant also contends the Examiner fails to provide
“rationale . . . why . . . [one] ordinary skill in the art would add such
additional complexity to the system discussed by Asai, nor how the systems
discussed by Asai and Chen would have to be modified to facilitate such a
combination.” Appeal Br. 8.
We do not find Appellant’s contentions persuasive. Rather, we find
the Examiner has provided a complete response to Appellant’s arguments
supported by a preponderance of evidence. Ans. 19–23. Therefore, we
adopt the Examiner’s findings and explanations provided therein. Id. For
additional emphasis, we note claim terms, during prosecution, are given their
broadest reasonable interpretation consistent with the specification. In re
Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004). Under
the broadest reasonable interpretation, claim terms are given their ordinary
and customary meaning, as would be understood by one of ordinary skill in
the art in the context of the entire disclosure. In re Translogic Tech., Inc.,
504 F.3d 1249, 1257 (Fed. Cir. 2007).
Neither the term “data structures” nor the term “translation” is
expressly defined in Appellant’s Specification. Instead, Appellant’s
Specification describes “data structures” compatible with different ISAs may
be generated from a data structure compatible file 146, shown in Figure 4
(Spec. ¶ 54) and
Appeal 2020-003811
Application 15/387,106

7
data structures in the program data may be translated from the
format of the first ISA to the format of a second ISA, different
from the first ISA. For example, the data translation processing
device 182 may translate data structures in any of the program
data discussed above (e.g., with reference to 282) to a format
compatible with an ISA of a different processing core 102 (e.g.,
an ISA K of a processing core 102-K). The translation may
include any operations to make the translated data structures
compatible with the second ISA (e.g., a change in endianness, a
change in the word size, a change in the address space, a change
in the number of operands, etc.).

Spec. ¶ 102 (emphasis added).
Based on Appellant’s Specification and the broad wording of
Appellant’s claim 1, we agree with the Examiner that the term “data
structure” can be broadly, but reasonably interpreted to encompass Asai’s
CDMO 150 and context data 152, as Asai’s “context is created for the native
code” and “includes any data necessary for [the] execution of the native
code formatted to meet the requirements of the target processor and the ISA
of the target processor.” Asai ¶ 9. Likewise, we also agree with the
Examiner that the term “translating” can be broadly, but reasonably
interpreted to encompass Asai’s “creation of context data for another
processor running a different ISA.” Ans. 21.
“[T]he fact that [A]ppellants can point to definitions or usages that
conform to their interpretation does not make the PTO’s definition
unreasonable when the PTO can point to other sources that support its
interpretation.” In re Morris, 127 F.3d 1048, 1056 (Fed. Cir. 1997).
With respect to Appellant’s argument against the reason to combine,
we agree with the Examiner that “utilizing a separate data translation
processing device and a bus as taught by Chen in the computing device of
Appeal 2020-003811
Application 15/387,106

8
Asai” would have been obvious to a skilled artisan because such an
incorporation “would merely entail a combination of known prior art
elements to achieve predictable results.” Final Act. 4.
For the above reasons, we sustain the Examiner’s rejections of
independent claims 1, 11, and 17 and their respective dependent claims 2–
10, 12–16, and 18–25, which Appellant does not argue separately. Appeal
Br. 10–11.

CONCLUSION
On the record before us, we conclude Appellant has not demonstrated
the Examiner erred in rejecting (1) claims 1–12, 14–22, 24, and 25 as
obvious over the combined teachings of Asai and Chen; (2) claim 13 as
obvious over the combined teachings of Asai, Chen, and Klein; and (3)
claim 23 as obvious over the combined teachings of Asai, Chen, and
Zimmer.

DECISION SUMMARY
In Summary:
Claim(s)
Rejected
35
U.S.C. §
Reference(s)/Basis Affirmed Reversed
1–12, 14–
22, 24, 25
103 Asai, Chen 1–12, 14–
22, 24, 25

13 103 Asai, Chen, Klein 13
23 103 Asai, Chen,
Zimmer
23
Overall
Outcome
1–25
Appeal 2020-003811
Application 15/387,106

9

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED