Intel Corporation

Patent Trials and Appeals Board

Jul 21, 2021

2020004771 (P.T.A.B. Jul. 21, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/911,350 03/05/2018 Bruce Querbach AA6674-US 1644
88032 7590 07/21/2021
Jordan IP Law, LLC
12501 Prosperity Drive, Suite 401
Silver Spring, MD 20904
EXAMINER
HUANG, MIN
ART UNIT PAPER NUMBER
2827
NOTIFICATION DATE DELIVERY MODE
07/21/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BRUCE QUERBACH and CHRISTOPHER CONNOR
Appeal 2020-004771
Application 15/911,350
Technology Center 2800
Before CATHERINE Q. TIMM, LINDA M. GAUDETTE, and
JENNIFER R. GUPTA, Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–22. See Final Act. 1. We have
jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant
identifies the real party in interest as Intel Corporation. Appeal Br. 3.
Appeal 2020-004771
Application 15/911,350
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CLAIMED SUBJECT MATTER
The claims are directed to an electronic processing system (see, e.g.,
claim 1), a semiconductor apparatus (see, e.g., claim 8), and a method of
determining a memory value of a multi-level memory cell (see, e.g., claim
16). All of the claims require an operation to determine “only a single-bit
value of the memory cell based on the entire multi-bit digital value.”
Claim 1, reproduced below with the limitation at issue italicized, is
illustrative:
1. An electronic processing system, comprising:
a processor;
multi-level memory communicatively coupled to the
processor;
an analog-to-digital converter communicatively coupled
to the multi-level memory to convert an analog voltage level of
a memory cell of the multi-level memory to a corresponding
multi-bit digital value; and
logic communicatively coupled to the multi-level
memory and the analog-to-digital converter to determine only a
single-bit value of the memory cell based on the entire multi-bit
digital value.
Appeal Br. 12 (Claims Appendix) (emphasis added).
REFERENCES
The prior art relied upon by the Examiner is:
Name Reference Date
Baek US 8,174,875 B2 May 8, 2012
Warren ’861 (W2) US 2011/0060861 A1 Mar. 10, 2011
Warren US 2011/0185111 A1 July 28, 2011
Zhou US 2015/0277768 A1 Oct. 1, 2015

Appeal 2020-004771
Application 15/911,350
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REJECTIONS
Claims 1, 2, 16, and 17 are rejected under 35 U.S.C. § 102(a)(1) as
being anticipated by Warren. Final Act. 2.
Claims 3 and 18 are rejected under 35 U.S.C. § 103 as being
unpatentable over Warren and Warren ’861 (W2). Final Act. 3.
Claims 4, 5, 19, and 20 are rejected under 35 U.S.C. § 103 as being
unpatentable over Warren and Warren ’861 (W2), further in view of Zhou.
Final Act. 4.
Claims 6–15, 21, and 22 are rejected under 35 U.S.C. § 103 as being
unpatentable over Warren and Warren ’861 (W2), further in view of Baek.
Final Act. 4.
OPINION
Appellant does not argue any of the claims apart from the others, and
Appellant focuses the arguments on the Examiner’s rejection of claim 1 as
anticipated by Warren. Appeal Br. 8–10. Thus, it will suffice for us to
address the rejection of claim 1 in resolving the issue on appeal. The issue is:
Has Appellant identified a reversible error in the Examiner’s finding that
Warren describes a method and system that is operative “to determine only a
single-bit value of the memory cell based on the entire multi-bit digital
value”?
Appellant has not identified such an error.
Appellant argues that Warren’s determination of single bit outputs for
multiple three bit codes is different than what is claimed. Appeal Br. 8–9.
The Examiner agrees with Appellant’s reading of Warren, but disagrees that
this teaching fails to support the rejection. Ans. 3–4. According to the
Examiner, Warren describes using a three bit cell to determine a one bit
Appeal 2020-004771
Application 15/911,350
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value as required by claim 1. Id. We agree with the Examiner. That Warren
describes converting more than one three bit code to a single bit code does
not negate the teaching of performing the conversion required by the claims.
First, there is no real dispute that Warren teaches a multi-bit memory
that converts 8, i.e., 23 distinct voltage levels, representing three data bits per
cell, i.e., data bits with combinations of three 0s and 1s such as ‘000’, ‘001’,
‘010’, etc. Warren ¶¶ 2, 8.
This comports with Appellant’s description of how a multi-level
memory cell works:
A multi-level non-volatile memory stores more than one
bit per cell. Multilevel NAND memory having four (4) possible
voltage levels per cell, may represent two (2) bits of data per
cell. NAND memory having eight (8) voltage levels per cell may
be referred to as triple-level cell (TLC) memory and may
represent three (3) bits of data per cell. NAND memory having
sixteen (16) voltage levels per cell may be referred to as quad-
level cell (QLC) memory and may represent four (4) bits of
data per cell.
Spec. ¶ 2 (emphasis added). Warren’s multi-memory cell is a triple-level cell
(TLC) as described in Appellant’s Specification. Warren teaches a three bit
multi-level memory and an analog-to-digital converter that converts eight
voltage levels to eight corresponding multi-bit digital values of three bits
(‘000’, ‘001’, 010’, ‘011’, ‘100’, ‘101’, ‘110’, ‘111’).
Both Appellant and the Examiner agree that Warren discloses
“[w]here one bit encoding is determined, any of a ‘000’, ‘001’, ‘010’, or
‘011’ are converted to a ‘0’ that is provided as an output; and any of a ‘100’,
‘101’, ‘110’, or ‘111’ are converted to a ‘1’ that is provided as an output.”
Warren ¶ 39; see also Warren ¶¶ 28, 39 (last column of table labeled “One
Bit Threshold Read Levels”); see also Fig. 4 (blocks 430, 440).
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Application 15/911,350
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When Warren’s system encodes any of ‘000’, ‘001’, ‘010’, or ‘011’ to
‘0’, and any of a ‘100’, ‘101’, ‘110’, or ‘111’ to a ‘1’, Warren is determining
a single-bit value (‘0’ or ‘1’) for each corresponding three bit input (‘000’,
etc.). Thus, for instance, the three bit code ‘000’ is converted to one bit code
‘0’. Put another way, Warren converts only a single-bit value (‘0’) of the
memory cell based on the entire multi-bit digital value (‘000’).
In the Reply Brief, Appellant contends that “the Examiner has not
established that any single bit value cited from Warren discloses ‘only a
single-bit value of the memory cell based on the entire multi-bit digital
value,” as recited in claim 1.” Reply Br. 6. From the context of the
paragraph, it appears that Appellant’s argument hinges on the meaning of
“entire” in the limitation as Appellant argues that “entire” “represents the
claimed ‘analog voltage level of a memory cell of the multi-level memory.’”
Id. But because each three bit code represents one (of eight) analog voltages
and Warren converts each corresponding three bit code into a single bit code
(e.g., ‘000’ is converted to ‘0’), it is unclear to us how the claim language
differentiates what is claimed from what is taught by Warren.
As one last point, we note that the word “entire” is not used in the
Specification in conjunction with “multi-bit digital value” (see e.g., Spec.
¶ 16) and for a triple-level cell (TLC), such as that taught by Warren, the
Specification equates the multi-bit digital value with the three bits of data of
the three bit code, e.g., ‘000’. Thus, Appellant has not persuaded us that the
word “entire” distinguishes the claimed system from the system of Warren,
which determines a single-bit value (e.g., ‘0’) based on the entire three bit
digital value (e.g., ‘000’). To give “entire” a meaning that would distinguish
what is claimed from what is taught by Warren would introduce an
ambiguity in the claim that may rise to the level of indefiniteness.
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We sustain the Examiner’s rejections.
CONCLUSION
The Examiner’s decision to reject claims 1–22 is AFFIRMED.
DECISION SUMMARY
Claim(s)
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1, 2, 16, 17 102(a)(1) Warren 1, 2, 16, 17
3, 18 103 Warren, Warren
’861
3, 18
4, 5, 19, 20 103 Warren, Warren
’861, Zhou
4, 5, 19, 20
6–15, 21, 22 103 Warren, Warren
’861, Baek
6–15, 21, 22
Overall
Outcome
1–22

RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED