Intel Corporation

Patent Trials and Appeals Board

Aug 27, 2021

2020001289 (P.T.A.B. Aug. 27, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/237,928 08/16/2016 Amit Kumar Srivastava ITL.3549US (P105984) 5150
47795 7590 08/27/2021
TROP, PRUNER & HU, P.C.
PO Box 41790
HOUSTON, TX 77241
EXAMINER
NAM, HYUN
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
08/27/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
Inteldocs_docketing@cpaglobal.com
tphpto@tphm.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
________________

Ex parte AMIT KUMAR SRIVASTAVA,
DUANE G. QUIET, and KENNETH P. FOUST
________________

Appeal 2020-001289
Application 15/237,928
Technology Center 2100
________________

Before JASON V. MORGAN, JAMES B. ARPIN, and ADAM J. PYONIN,
Administrative Patent Judges.

MORGAN, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant appeals from the
Examiner’s decision to reject claims 1–10 and 12–20.1 Claim 11 is canceled.
Amend. 4 (Sept. 27, 2018). We have jurisdiction under 35 U.S.C. § 6(b).
We affirm in part.

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant
identifies Intel Corporation as the real party in interest. Appeal Br. 3.
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SUMMARY OF THE DISCLOSURE
Appellant’s claimed subject matter relates to a host device that
includes,
a transceiver to communicate information on an interconnect; a
controller to control operation of the transceiver and to be a
master for the interconnect; and a role transfer logic to cause a
secondary device to be the master for the interconnect when at
least a portion of the host device is to enter into a low power.
Abstract.
REPRESENTATIVE CLAIM
Representative claim 6 is reproduced below (disputed limitations
emphasized and bracketing added).
REFERENCES
The Examiner relies on the following references:
Name Reference Date
Bormann et al.
(“Bormann”)
US 2002/0124198 A1 Sept. 5, 2002
Chhabra US 2008/0069021 A1 Mar. 20, 2008
REJECTIONS2
The Examiner rejects claims 1–10 and 12–20 under 35 U.S.C. § 103
as obvious over the combined teachings of Bormann and Chhabra. Final
Act. 3–7.

2 The Examiner previously rejected claims 6–9 under 35 U.S.C. § 112(a)
(Final Act. 2), but has withdrawn this rejection (Ans. 9).
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ANALYSIS
Claims 1 and 3–6
Claim 6, reproduced below with disputed recitations emphasized and
bracketed numbering added, is representative with respect to claims 1 and 3–
6.
6. A computing system comprising:
a host controller coupled to an interconnect to which a plurality
of devices are to be coupled, the host controller including:
[1] a first domain having:
a first driver to drive first information onto the
interconnect; and
a master controller comprising [2] a bus master for
the interconnect, [3] wherein the master controller
is to initiate a role transfer to a second controller
to cause the second controller to be the bus master
for the interconnect while at least a portion of the
host controller is in a low power state;
[4] a second domain having:
a wake detection circuit to identify a wake
indication received from the second controller, to
indicate that the second controller is to perform a
second role transfer to cause the master controller
to be the bus master for the interconnect;
the second controller to couple to the interconnect and to be [5]
a bus master for the interconnect, [6] wherein the second
controller when active has a lower power consumption level
than the host controller when active; and
at least one sensor to couple to the interconnect, [7] wherein the
second controller is to handle a communication from the at
least one sensor while at least the portion of the host controller
is in the low power state.
Appeal Br. 19 (Claims App’x).
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There are three issues with the definiteness of certain limitations of
claim 6, which must be resolved before we can analyze the Examiner’s
rejection. Generally, we resolve these issues in view of the plain language of
the claim, the recitation of similar limitations in the other pending claims,
and the Specification’s disclosure.
First, in claim 6, Appellant recites, “a first domain having: . . . a
master controller comprising a bus master for the interconnect” and “the
second controller to couple to the interconnect and to be a bus master for the
interconnect” (underlining and italics added). Although claim 6 appears to
recite two “bus masters,” one associated with the master controller and one
with the second controller, neither independent claim 1 nor independent
claim 10 similarly recites two “master” buses. See Vitronics Corp. v.
Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996) (other claims of the
patent can be valuable sources of enlightenment as to the meaning of a term
of a challenged claim). Moreover, each of the controllers having or being a
different “master bus” would be inconsistent with the remaining recitations
of claim 6 (i.e., “to cause the second controller to be the bus master for the
interconnect” (emphasis added)). Further, the Specification discloses only “a
master bus” of the master and secondary devices or controllers. See, e.g.,
Spec.¶¶ 12 (“[i]n this way, bus-connected devices such as a master device
that acts as a bus master for the bus can have faster wake capabilities”), 13
(“a master device (which may also be referred to as a master, host controller,
bus master, and/or main master)”), 36 (“[e]mbodiments may thus manage
system power without impacting system wake latency by transferring a bus
master role to one or more secondary master/bridge devices”). Therefore, for
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our analysis, we interpret claim 6 as reciting, “the second controller to
couple to the interconnect and to be [the] bus master for the interconnect.”
Second, claim 6 recites, “the second controller to couple to the
interconnect and to be a bus master for the interconnect, wherein the second
controller when active has a lower power consumption level than the host
controller when active” (emphases added). Claim 6 does not specify what
“when active” means, nor is the phrase used in any of the other pending
claims. But see Claim 10 (“the role transfer logic is to cause the secondary
device to be the master for the interconnect based at least in part on an
activity level on the interconnect” (emphasis added)). The Specification
makes only a single reference to “when active.” In particular, the
Specification discloses:
Stated another way, the secondary master/bridge device is
configured to handle communications on the bus, such as sensor
data being sent by a coupled sensor device. As such, when active
as bus master this device may receive incoming data
communications via the bus and provide the communications to
an intended destination, such as a host processor, which may
couple to the secondary master device by one or more other
interconnects, in some cases.
Spec. ¶ 14 (emphasis added). Therefore, for our analysis, we interpret claim
6 as reciting, “the second controller to couple to the interconnect and to be a
bus master for the interconnect, wherein the second controller when active
[as the bus master] has a lower power consumption level than the host
controller when active [as the bus master].”
Third, claim 6 recites, “the second controller when active has a lower
power consumption level than the host controller when active” (emphasis
added). However, claim 6 does not recite that “the host controller” has a
“power consumption level.” See also Claim 10 (“the secondary device
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having a lower power consumption than the host device”). Although claim 6
recites,” the host controller may be in a low power state” (emphasis added),
the Specification discloses:
As such, devices can be placed into deeper low power modes
(e.g., in which power consumption is on the order of
approximately a few microwatts (μW)), and reduce entry and exit
latencies with regard to such low power modes (e.g., to less than
a few microseconds). Although the scope of the present invention
is not limited in this regard, example buses may include a multi-
drop bus such as a bus in accordance with the forthcoming I3C
specification.
Spec. ¶ 12 (underlining and italics added); see id. ¶¶ 19 (associating reduced
power consumption with reduced activity), 36 (devices may have reduced
power consumption when they are not active as the bus master). Thus, we
understand that a reduced power consumption level is only one example of
operation in a low power mode or state. Nevertheless, claim 6 recites that
when a portion of the host controller is in a low power state, the master
controller that is included in the host controller has transferred its role as bus
master and is not “active.” Therefore, for our analysis, we interpret claim 6
as reciting that the host controller has a “power consumption level” before
the role transfer from the master controller to the second controller, and the
recited comparison between the “power consumption” levels of the host
controller and the second controller refers to levels experienced while each
controller is “active” as the bus master.
“It is the applicants’ burden to precisely define the invention.” In re
Morris, 127 F.3d 1048, 1056 (Fed. Cir. 1997). In the event of further
prosecution, Appellant should consider amending the claims to accurately
recite its claimed machine-readable media, computing systems, and host
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devices to the extent Appellant disagrees with our interpretations of the
claims.
In rejecting claim 6, the Examiner finds that Bormann’s process of a
peripheral device receiving state information from a CPU to have the
peripheral device operate in a primary3 mode and delaying the host from
exiting a sleeping state teaches or suggests recitations [1] and [3] (“a first
domain . . . wherein the master controller is to initiate a role transfer to a
second controller to cause the second controller to be the bus master for the
interconnect while at least a portion of the host controller is in a low power
state”), recitation [4] (“a second domain having . . . a wake detection circuit
to identify a wake indication received from the second controller, to indicate
that the second controller is to perform a second role transfer to cause the
master controller to be the bus master for the interconnect”), and recitation
[7] (“wherein the second controller is to handle a communication from the at
least one sensor while at least the portion of the host controller is in the low
power state”). Final Act. 4–5 (citing, e.g., Bormann ¶ 52, Fig. 5); Ans. 3–6.
The Examiner relies on Chhabra’s teaching that various devices that can take
on the role of a primary device or secondary device to allow for power
savings among devices to teach or suggest recitation [6], “wherein the
second controller when active has a lower power consumption level than the
host controller when active.” Final Act. 6 (citing Chhabra ¶ 24); Ans. 6.
Appellant contends the Examiner erred because “there is no device in
Bormann that includes the recited multiple domains[] included in a host
controller.” Appeal Br. 8. Appellant argues that Bormann merely teaches

3 Herein, we use the terms primary and secondary as synonymous with the
terms master and slave, respectively.
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“that a peripheral device . . . can detect when a CPU . . . is in a sleeping
state.” Id. at 9. Thus, Appellant argues, “Bormann absolutely fails anywhere
to teach or suggest that its CPU initiates any role transfer.” Id.; Reply Br. 2.
Appellant’s arguments are not persuasive because Bormann explicitly
teaches that as an alternative to the peripheral device monitoring the power
management state of the processing system or CPU, “power management
state information may be sent to the Peripheral Device by the processing
system or CPU.” Bormann ¶ 52 (emphasis added). Thus, Bormann’s
teachings and suggestions are not limited to a peripheral device that can
detect when a CPU is in a sleeping state, as Appellant argues. Appeal Br. 9.
Rather, Bormann also teaches or suggests the CPU initiating the role transfer
by sending power management information to the peripheral device.
Appellant further argues,
there is nothing in the CPU of Bormann to teach or suggest that
this master controller include, in another domain (namely the
recited second domain), a wake detection circuit to identify a
wake indication received from this second controller to indicate
that the second controller is to perform a second role transfer to
cause the master controller to be the bus master. Instead, the
CPU, wholly independently to anything else, enters into and
exits sleeping states and when it exits a sleeping state, it may be
master.
Id.
Appellant’s argument is not persuasive because, even when
Bormann’s host computer attempts to exit a sleeping state, the peripheral
device can delay the exit from a sleeping state if the peripheral device is in
the middle of an operation. Bormann, Fig. 5. Thus, Bormann teaches
including wake detection circuitry to identify when the peripheral device is
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no longer in the middle of an operation and is no longer delaying the exit
from a sleeping state. Bormann ¶ 56.
Appellant further argues nothing in the cited flowchart of Bormann
“meets the various elements the Examiner contends . . . including the recited
second controller and at least one sensor.” Appeal Br. 8. But Bormann’s
peripheral device responds to the processing system awakening from a
sleeping state by determining whether the peripheral device is in the middle
of an operation, thus, possibly delaying the processing system or CPU from
awakening. Id. Consequently, Bormann’s peripheral device includes a sensor
that senses when the processing system is awakening from a sleeping state.
Appellant argues that “a peripheral device cannot be said to somehow
handle a communication from itself,” and, thus, Bormann’s peripheral
device cannot teach or suggest both the recited second controller and at least
one sensor. Id. at 9. But neither claim 6 nor the Specification necessitates
that the second controller and sensor be separate or that the communications
be between the sensor and the logic-handling components of the second
controller be external. Consequently, Bormann teaches or suggests the
claimed second controller and sensor given a reasonable interpretation of
these recitations.
Appellant also argues the Examiner erred in relying on Chhabra
because while “Chhabra teaches that disparate devices may be present, the
alternate bus master capabilities are only available in systems having a
symmetrical ad-hoc mode network.” Id. at 9–10. Thus, Appellant argues that
in Chhabra, “when devices exist in an asymmetrical ad-hoc mode network,
only a permanent master device is possible.” Id. at 10; see also Chhabra
¶¶ 25–27 (cited at Ans. 10). We are not persuaded, however, as the only
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example given in the cited portions of Chhabra of a device taking on a
permanent primary device status is when the secondary device has
significantly fewer capabilities than the primary device, such that the
secondary device cannot carry out power save algorithms. Chhabra ¶ 27.
The specific example given is a cell phone (a primary device) and a wireless
headset (a secondary device). Id. We are unable to ascertain how this limited
example is pertinent, and we agree with the Examiner that the broader
teachings of Chhabra teach or suggest modifying Bormann, such that
Bormann’s peripheral device (secondary device) handles a communication
from sensor (determines when the processing system is awakening from a
sleeping state) while the processing system (the host controller) is in a lower
power state (before the host controller has actually awakened).
For these reasons, we agree with the Examiner that the combination of
Bormann and Chhabra teaches or suggests disputed recitations [1], [3]–[4],
and [6]–[7]. Accordingly, we sustain the Examiner’s obviousness rejection
of claim 6, and of claims 1 and 3–5, which Appellant argues are patentable
for similar reasons. Appeal Br. 10–11.
Claims 2 and 8
Claim 8, reproduced below with disputed recitations emphasized and
bracketed numbering added, is representative with respect to claims 2 and 8.
8. The computing system of claim 6, [8] wherein the host
controller further comprises a control logic to prevent a change
in one or more characteristics of the interconnect based at least
in part on the wake detection circuit identification of the wake
indication.
Appeal Br. 20 (Claims App.).
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In rejecting claim 8, the Examiner finds that Bormann’s peripheral
device, by being able to delay the host computer from exiting a sleeping
state, teaches or suggests recitation [8]. Final Act. 7 (citing Bormann Fig. 5).
Appellant contends the Examiner erred because “[w]hile Bormann teaches
that a host computer can be controlled in this way, this says nothing as to
any prevention of a change in interconnect characteristics.” Appeal Br. 13.
The Examiner, however, correctly finds that interconnect characteristics rely
on the communication characteristics of the primary and secondary devices.
Ans. 8. Thus, delaying the host computer (the primary device) from exiting a
sleeping state prevents the change in interconnect characteristics in
Bormann. Therefore, we agree with the Examiner that the combination of
Bormann and Chhabra teaches or suggests recitation [8].
Accordingly, we sustain the Examiner’s obviousness rejection of
claim 8, and of claim 2, which Appellant argues is patentable for similar
reasons. Appeal Br. 13.
Claim 7
Claim 7 is reproduced below with disputed recitations emphasized
and bracketed numbering added.
7. The computing system of claim 6, [9] wherein the master
controller is to send at least a portion of a context of the master
controller, policy information and interconnect characteristic
information to the second controller before the host controller
is to enter into the low power state.
Appeal Br. 19–20 (Claims App’x).
In rejecting claim 7, the Examiner finds that Chhabra’s exchange of
primary device capability advertisements between primary and secondary
devices teaches or suggests recitation [9]. Final Act. 6 (citing Chhabra
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Fig. 4A). Appellant acknowledges, “Chhabra teaches . . . that in an
asymmetrical ad-hoc network, stations such as walkie-talkies ‘both advertise
their master capabilities[—such as the ability to buffer data designated for
other stations—]to other stations in the network.’” Appeal Br. 12 (citing
Chhabra ¶ 28). But Appellant merely contends that these capabilities are
unrelated to any of the master controller context, policy information, and
interconnect characteristic information limitations of recitation [9] without
any explanation as to what distinguishes these broad categories from
Chhabra’s advertised capabilities.
Furthermore, the Examiner alternatively relies on Bormann to teach
the disputed limitations of recitation [9], and Appellant does not challenge
the Examiner’s alternative reliance on Bormann’s teachings. Ans. 8.
For these reasons, we agree with the Examiner that the combination of
Bormann and Chhabra teaches or suggests recitation [9]. Accordingly, we
sustain the Examiner’s obviousness rejection of claim 7.
Claim 9
Claim 9 is reproduced below with disputed recitations emphasized
and bracketed numbering added.
9. The computing system of claim 6, [10] wherein the host
controller further comprises a storage to store a pattern
corresponding to the wake indication, wherein the wake
detection circuit is to identify the wake indication when a
communication on the interconnect matches the pattern.
Appeal Br. 20 (Claims App’x).
In rejecting claim 9, the Examiner finds that Bormann’s delay of a
host computer exiting from a sleeping state teaches a binary logic decision
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that entails matching a pattern of data. Ans. 9. Thus, the Examiner finds that
Bormann teaches or suggests recitation [10].
Appellant contends that Chhabra, as previously relied on by the
Examiner, does not teach or suggest recitation [10]. Appeal Br. 13–14; Final
Act. 7 (citing Chhabra ¶ 5). But Appellant does not challenge the
Examiner’s reliance on Bormann. Therefore, based on the Examiner’s
findings with respect to Bormann, we agree with the Examiner that the
combination of Bormann and Chhabra teaches or suggests recitation [10].
Accordingly, we sustain the Examiner’s obviousness rejection of
claim 9.
Claims 10 and 13–20
Claim 10, reproduced below with disputed recitations emphasized and
bracketed numbering added, is representative with respect to claims 10 and
13–20.
10. A host device for controlling operation on an interconnect
comprising:
a transceiver to communicate information on the interconnect,
the interconnect to couple to the host device;
a controller to control operation of the transceiver and to be a
master for the interconnect; and
a role transfer logic to cause a secondary device to be the
master for the interconnect when at least a portion of the host
device is to enter into a low power mode, [11] wherein the role
transfer logic is to cause the secondary device to be the master
for the interconnect based at least in part on an activity level on
the interconnect, the secondary device having a lower power
consumption than the host device.
Appeal Br. 20 (Claims App’x).
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In rejecting claim 10 as obvious, the Examiner finds that Bormann’s
peripheral device—by delaying a host computer from exiting a sleeping state
based on the determination that the peripheral device is in the middle of an
operation—teaches or suggests recitation [11]. Ans. 7. In particular, the
Examiner finds that this determination requires an “information transfer
between [the] Peripheral device and whatever (interconnect is any
connection that is connected to [the] Peripheral device) determines that [the]
Peripheral device is in [the] middle of an operation.” Id.
Appellant contends the Examiner erred because
the peripheral device may be ‘in the middle of [an] operation’
and yet an interconnect coupled to it may have no activity
whatsoever. And conversely, this interconnect may be fully
busy because of communications flowing between other
devices – while the peripheral device is not in the middle of any
operation.
Reply Br. 3.
We agree with Appellant the Examiner erred. Bormann does not teach
that anything other than the peripheral device makes the determination that
the peripheral device is in the middle of an operation, or that the operations
the peripheral device may be in the middle of entail interconnect activity.
Thus, the Examiner’s findings fail to show that Bormann teaches or suggests
the claimed reliance on an activity level on the interconnect in the role
transfer logic of recitation [11].
Accordingly, we do not sustain the Examiner’s obviousness rejection
of claim 10, or of claims 12–20, which depend therefrom.
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CONCLUSION
In summary:
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1–10, 12–20 103 Bormann, Chhabra 1–9 10, 12–20
TIME PERIOD FOR RESPONSE
No time period for taking subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED-IN-PART