Gross, John Nicholas. et al.

Patent Trials and Appeals Board

Dec 9, 2019

14857275 - (D) (P.T.A.B. Dec. 9, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/857,275 09/17/2015 John Nicholas Gross JONK 2015-1 1052
23694 7590 12/09/2019
Law Office of J. Nicholas Gross, Prof. Corp.
PO BOX 9489
BERKELEY, CA 94709
EXAMINER
KING, DOUGLAS
ART UNIT PAPER NUMBER
2824
NOTIFICATION DATE DELIVERY MODE
12/09/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
eofficeaction@appcoll.com
jngross@pacbell.net
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte JOHN NICHOLAS GROSS and DAVID K. Y. LIU
____________

Appeal 2018-006190
Application 14/857,275
Technology Center 2800
____________

Before DONNA M. PRAISS, BRIAN D. RANGE, and LILAN REN,
Administrative Patent Judges.

PRAISS, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
decision2 finally rejecting claims 10–20 and 29–40. We have jurisdiction
under 35 U.S.C. § 6(b).
We AFFIRM IN PART.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Jonker, LLC is identified as the real party in interest.
Appeal Brief, filed January 12, 2018 (“Appeal Br.”) 2.
2 Final Office Action, dated June 12, 2017 (“Final Act.”).
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STATEMENT OF THE CASE
Background
The subject matter on appeal relates to “non-volatile memories which
are engineered or controlled to have limited data retention times.”
Specification, September 17, 2015 (“Spec.”) 1:16–17. According to the
Specification, a self-erase mechanism may be either (1) individual cells
engineered with characteristics that enhance charge leakage without
requiring additional active operations or (2) a read operation tailored to
make the data accessible only one time, single access. Id. at 6:25–7:14. The
Specification discloses another embodiment in which the data retention
period is controlled with additional active operations, such as a slow or
extremely slow erase operation or a mandatory, irreversible re-write of blank
(or random) data, to achieve a target data retention behavior. Id. at 7:15–28.
Of the appealed claims, claims 10 and 14 are independent. Claim 10 is
representative of the subject matter on appeal, and reproduced below
(disputed limitation emphasized):
10. A memory device on an integrated circuit adapted with
ephemeral data retention capability comprising:
an array of charge storage elements;
wherein each charge storage element in said array is
characterized by an inherent leakage current and is
configurable:
• to store a first amount of charge corresponding to a first
state corresponding to a first state representing a first data
value; and
• to store a second amount of charge corresponding to a
second state representing a second data value;
a programming control circuit configured:
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• to program said array of charge storage elements to said
second data value based on a first write operation;
• to initiate and control a slow erase operation on said
array, including at least a first mode in which a
controlled erase charge is actively removed from a
selected charge storage element over a controlled
predetermined period and in the absence of a new second
write operation for such selected charge storage element;
wherein said programming control circuit is adapted to actively
impose erase bias voltages to said array of charge storage
elements during said controlled predetermined period so that
said controlled erase charge is removed from such elements in
addition to charge lost to leakage current by such elements.
Appeal Br. 13 (Claims Appendix). Claim 14 is similar to claim 10, but
not does not specify the erase operation is a “slow” erase operation.
Id. at 14.
The Examiner maintains the following rejections over the
following references on appeal. Ans. 2–10; Final Act. 2–13.
The References
Name Reference Date
Chen US 2013/0070530 A1 Mar. 21, 2013
Hartselle US 2003/0131060 A1 July 10, 2003
Aasheim US 2003/0161186 A1 Aug. 28, 2003
Perlegos US 4,266,283 May 5, 1981
The Rejections
Claim(s) 35 U.S.C. § Reference(s)/Basis
31, 33, 37, 39 112(a) Written Description
29, 31, 35, 37 112(b) Definiteness
10, 11, 29, 31, 32, 33 102(a) Chen
13, 30, 34 103 Chen
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Claim(s) 35 U.S.C. § Reference(s)/Basis
14–20, 35–40 103 Chen, Hartselle, Aasheim
12 103 Chen, Hartselle, Perlegos
OPINION
After considering the evidence presented in this Appeal and each of
Appellant’s contentions, we are persuaded the Examiner erred harmfully in
rejecting claims 29, 31, 35, and 37. We address each of the rejections below.
Written Description
The Examiner rejects dependent claims 31, 33, 37, and 39 as lacking
written description support. Final Act. 2–3. Claims 33 and 39 recite “the
programming control circuit is configured to cause Fowler-Nordheim
tunneling to remove said charge during said controlled predetermined
period.” Appeal Br. 15, 16. Claims 31 and 37 recite “apply the smallest
possible bias required.” Id.
Appellant contends the Examiner erred in rejecting claims 33 and 39
because the Specification specifically mentions Fowler-Nordheim (F-N)
tunneling as an erase mechanism. Appeal Br. 11 (citing Spec. 9:13–17,
10:14–15, 17:24–31, 28:7–10. Regarding the rejection of claims 31 and 37,
Appellant contends that “the smallest possible bias” is specifically tracked in
the Specification and straightforward once the desired erase time is
provided. Id. (citing Spec. 18:3–9).
The Examiner responds that although the Specification mentions F-N
tunneling “as an erase mechanism,” it does not disclose this specific
mechanism for removing charges during the “controlled predetermined
period” as the claim requires. Ans. 8. Regarding “the smallest possible bias
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required” appearing in the Specification, the Examiner states that Appellant
has not demonstrated possession of the range of biases because “Appellant
has not conceived of every variation of memory and the accompanying
smallest possible bias which may be associated therewith.” Id. at 9.
In the Reply Brief, Appellant asserts that the use of FN tunneling for
the slow erase is disclosed in the Specification because immediately after FN
tunneling is described as an option for erase, the Specification describes the
“slow erase” operation. Reply Br. 8 (citing Spec. 17:22–18:7). Regarding the
range of biases that the Examiner determines is implied by the recitation
“smallest possible bias,” Appellant asserts that this is a physics problem to
solve for controlling the leakage from a capacitor and that the behavior of
memory cells of a particular geometry can be well-characterized with known
tools to determine what bias is required to remove a charge over a particular
target time period. Id. at 9.
We agree with Appellant that the Specification sufficiently discloses
FN tunneling as an active erase mechanism for implementing the “slow
erase” embodiment disclosed in the Specification. Spec. 17:22–18:7. As
Appellant points out, the description of FN tunneling as an active erase
mechanism is immediately followed by the disclosure of how the
mechanism is modified to effectuate a “slow erase,” i.e. by applying the
smallest possible bias, such as a negative voltage to the control gate, rather
than applying a large negative voltage to effectuate erase, and to apply the
erase “continuously or periodically . . . to continue to remove charge to
achieve a desired erase time.” Reply Br. 8–9; Spec. 17:22–18:7. Thus, the
claimed operation over a predetermined period required by claims 33 and 39
is disclosed in the Specification even though the disclosure is phrased
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differently. The claimed subject matter need not be described “in haec
verba” in the original specification in order to satisfy the written description
requirement. In re Wright, 866 F.2d 422, 425 (Fed. Cir. 1989). Rather,
“[a]dequate written description means that the applicant, in the specification,
must ‘convey with reasonable clarity to those skilled in the art that, as of the
filing date sought, he or she was in possession of the [claimed] invention.’”
Agilent Techs., Inc. v. Affymetrix, Inc., 567 F.3d 1366, 1379 (Fed. Cir. 2009)
(reh’g en banc denied Sep. 18, 2009) (citation omitted).
We also agree with Appellant that the Specification sufficiently
discloses the amount of bias required by claims 31 and 37 to remove charge
during a predetermined period to achieve a target data retention time. As
Appellant points out, the smallest amount of bias to remove to achieve a
target data retention time is disclosed in the Specification and it is a physics
calculation. Reply Br. 9; Appeal Br. 11. Thus, the Specification conveys to a
person skilled in the art that a small amount of bias is removed over time to
achieve a target date retention time that can be computed for a certain
amount of charge in a particular time.
Accordingly, we reverse the Examiner’s rejection of claims 31, 33,
37, and 39 as lacking written description support in the Specification.

Definiteness
The Examiner rejects dependent claims 29, 31, 35, and 37 as
indefinite for the reasons provided in the Final Office Action. Final Act. 3.
Claims 29 and 35 recite “a nominal data retention time capability of the
selected charge storage elements is actively shortened by said slow erase
operation.” Appeal Br. 15, 16. Claims 31 and 37 recite “the programming
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control circuit is configured to cause apply[ing] the smallest possible bias
required to remove charge from the selected charge storage elements during
said controlled predetermined period to achieve a target data retention time.”
Id.
Appellant contends that the Examiner erred in rejecting claims 29 and
35 as indefinite because a cell has a nominal data retention time that can be
determined readily using simulation tools and routine experiments as a
function of basic semiconductor physics described in the Specification.
Appeal Br. 11 (citing Spec. 9:8–10:17). Appellant asserts that the claim
emphasizes that the retention time capability is actively shortened by the
action of the control circuit. Id. Regarding claims 31 and 37, Appellant
argues that “smallest possible bias” is relatively straightforward to determine
once the desired erase time is provided using a conventional simulation tool
to determine the bias for a particular target design and erase time. Id. at 11–
12.
The Examiner responds that the recitation “nominal data retention
time” means a very small retention time that is then shortened, thus “one of
ordinary skill would not be aware when they had infringement the claim.”
Ans. 9. Regarding “the smallest possible erase time” recited in claims 31 and
37, the Examiner responds that the issue is the scope implied by the
limitation and whether “one of ordinary skill can avoid infringement by
noting that there is some ‘possible’ bias smaller than the one implemented.”
Id. at 10.
In the Reply Brief, Appellant argues that “nominal” refers to a design
value or an expected value in engineering designs rather than “very small”
as the Examiner construes this term. Reply Br. 9. Appellant also argues that
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the target data retention time is published in conventional datasheets as part
of the product specifications, thus the applied bias must match the target data
retention time. Id. at 10.
We are persuaded by Appellant’s arguments that the Examiner erred
in rejecting claims 29, 31, 35, and 37 as indefinite. The definiteness of a
claim depends on whether one skilled in the art would understand the
bounds of the claim when read in light of the specification. Howmedica
Osteonics Corp. v. Tranquil Prospects, Ltd., 401 F.3d 1367, 1371 (Fed. Cir.
2005). Appellant’s arguments sufficiently explain that one skilled in the art
would understand the “nominal data retention time” to be the expected or
design value and that the recited “smallest possible bias” to be the bias
required to achieve a target data retention time. Appellant’s arguments are
supported by the Specification, which equates “retention time” with “a fixed
amount of memory” and “a nominal data retention time” as “a required re-
program window.” Spec. 23:13–17. Similarly, the Specification describes
the “smallest possible bias” as a negative voltage to the control gate
“required to continue to remove charge to achieve a desired erase time.” Id.
at 18:3–7. Accordingly, we reverse the Examiner’s rejection of claims 29,
31, 35, and 37 as indefinite.

Anticipation
The Examiner rejects claims 10, 11, 29, and 31–33 as anticipated by
Chen for the reasons provided in the Final Office Action. Final Act. 4–6. We
address below the claims separately argued by Appellant.
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Independent Claim 10
Appellant contends that the Examiner erred in finding that Chen
discloses a slow erase mechanism as required by independent claim 10.3
Appeal Br. 7. According to Appellant, there is no mechanism by which
Chen’s programming control circuit actively removes charge from the
storage elements beyond any charge they lose by inherent leakage. Id. at 6.
Appellant acknowledges that Chen erases cells as part of a programming
operation but argues that Chen does not erase cells after they are
programmed. Id. (citing Chen Fig. 19, step 556). Appellant asserts that the
Examiner’s rejection is based on an erroneous interpretation of the claim that
“any erase can be considered slow.” Id. at 7 (quoting Final Act. 4).
Appellant contends that the Specification distinguishes the term “slow erase”
from different kinds of erase and that the Examiner’s rejection fails to give
effect to the claim recitation “a controlled erase charge is actively removed
from a selected charge storage element over a controlled predetermined
period and in the absence of a new second write operation.” Id. (citing Spec.
18). According to Appellant, Chen’s limited data retention occurs solely as a
result of the cell storing less charge and not from an operation that actively
removes a charge as required by the claims. Id. at 8–9.
The Examiner responds that “slow” is a relative term. Ans. 3. The
Examiner also finds Chen discloses charges are transferred or removed from
the floating gate during the deletion. Ans. 3–4 (citing Chen ¶ 119). The
Examiner maps step 552 of Chen’s Figure 19 as anticipating the claimed

3 As noted by the Examiner, Appellant’s reference to claim 1 in the Appeal
Brief is understood to refer to independent claim 10 because claim 1 is no
longer pending. Ans. 5.
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slow erase operation and finds there is no second write operation that is a
part of step 552 that is present during the slow erase of Chen as required by
claim 10. Id. at 4 (citing Chen Fig. 19). Regarding Appellant’s assertion that
Chen’s erase is due to leakage rather than active removal, the Examiner
finds Chen teaches that charges (electrons) are lost to applied voltages,
which would be in addition to any leakages. Id. at 5 (citing Chen ¶ 119).
In the Reply Brief, Appellant acknowledges that, “in the abstract,”
any erase can be considered slow to some degree. Reply Br. 4–5. Appellant
contends that the Examiner erred in finding that step 552 is a slow erase
separate from a second write operation because Chen indicates in paragraph
119 that erase step 552 “never occurs by itself as a separate operation.” Id. at
4. Appellant also maintains that Chen does not actively remove additional
charge because Chen makes a shorter retention cell by making it smaller
instead. Id. at 5.
We are not persuaded by Appellant’s arguments because the argument
does not identify error in the Examiner’s finding that Chen’s erase step 552
shown in Figure 19 is separate from a second write operation. Ans. 4.
Paragraph 119 states “In step 552, memory cells are erased (in blocks or
other units) prior to programming . . . .” Chen ¶ 119. Appellant does not
adequately explain why a step performed “prior to” another step is not a
separate step. Similarly, Appellant does not adequately explain why Chen’s
erase does not actively remove charge in view of the Examiner’s finding
(Ans. 5) that Chen applies a voltage which is in addition to any leakages.
Appellant does not dispute the Examiner’s finding that Chen teaches that
charge is lost to applied voltages in addition to any leakage.
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Appellant also argues that claim 10’s recited “slow erase operation”
must apply the smallest possible bias required to remove charge to achieve a
desired erase time. Appeal Br. 7–8. We decline to construe “slow erase
operation” so narrowly. Claim 10 does not recite application of the “smallest
possible bias,” but, for example, dependent claim 31 does. The context
provided by claim 31 suggests that not every “slow erase operation” as
recited by claim 10 inherently requires application of the smallest possible
bias as recited by claim 31.
Thus, Appellant has not identified reversible error in the Examiner’s
rejection of claim 10. Accordingly, we affirm the Examiner’s anticipation
rejection of claim 10 as supported by the preponderance of the evidence
cited in this Appeal.

Dependent Claim 11
Claim 11 depends from claim 10 and recites “wherein said slow erase
operation is effectuated immediately after said first write operation.” Appeal
Br. 13 (Claims Appendix). Appellant contends that the Examiner erred in
finding dependent claim 11 anticipated by Chen because Chen’s block 550 is
a pre-program and not a write operation as required by independent claim 1,
thus the actual write operation is not performed until after the erase. Appeal
Br. 9.
In response, the Examiner finds Chen’s “pre-program” operation
writes all the cells to the same state as Appellant asserts. Ans. 5. The
Examiner finds this is exactly what claim 10’s “first write operation”
requires by “to program said array of charge storage elements to said second
data value.” Id.
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Because Appellant agrees that in block 550 “all the cells are written to
the same state” (Appeal Br. 9), we are not persuaded that the Examiner erred
in rejecting claim 11 as anticipated by Chen. We do not consider Appellant’s
new arguments in the Reply Brief that the pre-program operation of block
550 is not a write operation because (1) step 556 is a write operation and
occurs after the erase and (2) block 550 does not store an amount of charge
representing a second data value for the cell that is being written. Reply Br.
5–6. Appellants have not proffered a showing of good cause explaining why
the arguments could not have been presented in the Appeal Brief after the
Examiner identified block 550 in the Final Rejection of claim 11. Final Act.
5. Therefore, we will not consider these new and untimely arguments in our
assessment of the Examiner's § 102 rejections. 37 C.F.R. §§ 41.37, 41.41.

Dependent Claim 29
Claim 29 depends from claim 10 and recites “a nominal data retention
time capability of the selected charge storage elements is actively shortened
by said slow erase operation.” Appeal Br. 15 (Claims Appendix). Appellant
contends that the Examiner erred in finding dependent claim 29 anticipated
by Chen because Chen describes a general erase typical for prior art cells
that removes all of the charge as quickly as possible and is performed
before, rather than after, a write operation. Appeal Br. 9.
The Examiner responds by finding that the plain meaning of retention
time is the amount of time that the data is retained in the cell. Ans. 6. The
Examiner also finds that retention time is actively shortened by imposing an
erasure on the memory, thus data is retained for a shorter time than if the
erasure had not been effected. Id. The Examiner states that the claim does
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not alter any physical characteristic of the charge storage element and that
Chen applies a voltage to remove charges over a period of time as with
Appellant’s device. Id.
In the Reply Brief, Appellant argues that Chen’s cell’s “nominal data
retention time capability” is not affected by an erase just as the capability of
a bucket to hold water is not affected by emptying it. Reply Br. 6.
We find Appellant’s argument persuasive of harmful error by the
Examiner based on the correct construction of “nominal data retention time”
discussed above in connection with the rejection of claim 29 as indefinite.
Because the Examiner does not adequately explain how Chen discloses a
required re-program window to establish a “nominal retention time”
capability of Chen’s charge storage element as defined by the Specification,
we reverse the rejection of claim 29 as anticipated by Chen. .

Dependent Claim 31
Claim 31 depends from claim 10 and recites “wherein the
programming control circuit is configured to cause apply [sic] the smallest
possible bias required to remove charge . . . during said controlled
predetermined period to achieve a target data retention time.” Appeal Br. 15
(Claims Appendix). Appellant contends that the Examiner erred in finding
dependent claim 31 anticipated by Chen because “Chen attempts to remove
all of the charge as quickly as possible” and is not “the smallest bias
required to remove charge” as recited in claim 31. Appeal Br. 9.
The Examiner responds that the Chen teaches zero volts applied and
charges are removed, therefore Chen discloses the smallest possible bias.
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Ans. 6. In the Reply Brief, Appellant asserts that Chen’s erase is performed
under high bias of 20 volts. Reply Br. 6 (citing Chen ¶ 119).
We find Appellant’s argument persuasive of harmful error because the
Examiner has not adequately explained how Chen discloses a bias of zero
volts to remove charge. Chen ¶ 119; Final Act. 6. Accordingly, we reverse
the Examiner’s rejection of claim 31 as anticipated by Chen.

Dependent Claims 32 and 33
Appellant does not separately argue the patentability of claims 32 and
33, which each depend from claim 10. Unlike claims 29 and 31, neither
claim 10 nor claim 11 requires either “a nominal data retention time
capability” or a “smallest possible bias required to remove charge from the
selected charge storage elements.” Because we affirm the Examiner’s
rejection of claim 11, we likewise affirm the rejection of claims 32 and 33
for the same reasons.

Obviousness
The Examiner rejects dependent claims 12–20, 30, and 34–40 as
unpatentable under 35 U.S.C. § 103(a) over Chen alone or in combination
with secondary references for the reasons provided in the Final Office
Action. Final Act. 7–13. We address below the claims separately argued by
Appellant.
Claim 12
Claim 12 depends from claim 10 and recites “wherein said controlled
predetermined period ranges from 104 to 106 seconds.” Appeal Br. 13
(Claims Appendix). Claim 12 stands rejected over the combination of Chen,
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Hartselle, and Perlegos. Final Act. 12–13. Appellant argues that the
references disclose a period for performing a regular erase, therefore they do
not disclose a particular duration which is the period when slow erase is
applied. Appeal Br. 11.
The Examiner responds that Appellant’s argument implies there is
some fundamental difference between the claimed application of voltage to
remove electrons over a period of time and the modified prior art doing the
same thing; Appellant, however, does not challenge the Examiner’s
combination or rationale for the rejection. Ans. 8.
Because we find that Chen discloses an erase period that renders the
claimed slow erase as discussed above in connection with claim 10, and
Appellant does not dispute the Examiner’s findings (Final Act. 12–13) that
Perlegos teaches erase times for flash memory cells is dependent upon an
applied voltage. Hartselle teaches it is desirable to erase certain data after
user configured time periods, and it would have been obvious to initiate a
slow erasure for the claimed period for user specifications, we affirm the
obviousness rejection of claim 12 over Chen, Hartselle, and Perlegos.

Claim 13
Claim 13 depends form claim 10 and recites “wherein said array is
partitioned into a plurality of subarrays of charge storage elements, and each
of said plurality of subarrays is subjected to said slow erase operation at a
different time in a predetermined program sequence.” Appeal Br. 14 (Claims
Appendix). Claim 13 stands rejected as obvious over Chen. Final Act. 7–8.
Appellant argues that Chen fails to disclose or suggest a sequence based
erasing of any kind. Appeal Br. 10.
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The Examiner responds that the Final Rejection provides a rationale
for erasing the blocks in a predetermined sequence, i.e. to ensure all blocks
are erased, and that rationale has not been challenged with argument. Ans.
6–7.
Because we find Chen discloses an erase period that teaches the
claimed slow erase as discussed above in connection with claim 10, and the
Examiner has provided a rationale for erasing blocks in a predetermined
programs sequence that has not been challenged, we likewise affirm the
obviousness rejection of claim 13 over Chen.

Claim 14
Claim 14 is independent and similar to claim 10. Claim 14 stands
rejected over the combination of Chen, Hartselle, and Aasheim. Final Act.
8–10. Appellant argues that Hartselle and Aasheim do not actively impose
erase bias voltages to cause an additional loss of charge beyond that lost to
leakage of current and consequently do fail to cure the deficiencies of Chen.
Appeal Br. 10.
The Examiner responds that Appellant does not challenge the
Examiner’s reliance on Hartselle and Aasheim, but merely attacks the
references for not teaching features that they are not relied upon for
teaching. Ans. 7.
Because Appellant does not argue the rejection made by the
Examiner, we affirm the obviousness rejection of claim 14.

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Claim 19
Claim 19 depends from claim 14 and recites “wherein said erase
operation cannot be disabled by any control signal provided to the integrated
circuit and occurs automatically to implement a forced erase of any array
data.” Appeal Br. 15 (Claims Appendix). Claim 19 stands rejected over the
combination of Chen, Hartselle, and Aasheim. Final Act. 11. Appellant
argues that the Examiner fails to explain what reference teaches or suggests
the type of erase operation claimed. Appeal Br. 10.
The Examiner responds that the Final Rejection provides a rationale
why a person having ordinary skill in the art would have been motivated to
include the claimed features and Appellant has not challenged that rationale.
Ans. 7.
Because the Examiner has provided reasoning for why a person
having ordinary skill in the art would have been motivated to implement the
claimed protection (Final Act. 11), which Appellant does not challenge, we
affirm the obviousness rejection of claim 19.

Claims 35–40
Appellant argues that dependent claims 35–40 should be reversed
based on the same arguments presented with respect to their counterparts
that depend from claim 10. Appeal Br. 10.
Because we find Appellant’s arguments persuasive of error in the
rejection of dependent claims 29 and 31, we likewise reverse the rejection of
dependent claims 35 and 37. Claim 35 depends from claim 14 and recites,
like claim 29, “a nominal data retention time capability.” Id. at 16 (Claims
Appendix). Claim 37 depends from claim 14 and recites, like claim 31, “the
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smallest possible bias.” Id. Accordingly, we reverse the Examiner’s rejection
of dependent claims 35 and 37 for the same reasons discussed above with
respect to claims 29 and 31 and affirm the rejection of the remaining
dependent claims 36 and 38–40.

CONCLUSION
In summary:
Claim(s)
Rejected 35 U.S.C. § References/Basis Affirmed Reversed
31, 33, 37, 39 112(a) Written Description
31, 33, 37,
39
29, 31, 35, 37 112(b) Definiteness 29, 31, 35, 37
10, 11, 29, 31,
32, 33 102(a)(1) Chen
10, 11, 32,
33 29, 31
13, 30, 34 103 Chen 13, 30, 34
14–20, 35–40 103 Chen, Hartselle, Aasheim
14–20, 36,
38–40 35, 37
12 103 Chen, Hartselle, Perlegos 12
Overall
Outcome
10–20, 28,
30, 32–34,
36, 38–40
29, 31, 35,
37

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED IN PART