Godo Kaisha IP Bridge

Patent Trials and Appeals Board

Dec 2, 2021

IPR2020-01009 (P.T.A.B. Dec. 2, 2021)

Trials@uspto.gov Paper 34
571-272-7822 Date: December 2, 2021

UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE PATENT TRIAL AND APPEAL BOARD

MICRON TECHNOLOGY, INC.,
Petitioner,
v.
GODO KAISHA IP BRIDGE 1,
Patent Owner.

IPR2020-01009
Patent 6,747,320 B2

Before JUSTIN T. ARBES, DAVID C. McKONE, and AMBER L. HAGY,
Administrative Patent Judges.
ARBES, Administrative Patent Judge.
JUDGMENT
Final Written Decision
Determining All Challenged Claims Unpatentable
35 U.S.C. § 318(a)
I. INTRODUCTION
A. Background and Summary
Petitioner Micron Technology, Inc. (“Petitioner”), filed a Petition
(Paper 1, “Pet.”) requesting inter partes review of claims 1 and 4–6
of U.S. Patent No. 6,747,320 B2 (Ex. 1001, “the ’320 patent”) pursuant to
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35 U.S.C. § 311(a). On December 7, 2020, we instituted an inter partes
review as to all challenged claims on all grounds of unpatentability asserted
in the Petition. Paper 8 (“Decision on Institution” or “Dec. on Inst.”).
Patent Owner Godo Kaisha IP Bridge 1 (“Patent Owner”) subsequently filed
a Patent Owner Response (Paper 15, “PO Resp.”), Petitioner filed a Reply
(Paper 21, “Reply”), and Patent Owner filed a Sur-Reply (Paper 25,
“Sur-Reply”). An oral hearing was held on September 16, 2021, and a
transcript of the hearing is included in the record (Paper 33, “Tr.”).
We have jurisdiction under 35 U.S.C. § 6. This Final Written
Decision is issued pursuant to 35 U.S.C. § 318(a). For the reasons that
follow, we determine that Petitioner has shown by a preponderance of the
evidence that claims 1 and 4–6 are unpatentable.

B. Related Matters
The parties indicate that the ’320 patent is the subject of the following
pending district court case: Godo Kaisha IP Bridge 1 v. Micron Technology,
Inc., Case No. 20-cv-00178 (W.D. Tex.) (“the district court case”).
See Pet. 5; Paper 5, 1. Petitioner also filed petitions challenging claims of
other patents asserted in the district court case in Cases IPR2020-01007 and
IPR2020-01008.

C. The ’320 Patent
The ’320 patent states that “[t]he present invention relates to a
semiconductor device, and in particular, to an [embedded dynamic
random-access memory (EDRAM)], in which a [dynamic random-access
memory (DRAM)] is co-resident with a high-speed [complementary
metal-oxide-semiconductor (CMOS)] logic circuit.” Ex. 1001, col. 1,
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ll. 8–10. DRAM stores each bit of data in a memory cell consisting of a
metal-oxide-semiconductor (MOS) capacitor and a transistor. Ex. 1011, 25.
An “essential component” of DRAM designs is a “sense amplifier,” which
“amplif[ies] very small Read signals appearing on the I/O lines into full
CMOS data signals used at the output data buffer.” Ex. 1012, 91. The
’320 patent explains various problems associated with prior art sense
amplifier layouts. Ex. 1001, col. 1, ll. 12–30. A colored version of Figure 5
of the ’320 patent is reproduced below (Pet. 14).

Colored Figure 5 depicts “a mask layout of a conventional CMOS sense
amplifier transistor of a DRAM” where region I is a “N-type sense amplifier
transistor pair region formed on a P-type semiconductor substrate” and
region II is a “P-type sense amplifier transistor pair region formed on a
N-type semiconductor substrate.” Ex. 1001, col. 1, ll. 31–36. The N-type
sense amplifiers include active region 503 (shown in red) and the P-type
sense amplifiers similarly include an active region (shown in blue). Id. at
col. 1, ll. 53–57. Each sense amplifier transistor has ring-type gate electrode
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504 (shown in green). Id. at col. 1, ll. 37–38. “Drain regions of a pair of
upper and lower transistors in the ring-type gate electrodes 504 are
connected in a diagonally crossed manner to bit lines 507,” and power
source line 509 is “connected to a source region between a pair of ring-type
gate electrodes 504.” Id. at col. 1, ll. 38–45. Three sides of ring-type gate
electrode 504 are used as channels. Id. at col. 1, ll. 46–47.
The prior art ring-type gate electrode layout was problematic
according to the ’320 patent because “a parasitic capacitor (gate overlap
capacitor) is formed in a portion where one side of the ring-type gate
electrode 504 that does not function as a transistor is overlapped with an
active region 503, which degrades a high-speed property.” Id. at col. 1,
ll. 53–57. The manufacturing process of the ring-type gate electrode layout
also resulted in decreased sensitivity of the sense amplifier and undesirable
differences in transistor characteristics. Id. at col. 1, l. 62–col. 2, l. 14.
The ’320 patent seeks to solve those problems by “placing the gate
electrodes of the sense amplifier transistors in a line-and-space shape” such
that pairs of transistor gate electrodes are disposed “in one active region in
parallel to each other in the same direction as that of [the] bit lines.” Id. at
col. 2, ll. 22–39. A colored version of Figure 1A of the ’320 patent is
reproduced below (Pet. 16).

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Colored Figure 1A depicts “a plan view showing a mask layout of a DRAM
sense amplifier transistor” according to one embodiment of the invention.
Ex. 1001, col. 4, ll. 37–39. Pair of linear gate electrodes 104 (shown in
green) is formed in N-type sense amplifier active region 103 (shown in red)
“via a gate insulating film in the same direction as that of bit lines 107”
(shown in yellow). Id. at col. 4, ll. 42–47. The P-type sense amplifier active
region (shown in blue) has a similar arrangement. Id.
The active regions are isolated by shallow trench isolation (STI)
regions 102 formed on the semiconductor substrate. Id. Petitioner provides
an annotated version of Figure 1A, consistent with the disclosure of the
’320 patent and reproduced below (Pet. 17).

Annotated Figure 1A depicts STI region 102 (shown in orange) between two
adjacent pairs of N-type sense amplifier transistors (outlined in red) and two
adjacent pairs of P-type sense amplifier transistors (outlined in blue).
Ex. 1001, col. 4, ll. 42–47, Fig. 1B (depicting labeled STI region 102 in a
cross-sectional view of region I taken along line a–a'). The ’320 patent also
describes an embodiment utilizing field shield electrodes between adjacent
pairs of sense amplifier transistors instead of STI regions. Id. at col. 5,
ll. 24–62, Figs. 3A–3B. According to the ’320 patent, the disclosed layout
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reduces the variation in gate processing size, suppressing the “difference[s]
in transistor characteristics” present in the prior art, and results in a sense
amplifier with “high performance.” Id. at col. 2, ll. 35–39.

D. Illustrative Claims
Challenged claims 1 and 4 of the ’320 patent are independent. Claims
5 and 6 depend from claim 4. Claims 1 and 4 recite:
1. A semiconductor device comprising a DRAM region
and a high-speed CMOS logic region that are co-resident with
each other,
wherein a pair of gate electrodes of a N-type sense
amplifier transistor and a pair of gate electrodes of a P-type sense
amplifier transistor constituting a CMOS sense amplifier of the
DRAM are disposed respectively in one active region in parallel
to each other in the same direction as that of bit lines, and a pair
of adjacent N-type sense amplifier transistors and a pair of
adjacent P-type sense amplifier transistors are isolated by
shallow trench isolation (STI) regions.
4. A semiconductor device comprising a DRAM region
and a high-speed CMOS logic region that are co-resident with
each other,
wherein a pair of gate electrodes of a N-type sense
amplifier transistor and a pair of gate electrodes of a P-type sense
amplifier transistor constituting a CMOS sense amplifier of the
DRAM are disposed respectively in one active region in parallel
to each other in the same direction as that of bit lines, active
regions are connected to each other in a pair of adjacent N-type
sense amplifier transistors and a pair of adjacent P-type sense
amplifier transistors, and on the active regions, field shield
electrodes are disposed between the pair of adjacent N-type sense
amplifier transistors and between the pair of adjacent P-type
sense amplifier transistors so as to be parallel to the pair of gate
electrodes of each of the sense amplifier transistors.

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E. Evidence
The pending grounds of unpatentability in the instant inter partes
review are based on the following prior art:
U.S. Patent No. 6,477,100 B2, filed Aug. 22, 2001, issued
Nov. 5, 2002 (Ex. 1006, “Takemura”);
U.S. Patent No. 6,018,172, issued Jan. 25, 2000 (Ex. 1004,
“Hidaka”);
U.S. Patent No. 5,883,814, issued Mar. 16, 1999
(Ex. 1005, “Luk”); and
U.S. Patent No. 4,730,280, issued Mar. 8, 1988 (Ex. 1007,
“Aoyama”).
Petitioner filed a declaration from John C. Bravman, Ph.D. (Ex. 1003) with
its Petition and a reply declaration from Dr. Bravman (Ex. 1031) with its
Reply. Patent Owner filed a declaration from Konstantinos P. Giapis, Ph.D.
(Ex. 2025) with its Response. Also submitted as evidence are transcripts of
the depositions of Dr. Bravman (Exs. 2027, 2055) and Dr. Giapis
(Ex. 1028).

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F. Asserted Grounds
The instant inter partes review involves the following grounds of
unpatentability:
Claim(s)
Challenged 35 U.S.C. § References/Basis
1 103(a)1 Hidaka, Luk, Takemura2
4–6 103(a) Hidaka, Luk

1 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
(2011) (“AIA”), amended 35 U.S.C. § 103. Because the challenged claims
of the ’320 patent have an effective filing date before the effective date of
the applicable AIA amendment, we refer to the pre-AIA version of
35 U.S.C. § 103.
2 Petitioner asserts for each of its obviousness grounds that the challenged
claims would have been obvious over the cited references “considered in
view of the knowledge of a person of ordinary skill in the art.” See Pet. 7,
39, 58, 68, 78. As explained in the Decision on Institution, we do not
include the general knowledge of a person of ordinary skill in the art in
listing the grounds themselves, recognizing that such knowledge is
considered in every obviousness analysis. See Dec. on Inst. 7 n.3; 35 U.S.C.
§ 311(b) (inter partes review “only on the basis of prior art consisting of
patents or printed publications”); Koninklijke Philips N.V. v. Google LLC,
948 F.3d 1330, 1337 (Fed. Cir. 2020) (“Although the prior art that can be
considered in inter partes reviews is limited to patents and printed
publications, it does not follow that we ignore the skilled artisan’s
knowledge when determining whether it would have been obvious to modify
the prior art. . . . Regardless of the tribunal, the inquiry into whether any
‘differences’ between the invention and the prior art would have rendered
the invention obvious to a skilled artisan necessarily depends on such
artisan’s knowledge.”); Randall Mfg. v. Rea, 733 F.3d 1355, 1362–63
(Fed. Cir. 2013) (“[T]he knowledge of [an ordinarily skilled] artisan is part
of the store of public knowledge that must be consulted when considering
whether a claimed invention would have been obvious.”); Dow Jones & Co.
v. Ablaise Ltd., 606 F.3d 1338, 1349 (Fed. Cir. 2010) (“[The obviousness]
analysis requires an assessment of the . . . ‘background knowledge possessed
by a person having ordinary skill in the art.’” (citing KSR Int’l Co. v.
Teleflex Inc., 550 U.S. 398, 401 (2007))).
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Claim(s)
Challenged 35 U.S.C. § References/Basis
1 103(a) Aoyama, Luk, Takemura
4–6 103(a) Aoyama, Luk, Hidaka

II. ANALYSIS
A. Level of Ordinary Skill in the Art
In determining the level of ordinary skill in the art for a challenged
patent, we look to “1) the types of problems encountered in the art; 2) the
prior art solutions to those problems; 3) the rapidity with which innovations
are made; 4) the sophistication of the technology; and 5) the educational
level of active workers in the field.” Ruiz v. A.B. Chance Co., 234 F.3d 654,
666–667 (Fed. Cir. 2000). “Not all such factors may be present in every
case, and one or more of them may predominate.” Id.
Petitioner states that it assumes an effective filing date of August 7,
2002, for the ’320 patent, and argues that a person of ordinary skill in the art
at that time would have had “a degree in electrical engineering, physics,
materials science, or a similar discipline, along with 3–4 years of experience
with the design and fabrication of MOS integrated circuits,” and would have
been “aware of and generally knowledgeable about the structure and
operation of DRAM” and “DRAM sense amplifiers, including their
structure, operation, and physical layout.” Pet. 6, 39 (citing Ex. 1003
¶¶ 34–37). Patent Owner “does not challenge” Petitioner’s proposed level of
ordinary skill in the art. PO Resp. 13; see Ex. 2025 ¶ 31. Based on the full
record developed during trial, including our review of the ’320 patent and
the types of problems and solutions described in the ’320 patent and cited
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prior art, we agree with Petitioner’s assessment of the level of ordinary skill
in the art and apply it for purposes of this Decision.

B. Claim Interpretation
We interpret the claims of the challenged patent
using the same claim construction standard that would be used to
construe the [claims] in a civil action under 35 U.S.C. 282(b),
including construing the [claims] in accordance with the ordinary
and customary meaning of such [claims] as understood by one of
ordinary skill in the art and the prosecution history pertaining to
the patent.
37 C.F.R. § 42.100(b) (2019). “In determining the meaning of [a] disputed
claim limitation, we look principally to the intrinsic evidence of record,
examining the claim language itself, the written description, and the
prosecution history, if in evidence.” DePuy Spine, Inc. v. Medtronic
Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006). Claim terms
are given their plain and ordinary meaning as would be understood by a
person of ordinary skill in the art at the time of the invention and in the
context of the entire patent disclosure. Phillips v. AWH Corp., 415 F.3d
1303, 1313 (Fed. Cir. 2005) (en banc). “There are only two exceptions to
this general rule: 1) when a patentee sets out a definition and acts as his own
lexicographer, or 2) when the patentee disavows the full scope of a claim
term either in the specification or during prosecution.” Thorner v. Sony
Comput. Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012).
Petitioner proposes interpretations for the claim terms “parallel,”
“field shield electrode,” and “between the pair of adjacent N-type sense
amplifier transistors and between the pair of adjacent P-type sense amplifier
transistors.” Pet. 19–23. In the Decision on Institution, we determined
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based on the record at the time that no claim terms required express
interpretation. Dec. on Inst. 24. Subsequent to that Decision, the district
court in the district court case construed the following terms in claim 1 of
the ’320 patent to each have its “[p]lain-and-ordinary meaning”: “a DRAM
region and a high-speed CMOS logic region that are co-resident with each
other,” “sense amplifier transistor,” “a N-type sense amplifier transistor and
. . . a P-type sense amplifier transistor constituting a CMOS sense
amplifier,” and “parallel.” Ex. 3001, 3–4.
Patent Owner in its Response argues that no express interpretation of
any claim term is necessary. PO Resp. 14. Petitioner in its Reply makes
various arguments regarding Patent Owner’s infringement contentions in the
district court case, which we address below in Section II.D.4.b.(1), but does
not propose a specific interpretation for any language in the claims.
See Reply 4–7. Based on the full record developed during trial, we conclude
that no terms require express interpretation to determine whether Petitioner
has met its burden to prove unpatentability of the challenged claims.
See Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d
1013, 1017 (Fed. Cir. 2017) (“Because we need only construe terms ‘that are
in controversy, and only to the extent necessary to resolve the controversy,’
we need not construe [a particular claim limitation] where the construction is
not ‘material to the . . . dispute.’” (citations omitted)).

C. Legal Standards
A claim is unpatentable for obviousness if, to one of ordinary skill in
the pertinent art, “the differences between the subject matter sought to be
patented and the prior art are such that the subject matter as a whole would
have been obvious at the time the invention was made.” KSR, 550 U.S. at
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406 (quoting 35 U.S.C. § 103(a) (2006)). The question of obviousness is
resolved on the basis of underlying factual determinations, including “the
scope and content of the prior art”; “differences between the prior art and the
claims at issue”; and “the level of ordinary skill in the pertinent art.”
Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966). Additionally,
secondary considerations, such as “commercial success, long felt but
unsolved needs, failure of others, etc., might be utilized to give light to the
circumstances surrounding the origin of the subject matter sought to be
patented. As indicia of obviousness or nonobviousness, these inquiries may
have relevancy.”3 Id. When conducting an obviousness analysis, we
consider a prior art reference “not only for what it expressly teaches, but also
for what it fairly suggests.” Bradium Techs. LLC v. Iancu, 923 F.3d 1032,
1049 (Fed. Cir. 2019) (citation omitted).
A patent claim “is not proved obvious merely by demonstrating that
each of its elements was, independently, known in the prior art.” KSR,
550 U.S. at 418. An obviousness determination requires finding “both ‘that
a skilled artisan would have been motivated to combine the teachings of the
prior art references to achieve the claimed invention, and that the skilled
artisan would have had a reasonable expectation of success in doing so.’”
Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd., 821 F.3d 1359,
1367–68 (Fed. Cir. 2016); see KSR, 550 U.S. at 418 (for an obviousness
analysis, “it can be important to identify a reason that would have prompted
a person of ordinary skill in the relevant field to combine the elements in the
way the claimed new invention does”).

3 Patent Owner has not presented any evidence of secondary considerations
of nonobviousness in this proceeding.
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“Although the KSR test is flexible, the Board ‘must still be careful not
to allow hindsight reconstruction of references . . . without any explanation
as to how or why the references would be combined to produce the claimed
invention.’” TriVascular, Inc. v. Samuels, 812 F.3d 1056, 1066 (Fed. Cir.
2016) (alteration in original). Further, an assertion of obviousness “cannot
be sustained by mere conclusory statements; instead, there must be some
articulated reasoning with some rational underpinning to support the legal
conclusion of obviousness.” KSR, 550 U.S. at 418 (quoting In re Kahn,
441 F.3d 977, 988 (Fed. Cir. 2006)); accord In re NuVasive, Inc., 842 F.3d
1376, 1383 (Fed. Cir. 2016) (stating that “conclusory statements” amount to
an “insufficient articulation[] of motivation to combine”; “instead, the
finding must be supported by a ‘reasoned explanation’”); In re Magnum Oil
Tools Int’l, Ltd., 829 F.3d 1364, 1380 (Fed. Cir. 2016) (“To satisfy its
burden of proving obviousness, a petitioner cannot employ mere conclusory
statements. The petitioner must instead articulate specific reasoning, based
on evidence of record, to support the legal conclusion of obviousness.”).

D. Obviousness Ground Based on Hidaka, Luk, and Takemura (Claim 1)
1. Hidaka
Hidaka discloses “a dynamic random access memory (DRAM)
formed on an SOI (Silicon On Insulator) substrate.”4 Ex. 1004, col. 1,

4 SOI technology involves “a crystalline Si film . . . grown on a layer of
oxide or nitride formed on Si wafers.” Ex. 1011, 57; see also PO Resp.
15–16; Ex. 1004, col. 6, ll. 44–46 (“SOI substrate 38 is formed of a p-type
silicon substrate 40, a buried oxide film 42 made of SiO2 and an SOI active
layer 44.”), Fig. 5; Ex. 2025 ¶¶ 42–43; Ex. 2032, col. 4, ll. 23–25 (describing
“a silicon-on-insulator structure comprised of silicon layer 33 on an oxide
layer 32 which is on a substrate 30”), Fig. 2; Ex. 2045, 1–2 (“[O]n the bulk
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ll. 16–19. Hidaka states that “further increase of the degree of integration of
DRAMs has been desired,” which in the past required “reduc[ing] the gate
length.” Id. at col. 1, ll. 50–55. Doing so, however, caused a “short channel
effect,” “leak through the transfer gate,” and “a high possibility of breakage
of data.” Id. at col. 1, l. 55–col. 2, l. 44. Hidaka’s disclosed “semiconductor
memory device formed on an SOI substrate” purportedly reduces such leak
current and has “a minimum layout area.” Id. at col. 2, ll. 47–54.
DRAM 10 in Hidaka includes memory cell array group 11 and sense
amplifier band 14 with “a plurality of P-channel sense amplifier groups 70
and a plurality of N-channel sense amplifier groups 72.” Id. at col. 5,
ll. 40–47, col. 9, ll. 5–12, Figs. 2, 9. “Each N-channel sense amplifier group
72 is provided with a plurality of N-channel sense amplifiers 74. Each sense
amplifier 74 includes cross-coupled N-channel MOS transistors 76 and 78.”
Id. at col. 9, ll. 14–17. “P-channel sense amplifier group 70 has a structure
similar to N-channel sense amplifier group 72, and operates in the
substantially same manner.” Id. at col. 9, ll. 41–43.

silicon substrate, a buried oxide layer is formed. On the top of the buried
oxide layer there is a silicon thin-film, where active MOS devices and
circuits are located.”).
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Figure 10 of Hidaka is reproduced below.5

Figure 10 depicts “structures of the P- and N-channel sense amplifiers . . .
as well as the drive transistors for driving these sense amplifiers, equalize
transistors for equalizing the potentials of bit line pairs and others.” Id. at
col. 10, ll. 26–30. “[G]ate electrode line 116 of N-channel MOS transistor
76 in N-channel sense amplifier 74 is connected to bit line /BL1 or /BL2.”
Id. at col. 10, ll. 30–32. “Gate electrode line 116 of N-channel MOS
transistor 78 is connected to bit line BL1 or BL2.” Id. at col. 10, ll. 32–34.
Hidaka similarly describes P-channel MOS transistors 124 and 126 of
P-channel sense amplifier 122, with gate electrodes 128 also connected to
the bit lines. Id. at col. 10, ll. 41–45.

2. Luk
Luk discloses “single chip implementations of logic and memory
components,” in particular “a method for system-on-chip layout automation

5 Figure 10 of Hidaka was corrected in a Certificate of Correction dated
May 8, 2001. See Ex. 1004; Pet. 26 n.4.
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which translates (compiles) a hardware description language (HDL) of a
design, consisting of logic components and memory components, into a
layout on a silicon chip, with optimized floor plan, macro and layout
structures of logic and dynamic random access memory (DRAM) circuits.”
Ex. 1005, col. 1, ll. 5–13. Figures 1 and 2 of Luk are reproduced below.

Figure 1 depicts “a conventional multi-chip processor and memory system in
which the processor 11 is connected to the memory 12, typically composed
of DRAM chips, by means of off-chip interconnections 13 (e.g., a system
bus).” Id. at col. 3, ll. 6–10. “This system suffers the problems of limited
bandwidth due to the off-chip interconnections and high power dissipation
due to large capacitive loading.” Id. at col. 3, ll. 11–13. Figure 2 depicts
“a single processor memory chip in which the processor 21 is connected to
the DRAM 22 by means of on-chip interconnections 23.” Id. at col. 3,
ll. 14–16. Luk discloses that because there are no off-chip interconnections,
“the bandwidth problems can be mostly eliminated since the amount of
memory data transfer rate (bits per unit time) available to the processor can
be made orders of magnitude higher by directly accessing the DRAM I/O
and internal controls.” Id. at col. 3, ll. 16–21.
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Luk discloses the use of a “DRAM compiler/configurator” to create,
“from basic DRAM building blocks, the physical structure, circuit, and
layout of embedded, growable DRAM macros, with different amount[s] of
memory capacity, banking, and input/output (I/O) bandwidth, different
addressing schemes, different mode of operations, . . . and timing
requirements for a wide range of integrated logic/DRAM applications.”
Id. at col. 1, ll. 52–62, col. 5, l. 56–col. 6, l. 59, Fig. 9. “Starting from a
hardware description language (HDL) of a chip design which consists of
memory components and logic components, through a sequence of
computer-aided design (CAD) steps, the HDL can be ‘compiled’ into chip
floor plan, macro layouts, and then finally into the complete layout of a
chip.” Id. at col. 5, ll. 57–63. The result of the compilation method is “the
overall chip layout for the integrated logic/DRAM chip.” Id. at col. 6,
ll. 9–11.

3. Takemura
Takemura discloses a semiconductor device including a
“large-capacity DRAM.” Ex. 1006, col. 1, ll. 14–16, 60–65. The DRAM
includes multiple “sub-memory array[s]” each “divided into a memory cell
area MCA [and] a sense amplifier area SAA.” Id. at col. 6, ll. 7–10, Fig. 23.
Each sense amplifier has “a source in common connection, a PMOS pair of
cross-coupled gate and drain, and an NMOS pair of cross-coupled gate and
drain.” Id. at col. 7, ll. 7–11. Takemura describes a sense amplifier circuit
with a “SGI (shallow groove isolation) indicat[ing] an insulating part for
isolation of each diffusion layer, . . . which is formed by embedding a
material such as Si oxide into a shallow groove in the substrate.” Id. at
col. 12, l. 61–col. 13, l. 64, Figs. 12(a)–(b), 13.
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4. Analysis
Petitioner argues that claim 1 is unpatentable over Hidaka, Takemura,
and Luk6 under 35 U.S.C. § 103(a), relying on the testimony of Dr. Bravman
as support. Pet. 39–58 (citing Ex. 1003). Patent Owner makes various
arguments in response, relying on the testimony of Dr. Giapis. PO Resp.
21–58 (citing Ex. 2025); Sur-Reply 1–22.

a) Undisputed Issues
Petitioner relies on Hidaka for the majority of the limitations of
claim 1. Pet. 39–58. Petitioner contends that Hidaka teaches a
semiconductor device comprising logic circuitry and a “DRAM region” (i.e.,
DRAM 10 with sense amplifier band 14) having “a pair of gate electrodes of
a N-type sense amplifier transistor and a pair of gate electrodes of a P-type
sense amplifier transistor constituting a CMOS sense amplifier.” Id. at 40,
42–47. Each N-channel sense amplifier 74 includes N-channel MOS
transistors 76 and 78, each P-channel sense amplifier includes similar
P-channel MOS transistors, and the complementary N- and P-type
transistors thus form a CMOS sense amplifier according to Petitioner. Id. at
42–43 (citing Ex. 1004, col. 9, ll. 8–11, 14–17, 41–43).
As to the structure of the transistors, claim 1 recites that the pairs of
gate electrodes of the sense amplifier transistors “are disposed respectively
in one active region in parallel to each other in the same direction as that of
bit lines.” Petitioner provides the following annotated version of Figure 18

6 Hidaka, Luk, and Takemura were not of record during prosecution of the
’320 patent. See Ex. 1001, code (56); Pet. 6.
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of Hidaka, which we find, based on the full trial record, is consistent with
Hidaka’s disclosure (id. at 44).

Annotated Figure 18 depicts gate electrode lines 116 (shown in green) of
transistors 76 and 78 of N-channel sense amplifier 74 (outlined in red)
disposed in active region 170 (shown in red). Id. at 43–44. According to
Petitioner, the pairs of gate electrodes are parallel to each other and in the
same direction as the bit lines BL1 and /BL1. Id. at 44–45 (also citing
Ex. 1004, col. 9, ll. 41–43, as teaching that the P-channel sense amplifiers
have a “similar” structure).

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Petitioner further provides the following annotated version of
Figure 10 of Hidaka, which we find, based on the full trial record, is
consistent with Hidaka’s disclosure (id. at 47).

Annotated Figure 10 depicts N-channel sense amplifier 74 (outlined in red)
and P-channel sense amplifier 122 (outlined in blue) with gate electrode
lines 116 (shown in green) parallel to each other and to bit lines BL1 and
/BL1 (shown in yellow). Id. at 46–47.
Claim 1 also recites that “a pair of adjacent N-type sense amplifier
transistors and a pair of adjacent P-type sense amplifier transistors are
isolated by shallow trench isolation (STI) regions” (“the shallow trench
isolation limitation”). Petitioner argues that Hidaka teaches “two adjacent
N-type sense amplifiers 74, each of which is formed by a pair of transistors
(i.e., N-channel MOS transistor 76 and N-channel MOS transistor 78) with
gate electrodes 116,” as shown in Figures 17 and 18, and the P-type sense
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amplifiers have a similar structure. Id. at 47–48. Petitioner further contends
that active areas 170 for adjacent N-type sense amplifiers are not connected
and thus are “isolated from each other,” as shown in the following annotated
version of Figure 18 (id. at 48).

Annotated Figure 18 depicts isolation (shown in orange) between adjacent
N-type sense amplifier transistors (shown in red), as argued by Petitioner.
Id. Petitioner acknowledges that “Hidaka does not detail how the isolation
between the active areas 170 has been effectuated,” but points out that
Hidaka in other instances uses local oxidation of silicon (LOCOS) films 46
to isolate adjacent transistors. Id. at 50 (citing Ex. 1004, col. 6, ll. 53,
59–61, Fig. 6).
Claim 1, though, requires STI rather than LOCOS isolation.
Petitioner relies on Takemura’s teaching of “shallow groove isolation”
(which a person of ordinary skill in the art would have understood to be
synonymous with STI according to Dr. Bravman) to isolate transistors of
a sense amplifier. Id. at 38 n.5 (citing Ex. 1003 ¶¶ 171–175), 51–53 (citing
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Ex. 1006, col. 13, ll. 60–64, Fig. 13). According to Petitioner, a person of
ordinary skill in the art would have been motivated to use STI to isolate
adjacent transistors in Hidaka’s DRAM for a number of reasons, including
that “STI was a known alternative to LOCOS,” STI was “known to eliminate
certain disadvantages inherent in the LOCOS isolation method” (e.g., an
undesirable “bird’s beak structure” from a laterally extending field oxide),
and STI can provide isolation for narrow spacing, allowing a more compact
device. Id. at 56–58. Petitioner further contends that a person of ordinary
skill in the art would have had a reasonable expectation of success in
achieving the claimed semiconductor device by modifying Hidaka’s device
to use the known STI method. Id. at 58.
Patent Owner does not dispute that Hidaka and Takemura teach the
above limitations of claim 1 or that a person of ordinary skill in the art
would have been motivated to combine the references’ teachings in the
manner asserted by Petitioner and would have had a reasonable expectation
of success in doing so; therefore, any such arguments are waived. See
Novartis AG v. Torrent Pharms. Ltd., 853 F.3d 1316, 1330 (Fed. Cir. 2017);
NuVasive, 842 F.3d at 1380–81; Paper 11, 8 (“Patent Owner is cautioned
that any arguments for patentability not raised in the response may be
deemed waived.”). Petitioner’s analysis for each of the limitations,
supported by the testimony of Dr. Bravman, which we credit, is persuasive.
See Pet. 40, 42–53, 56–58; Ex. 1003 ¶¶ 178–181, 195–244, 263–278,
288–293.

b) Disputed Issue: The Co-Resident Limitation
The sole issue disputed by Patent Owner pertains to the limitation of
claim 1 that the “DRAM region” and “high-speed CMOS logic region” of
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the claimed semiconductor device be “co-resident with each other” (“the
co-resident limitation”). Petitioner makes two arguments regarding the
co-resident limitation, relying on (1) Hidaka alone, and (2) modifying
Hidaka’s device based on the teachings of Luk. Pet. 39–42, 53–58.

(1) Hidaka Alone
Petitioner first relies on Hidaka alone. Pet. 40. Hidaka discloses that
DRAM 10, shown in Figure 2, is a “16 Mbit DRAM having a structure of
4 Mbitsx4” and includes “memory cell array group 11, a row decoder 12,
a column decoder 13, a sense amplifier band 14, an I/O circuit 15,
a row/column address buffer 16, an input buffer 17, an output buffer 18 and
a clock generating circuit 19.” Ex. 1004, col. 5, ll. 40–47. Petitioner argues
that based on this disclosure of “standard” DRAM peripheral circuitry,
“Hidaka’s DRAM, like any DRAM, . . . includes various peripheral logic
circuits,” and “[i]f this is all the ’320 patent requires, then the analysis need
go no further” because Hidaka teaches the co-resident limitation. Pet. 40.
In the Decision on Institution, we found, based on the record at the
time, that Hidaka alone does not teach the co-resident limitation. Dec. on
Inst. 31–32. We reach the same conclusion based on the full trial record.
The premise of Petitioner’s conditional “[i]f” statement—that claim 1
requires only that a DRAM have associated logic circuitry—is incorrect.
See Pet. 40. Claim 1 plainly recites that the “DRAM region” and
“high-speed CMOS logic region” must be “co-resident with each other,” not
that they merely exist. Hidaka teaches that its DRAM has associated logic
circuitry, but does not state specifically that the circuitry is a “high-speed
CMOS logic region” and does not disclose whether the DRAM and
associated logic circuitry are on the same device or different devices.
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Indeed, Petitioner acknowledges that “Hidaka does not . . . expressly state or
provide an example of DRAM that is ‘co-resident’ on the same chip with a
completely separate, non-DRAM ‘CMOS logic region’ like a processor.”
Id.
Petitioner in its Reply argues that “Patent Owner has conceded
obviousness under its district court interpretation of the claims.” Reply 4.
Petitioner’s position appears to be that Patent Owner’s accusation that
Petitioner’s various DRAM devices infringe the challenged claims shows
that Hidaka, which describes DRAM devices having common features, also
teaches the co-resident limitation. Id. at 4–7. In particular, Petitioner argues
that
[g]iven that Patent Owner (1) does not dispute that Hidaka
includes sense amplifiers and the same type of “logic” as any
other DRAM, and (2) itself asserts in District Court that DRAM
sense amplifiers are “co-resident” “high-speed CMOS logic,”
Patent Owner has conceded obviousness based on Hidaka under
its own interpretation of the claims. In view of this, Petitioner
requests entry of a decision that Hidaka alone teaches a “DRAM
region” and “co-resident” “high-speed CMOS logic region”
under Patent Owner’s claim interpretation, or a ruling that the
claims cannot be interpreted in the manner Patent Owner
proposes.
Id. at 6.
We disagree. Petitioner bears the burden to prove unpatentability
under the theories advanced in its Petition, not any theory argued by Patent
Owner in the district court case. Moreover, Petitioner does not point to any
“interpretation” of the co-resident limitation that Patent Owner allegedly
advanced in the district court case. Rather, Petitioner merely cites—without
pointing to any specific portion of the documents or explaining how they are
relevant—Exhibits 1029 and 1030, which are excerpts from an infringement
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claim chart and supplemental infringement claim chart in the district court
case.7 See id. at 5. Even if it was appropriate to look to Patent Owner’s
allegations as to how a particular accused product allegedly infringes the
claims, Petitioner has not explained, and we fail to see, how that equates
with an “interpretation” of the co-resident limitation. Nor has Petitioner
explained how Patent Owner’s infringement allegations mean Patent Owner
“conceded” that Hidaka teaches the limitation, particularly where there is
no allegation that Hidaka’s device is identical to the accused products.
For the reasons explained above, we are not persuaded that Hidaka
alone teaches the co-resident limitation.

(2) Modification to Hidaka Based on the Teachings of Luk
Petitioner’s second argument regarding the co-resident limitation is
based on a combination of Hidaka and Luk.
The Specification of the ’320 patent states that the “present invention”
relates to “an EDRAM, in which a DRAM is co-resident with a high-speed
CMOS logic circuit.” Ex. 1001, col. 1, ll. 8–10; see Pet. 40–42. The
’320 patent describes such known “co-resident” devices in the “Background
of the Invention” section. See Ex. 1001, col. 1, ll. 5, 16–28 (stating that
embedded DRAMs having both a DRAM and associated logic circuitry had
been “put into practical use” and that there were a number of techniques and

7 Petitioner appears to have submitted redacted portions of these exhibits,
without filing unredacted confidential versions and a motion to seal as
required by our rules. See 37 C.F.R. §§ 42.14, 42.54. Under the
circumstances, because we disagree with Petitioner as to the relevance of the
exhibits, we will not require any additional filings. See 37 C.F.R. § 42.5(b).
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fabrication processes known at the time to create “a commodity DRAM [that
is] co-resident with a high-speed logic”).
Petitioner contends that it was well-known at the time of the
’320 patent that a DRAM “could be integrated or embedded along with a
separate logic circuitry onto a single semiconductor chip” and “Luk provides
an example” of such integration. Pet. 41. Luk teaches, for example,
processor 21 connected to DRAM 22 on a single chip via on-chip
interconnections 23. Ex. 1005, col. 3, ll. 14–16, Fig. 2. Luk also explains
that an “integrated logic/DRAM chip” can be designed using “0.25 micron
CMOS technology.” Id. at col. 12, ll. 37–43. The “Unified Media Memory
(UMM)” chip described in Luk includes a synchronous DRAM (SDRAM)
and “logic functions” performed using a graphic processor for, among other
things, “high speed import/export” of data. Id. at col. 12, ll. 38–62. Luk,
therefore, teaches that a DRAM can be embedded on a chip with a
“high-speed CMOS logic region,” according to Petitioner. Pet. 42.
Petitioner provides a detailed explanation, with supporting testimony
from Dr. Bravman, for why a person of ordinary skill in the art would have
been motivated to “follow Luk’s teaching and embed Hidaka’s DRAM
along with CMOS logic on the same semiconductor chip.” Id. at 54–58
(citing Ex. 1003 ¶¶ 246–262, 279–287). According to Petitioner, Hidaka
expresses a desire to “increase . . . the degree of integration” of DRAMs, and
implementing Hidaka’s DRAM with logic circuitry on the same chip would
increase integration. See id. at 54 (quoting Ex. 1004, col. 1, ll. 50–58).
Further, Petitioner argues that Luk expressly discloses numerous benefits
from embedding a DRAM with CMOS logic, including minimizing “the
difference between the maximum data processing rate of the logic processor
and maximum data access rate of the DRAM memory,” permitting more
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layout flexibility, and providing for lower power dissipation, higher speed
operation, and “optimize[d] . . . overall performance” due to “heavy
capacitive loads” not being required. Id. at 54–55 (quoting Ex. 1005, col. 2,
ll. 4–30) (alterations in original). Petitioner also cites another reference,
Betty Prince, Semiconductor Memories: A Handbook of Design,
Manufacture, and Application 51 (2d ed. 1991) (Ex. 1013, “Prince”), as
evidencing that an ordinarily skilled artisan would have known that
embedded memory allows for greater performance by reducing bandwidth
problems and eliminating the need for interface circuitry and package leads.
Pet. 55. Dr. Bravman opines that
these benefits of embedded DRAM—both expressed in Luk and
generally known in the art—would have motivated one of
ordinary skill in the art as of the filing of the ’320 patent to embed
Hidaka’s DRAM on the same chip as logic. One of ordinary skill
in the art would recognize that in doing so, Hidaka’s DRAM, and
the logic that it is associated with, would [have] a lower power
usage, faster more optimized performance, and improved design
flexibility.
Ex. 1003 ¶ 256.
Finally, Petitioner contends that embedded DRAM was a known
variation to DRAM as a stand-alone memory device, and “[e]mbedding
Hidaka’s DRAM onto a chip with logic, instead of forming that DRAM on
its own chip, would have been considered nothing more than a routine and
straightforward design choice.” Pet. 55–58. Dr. Bravman testifies that both
separate DRAM and embedded DRAM were well-known and “a person
having ordinary skill in the art would not have considered Hidaka’s DRAM
to be limited to one form versus the other,” such that it was within the skill
of an ordinarily skilled artisan to implement Hidaka’s DRAM on the same
device as CMOS logic circuitry. Ex. 1003 ¶¶ 282–285.
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Patent Owner makes a number of arguments challenging the asserted
combination of Hidaka and Luk.
First, Patent Owner argues that a person of ordinary skill in the art
would not have made the proposed combination because Luk integrates
DRAM and CMOS logic on a “bulk” substrate, not SOI. PO Resp. 19–21,
27 (citing Ex. 2025 ¶¶ 69–77). Patent Owner contends that “Luk never
mentions a SOI solution or challenges using SOI, and a [person of ordinary
skill in the art] would not have understood Luk to contemplate integrating a
SOI-based DRAM with CMOS logic.” Id. at 20. Further, according to
Patent Owner,
[t]he only mention of SOI in Luk is to distinguish SOI-based
designs as an inadequate alternative to the integration problem
Luk says he solves because, according to Luk, SOI-based designs
result in DRAM and CMOS on different chips and Luk wanted
DRAM and CMOS on what Luk characterized as the same chip.
Id. at 20–21 (citing Ex. 1005, col. 1, ll. 28–37).
We disagree that a person of ordinary skill in the art would have
understood Luk’s teachings to be limited solely to “bulk” substrates. Patent
Owner is correct that Luk refers to integrating a DRAM and CMOS logic on
a “single chip.” See id. at 19. But Luk never states that this refers only to
the “bulk” substrate of a chip. Indeed, the words “bulk” and “substrate” do
not appear in the reference. To the contrary, Luk speaks broadly to “single
chip implementations of logic and memory components” and a method of
“system-on-chip layout automation” to create a design of logic and memory
components on a single chip “with [an] optimized floor plan [and] macro
and layout structures” (without mentioning or requiring that any particular
substrate be used). Ex. 1005, col. 1, ll. 6–14. Luk also describes the
problems associated with the conventional approach of separate DRAM and
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processor chips and the general solution of a “single processor memory
chip” in which the DRAM and processor are connected by “on-chip
interconnections” (again without mentioning or requiring that any particular
substrate be used). Id. at col. 3, ll. 6–21, Figs. 1, 2.
Importantly, the record demonstrates that the benefits of
DRAM-CMOS logic integration that Petitioner points to as the basis for its
obviousness argument apply regardless of the type of substrate used. See
Pet. 54–55; Reply 11–12.8 We credit the supporting testimony of

8 Patent Owner contends that Petitioner’s arguments in the Reply that Luk
applies to all types of substrates are improper new arguments that cannot be
considered. Sur-Reply 17–18. We disagree. Petitioner discusses the stated
benefits of DRAM-CMOS logic integration in the Petition, then, in its
Reply, responds to Patent Owner’s arguments that Luk limits those benefits
to “bulk” substrate devices. See Pet. 54–55; PO Resp. 38; Reply 11–12.
Our rules countenance such rebuttal. See 37 C.F.R. § 42.23(b) (“A reply
may only respond to arguments raised in the corresponding . . . patent owner
response . . . .”); Patent Trial and Appeal Board Consolidated Trial Practice
Guide (Nov. 2019), 73–74, available at https://www.uspto.gov/
TrialPracticeGuideConsolidated (“Petitioner may not submit new evidence
or argument in reply that it could have presented earlier, e.g. to make out a
prima facie case of unpatentability. . . . Generally, a reply or sur-reply may
only respond to arguments raised in the preceding brief. . . . ‘Respond,’ in
the context of 37 C.F.R. § 42.23(b), does not mean proceed in a new
direction with a new approach as compared to the positions taken in a prior
filing. While replies and sur-replies can help crystalize issues for decision,
a reply or sur-reply that raises a new issue or belatedly presents evidence
may not be considered.”); Anacor Pharms., Inc. v. Iancu, 889 F.3d 1372,
1380–81 (Fed. Cir. 2018) (noting that “the petitioner in an inter partes
review proceeding may introduce new evidence after the petition stage if the
evidence is a legitimate reply to evidence introduced by the patent owner, or
if it is used ‘to document the knowledge that skilled artisans would bring to
bear in reading the prior art identified as producing obviousness,’” and
determining that it was proper for the Board to rely on two references not
cited in the petition but discussed at length in the “patent owner’s response
and related submissions”); Idemitsu Kosan Co., Ltd. v. SFC Co. Ltd.,
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Dr. Bravman on this point, as it is consistent with Luk and a number of other
references in the record, and disagree with Patent Owner’s unsupported
contention that Luk’s benefits are only realized by using a “bulk” substrate.
See Ex. 1003 ¶¶ 248–255; Ex. 1031 ¶¶ 11–27; PO Resp. 38 (citing Ex. 2025
¶ 140). For example, Luk expressly discloses the benefits of a reduced
communication bottleneck between the memory and processor, elimination
of “heavy capacitive loads,” lower power dissipation, higher speed
operation, improved performance, and increased ability to modify and
customize a desired layout. See, e.g., Ex. 1005, col. 1, ll. 16–37, col. 2,
ll. 1–30 (disclosing that “logic processor(s) and DRAM memory []
integrated onto a single chip” is what “solves the processor/memory
performance gap and bandwidth problems” of the prior art), col. 3, ll. 6–32
(disclosing that “integrating the processor and DRAM on the same chip”
reduces power dissipation and improves performance); Ex. 1003 ¶ 252
(citing Ex. 1005, col. 2, ll. 18–30, col. 4, ll. 4–18). Luk never indicates that
such benefits apply only when the DRAM and CMOS logic are implemented
on a “bulk” substrate. Dr. Giapis also acknowledges that Luk’s stated
benefits of DRAM-CMOS logic integration apply regardless of the type of
substrate used. Ex. 1028, 112:21–117:3.
Additional evidence in the record supports Dr. Bravman’s view that a
person of ordinary skill in the art would have understood DRAM-CMOS
logic integration to be beneficial regardless of whether the device is “bulk,”
SOI, or something else. Prince discloses improved performance as a benefit

870 F.3d 1376, 1380–81 (Fed. Cir. 2017) (permitting rebuttal argument from
a petitioner in response to a patent owner’s teaching away argument, as such
argument was “simply the by-product of one party necessarily getting the
last word”).
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of memory-processor integration, without mentioning the type of substrate
that must be used. Ex. 1013, 51. Other references describe benefits of
integration without regard to the type of substrate used, and disclose both
“bulk” and SOI devices. See Ex. 1031 ¶¶ 16–21 (citing Ex. 2035, col. 1,
ll. 14–17, 40–56; Ex. 2038, col. 1, l. 64–col. 2, l. 1; Ex. 2039, col. 1,
ll. 20–26, 38–40). Given this evidence, we agree with Dr. Bravman that
“embedded DRAM was [a] known product type prior to the filing of the
’320 patent, and was known to provide benefits over DRAM and CMOS
logic formed on separate chips, including increased communication
bandwidth between the DRAM and logic, improved overall performance,
reduced power consumption, and improved design flexibility,” and “one of
ordinary skill in the art would have understood that the benefits obtained
from putting DRAM and logic on the same chip—instead of separate
chips—would apply to devices that employ bulk silicon, SOI, or
combinations of both.” See id. ¶¶ 20–21.
Another relevant detail is that the known benefits of DRAM-CMOS
logic integration are tied directly to a goal of Hidaka itself—namely, to
increase the integration of DRAMs. See Pet. 54; Ex. 1003 ¶¶ 246–248;
Ex. 1004, col. 1, ll. 50–53 (“further increase of the degree of integration of
DRAMs has been desired”). We find that a person of ordinary skill in the
art would have understood Luk’s teachings regarding DRAM-CMOS logic
integration as helping to fulfill Hidaka’s stated desire, which further supports
Petitioner’s position that a person of ordinary skill in the art would have
been motivated to combine their teachings.
Patent Owner reads Luk’s single reference to SOI technology as
allegedly indicating that SOI designs were an “inadequate alternative” to the
integration problem. PO Resp. 20–21, 33 (emphasis omitted). Read in
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context, we do not agree. The full paragraph in the “Background
Description” of Luk reads:
The main reason of the [bandwidth bottleneck] problems
in systems with processor and dynamic random access memory
(DRAM) is due to the fact that processor chips and memory chips
are implemented in separate chips. There are other attempts to
solve the problems, namely by using multi-layer ceramic module
(MCM) technology or silicon on insulator (SOI) carrier
technology to house the individual silicon chips together. But
this still does not address the problem that the processors (logic)
and the memory (DRAM) are implemented in different chips
and, as a result, the limited bandwidth between the processor and
the memory and the large capacitive loads presented [i]n the
off-chip interconnections are still limiting the overall system
performance.
Ex. 1005, col. 1, ll. 25–37 (emphasis added). Luk describes SOI “carrier”
technology with a “hous[ing]” for two “individual silicon chips.” Id.
Dr. Bravman explains, with supporting evidence in the record, that “[t]he
term ‘carrier’ was generally known in the art to mean a ‘substrate structure
for supporting’ different ‘integrated circuit components’ that are ‘formed as
chips mountable on the carrier,’” where each chip has its own respective
substrate. Ex. 1031 ¶ 29 (quoting Ex. 1032, col. 3, ll. 42–50, col. 11,
ll. 20–25). Thus, Luk appropriately indicates that SOI “carrier” technology
would not solve the bandwidth bottleneck problem (just like other two-chip
implementations) because the memory and processor components would be
implemented on a housing with two “different chips” and “off-chip
interconnections” between them. Ex. 1005, col. 1, ll. 25–37. This merely
distinguishes multi-chip SOI carrier devices; it does not say anything about
the use of a single chip with a single SOI substrate for both components.
See Ex. 1031 ¶¶ 28–29.
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To be sure, Luk does not expressly disclose using SOI as a substrate
for both a DRAM and CMOS logic. See PO Resp. 20; Ex. 2027, 68:12–15.
But we see nothing in its disclosure indicating that doing so was disfavored
or would not solve the bandwidth bottleneck problem the reference is
designed to solve. Nor do we find anything in Luk suggesting that the stated
benefits arise because of a “bulk” substrate. Again, Luk and other
references in the record broadly disclose the benefits of DRAM-CMOS logic
integration without indicating that a particular type of substrate is necessary
to achieve those benefits. Thus, a person of ordinary skill in the art “would
have considered Luk to be directly applicable to all DRAM, including
Hidaka’s SOI DRAM.” See Reply 13.
Second, Patent Owner argues that Petitioner does not consider the
references as a whole and fails to explain “what type of semiconductor
device (SOI-CMOS, bulk-CMOS or some hybrid) a [person of ordinary skill
in the art] purportedly would have been led to make based on Hidaka and
Luk.” PO Resp. 27–32; Sur-Reply 7–12. According to Patent Owner, it was
Petitioner’s burden to describe the combined semiconductor device in the
Petition because obviousness requires a showing of how a person of ordinary
skill in the art would have combined prior art references. PO Resp. 28–31,
37. Patent Owner points out that Dr. Bravman acknowledged that he did not
“describe a particular device” with a particular type of substrate in his
analysis. Id. at 29–30; see Ex. 2027, 71:18–73:12. Patent Owner also
contends that describing the combined semiconductor device (including its
substrate) was “critical” because substrate type has a “significant and
probably pro[f]ound effect on the entirety of the processing regime.”
PO Resp. 31 (quoting Ex. 2027, 73:14–74:3) (emphasis omitted; alteration
in original).
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Petitioner, however, did describe how the prior art would have been
combined. Petitioner explained in the Petition that a person of ordinary skill
in the art would have been motivated to (1) “follow Luk’s teaching and
embed Hidaka’s DRAM along with CMOS logic on the same semiconductor
chip,” and (2) follow Takemura’s teaching and “replace Hidaka’s LOCOS
isolation with [a] STI.” Pet. 40–41, 54, 57–58. Hidaka discloses a
“semiconductor device” of a DRAM on a “SOI (Silicon on Insulator)
substrate,” with isolation between adjacent N-type sense amplifier transistors
and P-type sense amplifier transistors. Id. at 40, 48–50; see Ex. 1004, col. 1,
ll. 16–19, Fig. 18. Thus, Petitioner’s position is that a person of ordinary
skill in the art would start with Hidaka’s “semiconductor device”9 and
modify it in two respects: (1) to integrate it with CMOS logic on the same
semiconductor chip (based on Luk), and (2) to isolate the pairs of sense
amplifier transistors with STI regions (based on Takemura, which Patent
Owner does not dispute). Pet. 40–41, 54, 57–58. In other words, the
combined semiconductor device is simply a modified version of Hidaka’s
DRAM. See Paper 7, 17 (Patent Owner acknowledging that Petitioner is
asserting “obviousness over Hidaka modified based on Luk and Takemura”).
And Petitioner gives reasons why an ordinarily skilled artisan would have
been motivated to make the modifications. Pet. 54–58. This is sufficient to
explain “how” and “why” the prior art references are being combined.
See TriVascular, 812 F.3d at 1066; Kinetic Concepts, Inc. v. Smith &

9 As explained above, this is consistent with Petitioner’s overall obviousness
theory. Hidaka wants to “increase . . . the degree of integration” of DRAMs,
and modifying Hidaka’s DRAM based on Luk to implement it with CMOS
logic on the same chip would further that goal. See Ex. 1004, col. 1,
ll. 50–58.
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Nephew, Inc., 688 F.3d 1343, 1368 (Fed. Cir. 2012) (“[W]e must [] be
careful not to allow hindsight reconstruction of references to reach the
claimed invention without any explanation as to how or why the references
would be combined to produce the claimed invention.”).
To the extent Patent Owner places significant importance on the type
of substrate a person of ordinary skill in the art would have used for the
modified semiconductor device of Hidaka, we note that Hidaka’s device has
a SOI substrate. Thus, it is a SOI device that is being modified, and
Petitioner did not contend in the Petition that any non-SOI substrate would
be used when the device is modified based on the teachings of Luk. Further,
claim 1 is agnostic as to the type of substrate used. The claim recites a
“semiconductor device” with an “active region,” which dictates that a
substrate exists, but the claim never recites a “substrate,” specifies a
particular type of substrate, or recites any properties of the substrate.
See Sur-Reply 13; Ex. 1028, 34:9–36:20; Tr. 42:13–21 (Patent Owner
acknowledging that “the claims are not limited to a particular
semiconductor, or a particular kind of substrate”). Nor does the
Specification limit the device to a particular type of substrate. See Ex. 1028,
37:18–38:9. There is no dispute that different types of substrates (e.g.,
“bulk” substrate, SOI substrate) were known at the time of the ’320 patent.
See, e.g., PO Resp. 15 (arguing that “bulk silicon substrate” was
conventional at the time of the ’320 patent and SOI was known at the time as
“a less common alternative to bulk”), 43 (“SOI substrate on which the
Hidaka DRAM is formed”).

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Patent Owner argues in its Response that there are four “conceivable”
ways Petitioner might have alleged in the Petition that Hidaka and Luk could
be combined, providing the following illustrative figures (id. at 35–37).

The figures depict Patent Owner’s characterization of “options” 1–4 that
implement a DRAM and CMOS logic region on various substrates. Id.
Patent Owner addresses all four alleged options, asserting that Petitioner
fails to provide sufficient reasoning under any of the four possible
arrangements. Id. at 39–52.
As an initial matter, Patent Owner’s arguments regarding options 1, 3,
and 4 are immaterial. See id. at 39–45, 49–52. With respect to option 1, as
explained above, Petitioner’s position is that a person of ordinary skill in the
art would have had reason to modify Hidaka’s device (DRAM on SOI)
based on the teachings of Luk and “embed” it with CMOS logic “on the
same semiconductor chip.” Pet. 54. Petitioner never took the position that a
person of ordinary skill in the art would “start with Luk’s example [of]
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embedded DRAM devices on a bulk substrate and then” modify Luk’s
device. See Reply 8. Petitioner instead proposes modifying Hidaka’s
device. Pet. 54; Reply 7–8. Patent Owner also argues that a person of
ordinary skill in the art “would not have used Hidaka’s SOI-specific DRAM
on bulk” for various reasons, including that “Hidaka disparages DRAM
‘formed on a silicon substrate,’ because it can have data errors from
‘α-particles,’” which “teaches away from modifying Hidaka by
implementing its DRAM on bulk.” PO Resp. 26–27. Petitioner, however,
never argued that a person of ordinary skill in the art would have modified
Hidaka’s device to be on a bulk substrate. See Pet. 40–42, 54–58; Reply 8.
With respect to options 3 and 4, which are hybrid devices with one of
the DRAM and CMOS logic being on a SOI region and one on a bulk
region, Petitioner argues in a footnote in its Reply that Patent Owner’s
evidence shows that such devices were known in the art. Reply 15 n.1.
Petitioner, however, never argued in the Petition, and Dr. Bravman offers no
testimony that would support such an argument, that an ordinarily skilled
artisan would have combined Hidaka and Luk in such a hybrid manner.
See Tr. 20:1–21 (Petitioner arguing that the Petition “demonstrated” option 2
and acknowledging that the Petition did not discuss the “mixed substrates”
of options 3 and 4); Sur-Reply 15–16.
Again, the specific modification proposed by Petitioner is to modify
Hidaka’s device (DRAM on SOI) based on the teachings of Luk and
“embed” it with CMOS logic “on the same semiconductor chip.” Pet. 54;
Reply 7–8. That modification appears to be (in simplified form) what
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Patent Owner characterizes as option 2.10 For the reasons explained above,
we determine that Petitioner has made a sufficient showing with respect to
the combined semiconductor device.
Patent Owner further argues, with respect to option 2, that Petitioner
“fail[s] to address significant challenges that would have discouraged a
[person of ordinary skill in the art] from pursuing such a device.” PO Resp.
46–49 (citing Ex. 2025 ¶¶ 113–123); Sur-Reply 18–21. According to Patent
Owner, “SOI technology was still experimental in the relevant timeframe
[of August 2002] and was known to present issues that impeded its adoption;
indeed, even in 2005, major chip manufacturers such as Intel and TSMC had
either delayed their release of SOI devices or abandoned them altogether.”
PO Resp. 46–47 (citing Ex. 2041). Patent Owner contends that “there were
specific problems with integrating DRAM with SOI-based CMOS logic,”
including the creation of “high leakage current” and “floating body effects,”

10 Patent Owner contends that any reliance on option 2 in the Reply is an
improper new argument. Sur-Reply 16. We disagree. Although
Dr. Bravman did not describe a particular device with a particular type of
substrate in his initial declaration, Petitioner expressly argued in the Petition
that a person of ordinary skill in the art would have been motivated to
“follow Luk’s teaching and embed Hidaka’s DRAM along with CMOS logic
on the same semiconductor chip.” See Pet. 54. We disagree with Patent
Owner’s argument at the hearing that the proposed combination is
“ambiguous”—the Petition clearly was premised on modifying Hidaka’s
device based on the teachings of Luk (and based on the teachings of
Takemura, which Patent Owner does not dispute and does not characterize
as ambiguous). See Tr. 34:24–35:18, 38:6–39:9; Apple Inc. v. Andrea Elecs.
Corp., 949 F.3d 697, 706–707 (Fed. Cir. 2020) (concluding that the
petitioner’s reply arguments did not change the asserted “legal ground” and
were not “the types of arguments that [the court had] previously found to
raise a ‘new theory of unpatentability’”); Chamberlain Group, Inc. v. One
World Techs., Inc., 944 F.3d 919, 924–925 (Fed. Cir. 2019) (“Parties are not
barred from elaborating on their arguments on issues previously raised.”).
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that made DRAM and CMOS “incompatible” for a SOI device. Id. at 47–48
(citing Exs. 2023, 2033, 2034) (emphasis omitted). Patent Owner argues
that IBM was not able to achieve “successful integration of DRAM and
CMOS on SOI” until much later in 2007–2008, and even then, the solution
IBM adopted was “DRAM on bulk and CMOS logic on SOI” (not both
components on SOI), which was “consistent with the state of the art.” Id.
(citing Exs. 2023, 2028, 2035–2037).
Petitioner responds that the documents cited by Patent Owner actually
demonstrate the opposite—namely, that “not only was it known that
embedded DRAM could be formed on SOI, but that doing so was desirable,”
and Hidaka solves the problems identified by Patent Owner. Reply 16–18.
After reviewing the evidence of record, we agree with Petitioner. By
the time of the ’320 patent (August 2002), SOI devices were well-known,
known to have various advantages over devices with a bulk substrate, and
increasingly being used. See, e.g., id. at 12–13; Ex. 1028, 44:5–9, 59:2–11;
Ex. 2025 ¶ 75; Ex. 2029, col. 1, l. 41–col. 2, l. 37 (SOI devices “consume
less power than do bulk CMOS devices,” “operate at higher speeds,” and
“offer[] a number of [other] advantages relative to traditional transistor
formation in a bulk silicon wafer”); Ex. 2031 ¶¶ 5–6 (SOI devices have
“demonstrated significant progress recently” and provide “several
advantages . . . over the general [integrated circuit (IC)] devices made on
bulk substrate”); Ex. 2033, col. 2, ll. 52–54 (“To increase logic performance,
it is desirable to fabricate CMOS devices in the logic portion in SOI
regions.”); Ex. 2039, col. 1, ll. 27–33 (“SOI devices, such as a
SOIMOSFET, using an SOI substrate in place of a conventional silicon bulk
substrate ha[ve] been attracting a great deal of attention. . . . Such SOI
devices have already been mass-produced for use in high-performance logic
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circuits.”); Ex. 2043, col. 1, ll. 16–26 (“Silicon-on-insulator (SOI)
technology is becoming of increasing importance in the field of integrated
circuits. . . . High performance and high density integrated circuits are
achievable using SOI technology because of the reduction of parasitic
elements present in integrated circuits formed in bulk semiconductor.”).
Implementing DRAM on SOI, as in Hidaka, also was well-known. See, e.g.,
Pet. 24–25, 40; Reply 18; Ex. 1004, col. 1, ll. 16–19; Ex. 2032, col. 1,
ll. 10–25 (“SOI is good for DRAM for several reasons.”); Ex. 2045, 1, 7
(“SOI CMOS technology has been used to realize . . . DRAM, SRAM, and
other system circuits”), 92–94. Thus, we do not agree with Patent Owner’s
characterization of SOI technology as still “experimental” in August 2002.
See PO Resp. 46–47.
Significantly, embedded DRAM on SOI also was known to persons of
ordinary skill in the art and seen as desirable. See, e.g., Reply 13–14, 16–17
(quoting nine prior art references submitted by Patent Owner (Exhibits 2023,
2028, 2033, 2035–2039, and 2045) that “discuss various embedded DRAMs
that employ SOI”); Ex. 1031 ¶¶ 24–27; Ex. 1026 (“Shiho”), col. 2, ll. 40–47
(describing embedded DRAM integrated circuits with a substrate that may
be many different types, including a “silicon on insulator (SOI) substrate[]”),
Fig. 1; Ex. 1027 (“Yamamoto”) ¶¶ 9, 105; Ex. 2039, col. 1, ll. 34–40
(“development of a system [large scale integration (LSI)] or a
system-on-chip which carries a memory (e.g., a DRAM) together with an
SOI logic on a single chip has become an urgent necessity”). Patent Owner
responds that Shiho discloses SOI as a substrate merely in a “catch-all
phras[e]” of the type that “patent applicants use to support broad claims.”
Sur-Reply 20–21. Although Shiho does not describe a particular embedded
DRAM device with a SOI substrate, we do not discount it completely. It is
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at least some support showing that a person of ordinary skill in the art would
have recognized that a wide variety of substrates, such as SOI, could be used
when making an embedded DRAM device, and that modifying a
DRAM-on-SOI device like Hidaka to have integrated CMOS logic would
not have been as problematic as Patent Owner contends.11
With respect to IBM’s development of an embedded DRAM device,
an EE Times article published in 2000 states the following:
IBM Corp. has found a way to embed DRAM in a
silicon-on-insulator (SOI) logic process, filling a menacing
pothole in its system-on-a-chip road map.
Both technologies are considered vital to creating the
complex semiconductors at the heart of future electronic
devices—one being an element crucial to integrated system
designs, and the other a processing technique that allows
high-speed circuits to maintain electrical integrity, even when
packed into ever-smaller spaces.
Until now, the two were considered hopelessly
incompatible.
Ex. 2023, 1; see Ex. 2054 ¶ 5. The article further states that “SOI has
become the primary processing technology for IBM’s high-end products,
mainly microprocessors and SRAM,” and “[e]mbedded DRAM is also
gaining acceptance,” but there was “a question of whether [IBM] could ever
embed DRAM in SOI.” Ex. 2023, 1. The article describes IBM’s technique
as “patterned SOI” where wafers are fabricated with “areas of both bulk
CMOS and SOI.” Id. at 2. “When DRAM cells were isolated in the bulk

11 Shiho also is consistent with Luk’s disclosure of the benefits of
embedding a DRAM with CMOS logic. See Pet. 54–55; Ex. 1026, col. 1,
ll. 16–22 (“Embedded DRAM is likely to provide microcontroller (MCU)
and other embedded controllers faster access to larger capacities of on-chip
memory at a lower cost than that currently available . . . .”); Ex. 1031 ¶ 27.
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regions, memory and logic were able to coexist in a chip design without
sacrificing the performance of either.” Id.
Patent Owner relies on the statement that DRAM and CMOS logic
were considered “hopelessly incompatible” for implementing on SOI.
PO Resp. 47. The article, however, states that IBM “ha[d] found a way” to
create embedded DRAM on SOI; thus, the previous view in the art was
no longer the case at least as of 2000 (two years before the ’320 patent).
See Ex. 2023, 1. The other references cited above, such as Shiho (filed in
1999), further support that view. See Ex. 1026, code (22), col. 2, ll. 40–47.
Patent Owner also points to the fact that IBM adopted a hybrid design
with DRAM on bulk and CMOS logic on SOI (option 4 above), rather than a
design with both components on SOI (option 2 above). PO Resp. 47–48;
Sur-Reply 21. Given the other evidence before us, however, we are not
persuaded that the fact that IBM encountered issues with implementing
DRAM on SOI means that others did as well or that a person of ordinary
skill in the art would not have considered integrating a DRAM with CMOS
logic on SOI. Indeed, Hidaka provided a solution for implementing DRAM
on SOI, and expressly states that its implementation was designed to solve
various problems in the art, such as reducing leakage current, suppressing
noise interference, and achieving a “minimum layout area.” Ex. 1004,
col. 1, ll. 16–19, col. 2, ll. 47–54, col. 3, ll. 18–34; see Reply 19. And
references like Shiho suggest that embedded DRAM on SOI was
contemplated in the art at the time. See Ex. 1026, col. 2, ll. 40–47.
In sum, the evidence of record indicates that development of
embedded DRAM devices using a SOI substrate (as in Petitioner’s proposed
combination of Hidaka and Luk) was contemplated and ongoing by August
2002. Although some in the industry encountered some issues with creating
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such devices, viewing the evidence as a whole, we are not persuaded that
those issues would have dissuaded a person of ordinary skill in the art from
making the asserted combination of Hidaka and Luk.
We also note that, to the extent Patent Owner disputes Petitioner’s
asserted combination based on the complexity of substrate “selection,”
Sur-Reply 14, 17, the asserted combination starts with Hidaka’s DRAM
device that has an existing substrate (SOI) and makes the modification of
embedding the DRAM with CMOS logic on the same chip; no other
substrate is being “select[ed].”
Third, Patent Owner argues that Petitioner’s asserted motivation to
combine Hidaka and Luk is unsupported, pointing to various statements
made by Dr. Bravman during cross-examination where he “effectively
admitted the only ‘reason’ he combined various features from Luk and
Hidaka was that he needed to do so to reconstruct the Challenged Claims.”
PO Resp. 32–34 (citing Ex. 2027, 80:15–81:21, 85:6–86:10, 86:12–87:3,
88:14–89:8, 91:1–14); Sur-Reply 22. We have reviewed the cited
statements in context and do not read them in that manner. Dr. Bravman
was asked whether he provided in his declaration any “specific reasons why
a [person of ordinary skill in the art] would pick Hidaka’s DRAM to
combine with CMOS logic on a single chip” or any “motivations that are
specific to any unique attribute of Hidaka.” Ex. 2027, 80:15–81:21, 85:6–9,
85:19–86:10, 87:12–88:8, 90:4–6, 90:18–91:14. In response, he explained
that he “chose[]” Hidaka as the base reference because it “shows quite
clearly the design features” (e.g., of the sense amplifier transistors recited in
claim 1) and the fact that they “were largely known in the art already,” and
referred to the motivation to combine analysis in his declaration where he
explains his alleged motivation to start with Hidaka’s DRAM device and
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modify it based on Luk. Id. We see nothing improper with that analysis.
See Reply 3–4, 20–22. As explained above, Dr. Bravman’s declaration
explains in detail the basis for his opinions regarding the combination of
Hidaka and Luk, and is supported by the disclosures of the references
themselves and other evidence of record.
Patent Owner also contends that Petitioner’s motivation to combine
analysis is deficient because it includes a statement that “DRAM—like that
taught by Hidaka—could be integrated or embedded along with a separate
logic circuitry onto a semiconductor chip,” and obviousness requires a
showing that a person of ordinary skill in the art would have made the
combination. PO Resp. 34–35 (quoting Pet. 41). We agree as to the latter
point. The analysis for why the combination would have been made appears
later in the Petition, and we find it sufficient for the reasons explained above.
See Pet. 53–56.
Fourth, Patent Owner argues that there is no support for the assertion
in the Petition that “a [person of ordinary skill in the art] would have
recognized that Luk’s system is specifically designed to take existing
memory components—like those disclosed by Hidaka—and tailor them for
use in an embedded chip,” and Dr. Bravman’s testimony to that effect is
conclusory. PO Resp. 52–53 (quoting Pet. 58; citing Ex. 1003 ¶¶ 285–287).
Patent Owner contends that “Petitioner points to no feature of Hidaka’s
DRAM a [person of ordinary skill in the art] allegedly would have ‘tailored’
or modified based on teachings of Luk.” Id. at 53–54.
As explained in the Decision on Institution, we agree that Petitioner
and Dr. Bravman do not describe a particular modification to Hidaka’s
DRAM itself. Dec. on Inst. 40. Rather, the asserted modification to Hidaka
is to take Hidaka’s existing DRAM and “embed [it] along with CMOS logic
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on the same semiconductor chip.” Pet. 54. We do not see why it was
necessary for Petitioner to propose specific modifications to Hidaka’s
DRAM itself, beyond the straightforward modification described in the
Petition. See id.; Rovalma, S.A. v. Bohler-Edelstahl GmbH & Co. KG,
856 F.3d 1019, 1025 (Fed. Cir. 2017) (“the amount of explanation needed
varies from case to case, depending on the complexity of the matter and the
issues raised in the record”).
Further, although the cited portions of Dr. Bravman’s declaration do
not cite supporting evidence (and thus are entitled to less weight than other
testimony that is directly supported), they are consistent with the overall
disclosure of Luk and Dr. Bravman’s earlier testimony. Dr. Bravman
testifies that “Luk provides one of ordinary skill in the art with an example
method that can be used to embed an existing DRAM design (like that
taught by Hidaka) onto the same chip as CMOS logic,” such that one of
ordinary skill in the art could take the existing memory components of
Hidaka’s DRAM and “determine how to best pattern them onto the same
chip as CMOS logic.” Ex. 1003 ¶¶ 285–286. Luk describes in detail a
“DRAM compiler/configurator” for creating “the physical structure, circuit,
and layout” of an embedded DRAM design with different parameters, such
as memory capacity, modes of operation, etc. Ex. 1005, col. 1, ll. 41–62,
col. 5, l. 56–col. 6, l. 59, Fig. 9; see Pet. 35–36; Ex. 1003 ¶¶ 161–162. Luk
also provides flexibility in implementing different kinds of integrated
DRAM/logic chips, stating that it is an object of the invention to use the
DRAM compiler/configurator “for a wide range of integrated logic/DRAM
applications.” See Ex. 1005, col. 1, ll. 52–62. Luk’s disclosure, as well as
the other evidence of record describing DRAM-CMOS logic integration
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discussed herein, indicates that it would have been within the skill of an
ordinarily skilled artisan to modify Hidaka’s device as Petitioner contends.
Fifth, Patent Owner argues that Petitioner has not proven that a person
of ordinary skill in the art would have had a reasonable expectation of
success in modifying Hidaka’s device, based on the teachings of Luk, to
achieve a semiconductor device with a DRAM region and co-resident
high-speed CMOS logic region, as recited in claim 1. PO Resp. 55–58.
In particular, Patent Owner argues that Petitioner’s contention and
Dr. Bravman’s testimony that embedding Hidaka’s DRAM on the same chip
as CMOS logic would have been a “routine and straightforward design
choice” are conclusory. Id. at 55 (quoting Pet. 55–56; citing Ex. 1003
¶¶ 245–293). Further, according to Patent Owner, “Dr. Bravman’s assertion
that embedding Hidaka’s DRAM onto a chip with logic would have been
‘routine’ is belied by his own repeated acknowledgement of the complexities
involved in designing an integrated DRAM/logic chip.” Id. at 56 (citing
Ex. 2025 ¶¶ 143–145; Ex. 2027, 63:8–64:2, 64:4–65:5, 73:14–74:3).
We find that Petitioner has made a sufficient showing that a person of
ordinary skill in the art would have had a reasonable expectation of success
in combining the references’ teachings and achieving the semiconductor
device of claim 1. “[E]xpectation of success need only be reasonable, not
absolute.” Pfizer, Inc. v. Apotex, Inc., 480 F.3d 1348, 1364 (Fed. Cir. 2007).
Petitioner explains, with supporting testimony from Dr. Bravman and
supporting evidence in the record, how SOI-based DRAM (e.g., Hidaka),
SOI-based CMOS logic, and embedded DRAM on a SOI substrate (e.g.,
Shiho, Yamamoto) were known to persons of ordinary skill in the art at the
time of the ’320 patent. See Pet. 40, 54–58; Reply 13, 16–18, 20; Ex. 1003
¶¶ 179, 257–262; Ex. 1031 ¶¶ 24–27. And, of course, the ’320 patent
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acknowledges that embedded DRAMs with a co-resident DRAM and logic
circuitry had been “put into practical use,” and that there were a number of
known techniques and fabrication processes to create “a commodity DRAM
[that is] co-resident with a high-speed logic.” Ex. 1001, col. 1, ll. 16–27.
After reviewing the full trial record, we find that an ordinarily skilled artisan
would have had a reasonable expectation of success in making the proposed
modification to Hidaka based on Luk.
For the reasons explained above, we find that the combination of
Hidaka and Luk teaches the co-resident limitation of claim 1 and that
Petitioner has provided sufficient reasoning for why a person of ordinary
skill in the art would have been motivated to modify Hidaka’s device based
on the teachings of Luk and would have had a reasonable expectation of
success in doing so.

c) Conclusion
For the reasons set forth by Petitioner and explained above, we are
persuaded that Hidaka, Luk, and Takemura collectively teach all of the
limitations of claim 1. We also are persuaded that a person of ordinary skill
in the art would have been motivated to modify Hidaka’s device (based on
the teachings of Luk) to have its DRAM be “co-resident” with a high-speed
CMOS logic region and to further modify the device (based on the teachings
of Takemura) to use STI rather than LOCOS isolation, achieving the
semiconductor device recited in the claim, and would have had a reasonable
expectation of success in doing so. Petitioner has proven, by a
preponderance of the evidence, that claim 1 would have been obvious based
on Hidaka, Luk, and Takemura under 35 U.S.C. § 103(a).

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E. Obviousness Ground Based on Hidaka and Luk (Claims 4–6)
1. Claim 4
Independent claims 1 and 4 are identical except for the type of
isolation they require. Claim 1 recites that the pair of adjacent N-type sense
amplifier transistors and pair of adjacent P-type sense amplifier transistors
are isolated by “shallow trench isolation (STI) regions.” Petitioner relies on
Takemura for a teaching of STI regions. Pet. 47–53; see supra Section
II.D.4.a.
Claim 4, by contrast, recites isolation using “field shield electrodes.”
Specifically, claim 4 recites (“the field shield electrodes limitation”) that
active regions are connected to each other in a pair of adjacent
N-type sense amplifier transistors and a pair of adjacent P-type
sense amplifier transistors, and on the active regions, field shield
electrodes are disposed between the pair of adjacent N-type sense
amplifier transistors and between the pair of adjacent P-type
sense amplifier transistors so as to be parallel to the pair of gate
electrodes of each of the sense amplifier transistors.
Petitioner argues that Hidaka teaches the recited isolation, pointing to the
annotated version of Figure 18 reproduced in Section II.D.4.a above.
Pet. 60. According to Petitioner, the annotated figure depicts an isolation
(shown in orange) “between” adjacent N-type sense amplifier transistors
(shown in red) and “parallel” to the gate electrodes of the sense amplifier
transistors (shown in green), and the P-type sense amplifiers have the same
structure. Id. (citing Ex. 1004, col. 9, ll. 41–43). Petitioner further cites
Hidaka’s teaching of adjacent transistors being isolated using “field shield
isolation” via a field shield electrode. Id. at 61. Petitioner asserts that a
person of ordinary skill in the art would have understood that Hidaka’s field
shield electrode could be used to isolate Hidaka’s sense amplifier transistors,
just like LOCOS isolation, and, in that case, the active regions would remain
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physically “connected” to each other but isolated by the electric field created
by the field shield electrode. Id. at 61–63.
Petitioner argues, citing Dr. Bravman’s testimony and supporting
documentation in the record, that an ordinarily skilled artisan would have
been motivated to do so because field shield electrodes have a number of
benefits over LOCOS isolation (e.g., avoiding stress concentration, high
reliability, more compact size), and would have had a reasonable expectation
of success in doing so because Hidaka already teaches “field shield
isolation” as an acceptable method of transistor isolation. Id. at 61, 67–68
(citing Ex. 1003 ¶¶ 334–345; Ex. 1016, col. 1, ll. 15–39; Ex. 1017, col. 1,
ll. 59–67); see Ex. 1004, col. 11, ll. 19–25.
With respect to the co-resident limitation recited in both claim 1 and
claim 4, Petitioner argues that the limitation “is disclosed by Hidaka and Luk
for the same reasons explained in Section I.C.1.a” of the Petition and a
person of ordinary skill in the art “would have been motivated and
considered it obvious to apply the teachings of Luk to Hidaka, and would
have reasonably expected this combination to succeed, for the same reasons
discussed in Section I.C.2” of the Petition. Pet. 59, 67. Patent Owner
responds that neither section exists, which is “fatal” to the Petition in Patent
Owner’s view, but even if not, Petitioner’s arguments regarding claim 4 fail
for the same reasons argued with respect to claim 1. PO Resp. 6, 58–59. As
explained in the Decision on Institution, given that the co-resident limitation
is recited identically in both claim 1 and claim 4, and Petitioner relies on the
combination of Hidaka and Luk for the limitation, we understand the cited
references to be typographical errors that were meant to refer to Sections
VII.C.1.a and VII.C.2 of the Petition. See Dec. on Inst. 44 n.8. We also
disagree with Patent Owner’s arguments regarding the combination of
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Hidaka and Luk for the reasons explained above. See supra Section
II.D.4.b.(2).
We have reviewed Petitioner’s contentions and supporting evidence,
including the testimony of Dr. Bravman, and are persuaded that Petitioner
has proven, by a preponderance of the evidence, that claim 4 would have
been obvious based on Hidaka and Luk under 35 U.S.C. § 103(a), for the
reasons stated by Petitioner. See Pet. 58–63, 67–68; Ex. 1003 ¶¶ 294–315,
334–345.

2. Claims 5 and 6
Claim 5 depends from claim 4 and recites that “the pair of gate
electrodes and the field shield electrodes are disposed at a substantially equal
interval.” Petitioner argues that “in every one of Hidaka’s figures,”
including Figure 18, “the isolation region is centered between the gates of
two adjacent sense amplifier transistors.” Pet. 63–64. Petitioner further
contends that Hidaka’s “field shield electrode is positioned and located such
that [it] is in the middle of the space between two active areas,” and a person
of ordinary skill in the art would have understood that the symmetrical
spacing was “purposeful” because “[p]ositioning the field shield electrode at
equal distances to adjacent signal bearing components—like transistor gate
electrodes—ensures that the components are fully isolated and do not
experience varying degrees of noise and interference.” Id. at 64–65.
Claim 6 depends from claim 4 and recites that “a ground potential or a
negative voltage used for a substrate potential of a DRAM cell is applied to
the field shield electrodes on the N-type active regions.” Petitioner argues
that the limitation would have been obvious based on Hidaka, as Hidaka
teaches isolation of adjacent transistors using field shield electrodes and a
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person of ordinary skill in the art would have understood that Hidaka’s
device operates in the manner recited in claim 6. Id. at 66. As support,
Petitioner notes that Hidaka is related to another application, U.S. Patent
Application No. 08/353,276, and a continuation of that application describes
operation of a field shield electrode where a “[g]round potential Vss or a
negative potential” is applied to isolate adjacent elements. Id. (quoting
Ex. 1019, col. 32, ll. 16–20; citing Ex. 1004, col. 1, ll. 9–12).
Patent Owner does not argue separately dependent claims 5 and 6.
See PO Resp. 21–59; Sur-Reply 1–22. We disagree with Patent Owner’s
arguments regarding parent claim 4 for the reasons explained above.
See supra Section II.E.1. We have reviewed Petitioner’s contentions and
supporting evidence, including the testimony of Dr. Bravman, and are
persuaded that Petitioner has proven, by a preponderance of the evidence,
that claims 5 and 6 would have been obvious based on Hidaka and Luk
under 35 U.S.C. § 103(a), for the reasons stated by Petitioner. See
Pet. 63–68; Ex. 1003 ¶¶ 316–345.

F. Obviousness Grounds Based on Aoyama, Luk, and Takemura (Claim 1),
and Aoyama, Luk, and Hidaka (Claims 4–6)
1. Aoyama
Aoyama discloses “[a] semiconductor memory device, whose pairs of
bit lines are connected to a pair of data buses, . . . divided into a plurality of
blocks each comprising a plurality of parted memory cells, a pair of
switching elements, and a block sense amplifier.” Ex. 1007, code (57).
Aoyama describes a static RAM, but states that its disclosed “invention can
be also applied to [a] dynamic RAM.” Id. at col. 7, ll. 52–54. The block
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sense amplifier in Aoyama’s memory device includes P-channel MOS
transistors and N-channel MOS transistors. Id. at col. 6, ll. 14–23, Fig. 6.
Figure 7(a) of Aoyama is reproduced below.

Figure 7(a) depicts “a plan view of the pattern of a block sense amplifier . . .
in a block located farthest from the data bus of the semiconductor memory
device.” Id. at col. 4, ll. 28–31. The block sense amplifier includes
P-channel MOS transistors Q1 and Q2, N-channel MOS transistors Q3, Q4,
and Q5, P-type and N-type active areas, sense amplifier gate electrodes, and
bit lines BLi0, /BLi0, BLi1, and /BLi1. Id. at col. 6, ll. 14–61.

2. Analysis
Petitioner argues that claim 1 is unpatentable over Aoyama, Luk, and
Takemura, and claims 4–6 are unpatentable over Aoyama, Luk, and Hidaka,
under 35 U.S.C. § 103(a), relying on the testimony of Dr. Bravman as
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support. Pet. 68–82 (citing Ex. 1003). Petitioner’s analysis of the
Aoyama-based asserted grounds is similar to its analysis for the
Hidaka-based grounds. Compare Pet. 39–68, with id. at 68–82. Petitioner
relies on Aoyama for the majority of the claim limitations, including a
“DRAM region” having “a pair of gate electrodes of a N-type sense
amplifier transistor and a pair of gate electrodes of a P-type sense amplifier
transistor constituting a CMOS sense amplifier” where the pairs of gate
electrodes of the sense amplifier transistors “are disposed respectively in one
active region in parallel to each other in the same direction as that of bit
lines.” Id. at 69–72, 78–79. Petitioner relies on combinations of Aoyama
(1) with Luk for the co-resident limitation of claims 1 and 4, (2) with
Takemura for the shallow trench isolation limitation of claim 1, and (3) with
Hidaka for the field shield electrodes limitation of claim 4. Id. at 68–69,
73–79.
With respect to the co-resident limitation of independent claims 1 and
4, Petitioner makes two arguments. First, Petitioner relies on Aoyama alone,
arguing that a person of ordinary skill in the art “would have understood that
Aoyama’s memory, like all semiconductor memory, includes standard
peripherical logic.” Id. at 69 (citing Ex. 1003 ¶¶ 348–351; Brent Keeth &
R. Jacob Baker, DRAM Circuit Design: A Tutorial 33 (2001) (Ex. 1012,
“Keeth”)). As explained in the Decision on Institution, it is unclear what
Petitioner means by “standard peripherical logic,” as Petitioner and
Dr. Bravman do not explain the phrase or identify any particular
component(s) in Aoyama or the cited page of Keeth. See id.; Dec. on Inst.
47–48. Nor do Petitioner and Dr. Bravman explain in any detail why the
alleged “standard peripherical logic” constitutes a “high-speed CMOS logic
region” that is co-resident with a “DRAM region.” Indeed, Petitioner
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acknowledges that “Aoyama does not specifically state that its DRAM is
included on the same chip as separate, non-memory CMOS logic, such as a
processor.” Pet. 69. We are not persuaded that Aoyama alone teaches the
co-resident limitation.
Second, Petitioner again relies on a combination with Luk, stating that
“[w]hile Aoyama does not explicitly explain that its DRAM can be
‘co-resident’ on the same chip as separate, non-DRAM logic, Luk teaches
this and explains that integrating DRAM and separate logic provides many
benefits,” referencing Sections I.C.1.a and I.C.2 of its Petition. Pet. 68–69,
75 (arguing that a person of ordinary skill in the art would have been
motivated to combine Aoyama and Luk “for the same reasons discussed in
Section I.C.2” of the Petition), 77–78. Again, we assume that these
references are typographical errors and meant to refer to the portions of the
Petition involving the combination of Hidaka and Luk (Sections VII.C.1.a
and VII.C.2). See Dec. on Inst. 48; Reply 22.
We are not persuaded that Petitioner has made a sufficient showing
that a person of ordinary skill in the art would have had reason to combine
Aoyama and Luk. Petitioner provides no explanation in the Petition
regarding the combination of Aoyama and Luk, beyond referring to the
arguments regarding the combination of Hidaka and Luk. See Pet. 68–69,
75, 77–78.12 Importantly, as Patent Owner correctly points out, the latter

12 To the extent Petitioner attempts to rely on paragraphs from
Dr. Bravman’s declaration, we note that none of that analysis is explained in
the Petition; the Petition solely refers to the earlier arguments regarding
Hidaka and Luk. See Pet. 75; Reply 22; Ex. 1003 ¶¶ 374–389; 37 C.F.R.
§ 42.6(a)(3) (“Arguments must not be incorporated by reference from one
document into another document.”); Cisco Sys., Inc. v. C-Cation Techs.,
LLC, IPR2014-00454, Paper 12 at 10 (PTAB Aug. 29, 2014) (informative).
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arguments are specific to Hidaka’s device and premised on particular
teachings of Hidaka. See PO Resp. 63–64 (citing Pet. 54, 55, 57, 58).
For example, in support of its argument that it would have been “obvious to
follow Luk’s teaching and embed Hidaka’s DRAM along with CMOS logic
on the same semiconductor chip,” Petitioner points out that Hidaka “already
recognizes that it is desirable to ‘increase [] the degree of integration’ of
DRAM.” Pet. 54 (quoting Ex. 1004, col. 1, ll. 50–58; alteration in original).
We find that disclosure in Hidaka compelling. See supra Section
II.D.4.b.(2). Aoyama discloses an entirely different device. See supra
Section II.F.1. Absent any explanation from Petitioner, we are not
persuaded that Petitioner’s arguments regarding the combination of
Hidaka’s DRAM teachings with Luk’s teachings regarding integration with
CMOS logic on a single chip automatically would apply in the same way to
combining Aoyama’s DRAM teachings with Luk.
A similar situation occurred in Magnum Oil, 829 F.3d at 1379–80. In
that case, the petitioner asserted obviousness grounds based on two different
combinations of references: (1) Alpha, Cockrell, and Kristiansen, and
(2) Lehr, Cockrell, and Kristiansen. Id. at 1372. For the second ground, the
petitioner merely incorporated its previous arguments regarding Alpha and
stated that “[t]he same analysis applies to combinations using Lehr as a base
reference,” “without presenting particularized arguments explaining why
those arguments from Alpha would be cross-applicable to the Lehr
reference,” which described a different device. Id. at 1372, 1379–80
(emphasis added). The court reversed the Board’s decision that the claims
were unpatentable based on the Lehr ground, finding that the petitioner
“failed to articulate a motivation to combine the specific teachings of Lehr,
Cockrell, and Kristiansen to achieve the claimed invention.” Id. at 1379.
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The petitioner provided only “conclusory statements” as to the Lehr ground,
rather than “specific reasoning, based on evidence of record, to support the
legal conclusion of obviousness.” Id. at 1380. Petitioner here makes a
similar conclusory assertion that the same analysis for the asserted ground
based on the combination of Hidaka and Luk applies to the asserted ground
based on the combination of Aoyama and Luk, without providing the
particularized analysis required to support a conclusion of obviousness as to
that combination.
Petitioner argues that a petition “can make an argument via internal
cross-reference so long as the cross-referenced section supports the
argument in question.” Reply 23. We agree that such cross-referencing is
permissible. See CRFD Research, Inc. v. Matal, 876 F.3d 1330, 1345–46
(Fed. Cir. 2017) (agreeing with the petitioner that it “incorporated [an]
argument into other grounds of unpatentability . . . by direct citation to [the]
argument in the petition”). The problem for Petitioner is that the
cross-referenced portions of the Petition do not support Petitioner’s
arguments, as they are premised on Hidaka’s teachings and pertain to a
specific modification to Hidaka’s device based on the teachings of Luk.
Petitioner does not explain sufficiently, for example, why Aoyama’s device
is similar to Hidaka’s or why Aoyama’s teachings are similar to the relevant
teachings of Hidaka (e.g., those regarding the desirability of DRAM
integration).
Petitioner further contends that “there is no requirement under the law
that the motivation to include logic with Hidaka’s DRAM be any different
than the motivation to include logic with Aoyama’s DRAM” because “[t]he
same motivation can apply to multiple references.” Reply 23 (citing
Celgene Corp. v. Peter, 931 F.3d 1342, 1354–55 (Fed. Cir. 2019)). We do
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not read Celgene as supporting Petitioner’s contention that a single
cross-reference to an earlier asserted ground is sufficient to establish a
reason to combine for a different combination. To the contrary, the court
noted that the alleged motivation to combine in Celgene constituted
“a specific motivation to improve the prior art.” Celgene, 931 F.3d at 1354.
Petitioner has not provided such a specific motivation with respect to
Aoyama and Luk. Moreover, even if Petitioner is correct that the same
rationale for Hidaka and Luk can apply to Aoyama and Luk, it was
Petitioner’s burden to explain why the same analysis would apply to a
different device like that of Aoyama. Petitioner failed to do so.
Finally, Petitioner argues that the same “benefits” of embedding
DRAM would “apply to all DRAM designs,” including Aoyama’s DRAM.
Reply 23–24. We do not see where that argument was made in the Petition,
however. Indeed, the only portions of the Petition that Petitioner cites for
the argument discuss Luk generically and the combination of Hidaka and
Luk. See id. (citing Pet. 34, 54–56).
Petitioner has not proven, by a preponderance of the evidence, that
claim 1 would have been obvious based on Aoyama, Luk, and Takemura, or
that claims 4–6 would have been obvious based on Aoyama, Luk, and
Hidaka, under 35 U.S.C. § 103(a).

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III. CONCLUSION13
Petitioner has demonstrated, by a preponderance of the evidence, that
claims 1 and 4–6 of the ’320 patent are unpatentable. In summary:
IV. ORDER
In consideration of the foregoing, it is hereby:
ORDERED that claims 1 and 4–6 of the ’320 patent have been shown
to be unpatentable.

13 Should Patent Owner wish to pursue amendment of the challenged claims
in a reissue or reexamination proceeding subsequent to the issuance of this
Decision, we draw Patent Owner’s attention to the April 2019 Notice
Regarding Options for Amendments by Patent Owner Through Reissue or
Reexamination During a Pending AIA Trial Proceeding. See 84 Fed. Reg.
16,654 (Apr. 22, 2019). If Patent Owner chooses to file a reissue application
or a request for reexamination of the challenged patent, we remind Patent
Owner of its continuing obligation to notify the Board of any such related
matters in updated mandatory notices. See 37 C.F.R. §§ 42.8(a)(3),
42.8(b)(2).
Claims

35 U.S.C. § References/
Basis
Claims
Shown
Unpatentable

Claims
Not Shown
Unpatentable
1 103(a) Hidaka, Luk,
Takemura
1
4–6 103(a) Hidaka, Luk 4–6
1 103(a) Aoyama, Luk,
Takemura
1
4–6 103(a) Aoyama, Luk,
Hidaka
4–6
Overall
Outcome
1, 4–6
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This is a final decision. Parties to the proceeding seeking judicial
review of the decision must comply with the notice and service requirements
of 37 C.F.R. § 90.2.

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FOR PETITIONER:
Jeremy Jason Lang
K. Patrick Herman
ORRICK, HERRINGTON & SUTCLIFFE LLP
ptabdocketjjl2@orrick.com
p52ptabdocket@orrick.com

FOR PATENT OWNER:
Gerald B. Hrycyszyn
Richard F. Giunta
Elisabeth Hunt
Robert A. Jensen
Gregory S. Nieberg
Anant K. Saraswat
WOLF GREENFIELD & SACKS, P.C.
ghrycyszyn-ptab@wolfgreenfield.com
rgiunta-ptab@wolfgreenfield.com
ehunt-ptab@wolfgreenfield.com
rjensen-ptab@wolfgreenfield.com
gnieberg-ptab@wolfgreenfield.com