Giriyappa, Ravichandra et al.

Patent Trials and Appeals Board

Oct 31, 2019

15261652 - (D) (P.T.A.B. Oct. 31, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/261,652 09/09/2016 Ravichandra Giriyappa 070852.000316 4347
125968 7590 10/31/2019
Vorys, Sater, Seymour and Pease LLP
(ImgTec)
1909 K St., N.W.
Ninth Floor
Washington, DC 20006
EXAMINER
FOTAKIS, ARISTOCRATIS
ART UNIT PAPER NUMBER
2633
NOTIFICATION DATE DELIVERY MODE
10/31/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patlaw@vorys.com
vmdeluca@vorys.com
vorys_docketing@cardinal_ip.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE PATENT TRIAL AND APPEAL BOARD

Ex parte RAVICHANDRA GIRIYAPPA, VINAYAK PRASAD,
and OANA ROSU

Appeal 2019-000354
Application 15/261,652
Technology Center 2600

Before ERIC S. FRAHM, SCOTT E. BAIN, and MICHAEL T. CYGAN,
Administrative Patent Judges.

CYGAN, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–6, 8, 9, 11, 14, 15, 17, 19, 20, and 22.
Appeal Br. 2. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies the real party in interest as
Imagination Technologies Limited. Appeal Br. 2.
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CLAIMED SUBJECT MATTER
The claims are directed a circuit for estimating a time difference
between a first signal and a second signal for the purpose of maintaining
time synchronization in computer and communication systems. Abstract;
Appeal Br. 3. The circuit receives a first signal, second signal, and produces
a plurality of delayed versions of the second signal. Abstract. The circuit
compares the delayed versions of the second signal to the first signal to
identify which version most closely matches the first signal. Id. The circuit
then estimates the time difference between the first and second signal. Id.
Independent claims 1 and 15 are illustrative, with limitations at issue
italicized for emphasis:
1. A circuit for estimating a time difference between an
occurrence of a first event and an occurrence of a second event,
the circuit comprising:
a first time marker generator configured to generate a
first time marker in response to the occurrence of the first
event;
a second time marker generator configured to generate a
second time marker in response to the occurrence of the second
event;
a first signal line for receiving the first time marker;
a delay unit configured to receive the second time marker
and delay the second time marker so as to provide a plurality of
delayed versions of the second time marker, each delayed
version being delayed by a different amount of delay to the
other delayed versions;
a comparison unit configured to compare each of the
delayed versions of the second time marker with the first time
marker so as to identify which of the delayed versions of the
second time marker most closely matches the first time marker
temporally; and
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a difference estimator configured to estimate the time
difference between the first and second time markers in
dependence on the identified delayed version.
15. A method of estimating a time difference between an
occurrence of a first event and an occurrence of a second event,
the method comprising:
generating a first time marker in response to the
occurrence of the first event;
generating a second time marker in response to the
occurrence of the second event;
receiving the first time marker;
receiving the second time marker and delaying the
second time marker so as to provide a plurality of delayed
versions of the second time marker, each delayed version being
delayed by a different amount of delay to the other delayed
versions;
comparing each of the delayed versions of the second
time marker with the first time marker so as to identify which
of the delayed versions of the second time marker most closely
matches the first time marker temporally; and
estimating the time difference between the first and
second time markers in dependence on the identified delayed
version.
Independent claims 1 and 20 recite a circuit and computer-readable
medium, respectively, having limitations commensurate in scope with claim
15. Dependent claims 2–6, 8, 9, 11, 14, 17, 19, and 22 each incorporate the
limitations of their respective independent claims. Claims 10 and 16 have
been cancelled, and claims 7, 12, 13, 18, and 21 have been indicated to
contain allowable subject matter, and are not on appeal. Appeal Br. 2.

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REFERENCES
Name Reference Date
Lakshmikumar US 6,104,228 Aug. 15, 2000
Wolf et al. (“Wolf”) US 2006/0140222 A1 June 29, 2006
Kataria et al. (“Kataria”) US 2008/0080563 A1 Apr. 3, 2008

REJECTIONS
Claims 15, 20, and 22 are rejected under 35 U.S.C. §102(a)(1) as
being anticipated over Lakshmikumar. Claims 1–6 are rejected under 35
U.S.C. §103 over the combination of Lakshmikumar and Wolf. Claims 8,
9, 11, and 14 are rejected under 35 U.S.C. §103 over the combination of
Lakshmikumar, Wolf, and Kataria. Claims 17 and 19 are rejected under 35
U.S.C. §103 over the combination of Lakshmikumar and Kataria.
OPINION
A. Anticipation
Claims 15, 20, and 22 are rejected under 35 U.S.C. §102(a)(1) as
being anticipated over Lakshmikumar. With respect to claim 15, the
Examiner has determined that Lakshmikumar discloses generating a first
time marker (clock signal #58, Figs. 3, 4A–6A) in response to a first event
(#58, Figs. 4A–6A), and a second time marker (clock signal #56, Figs. 4,
4A–6A) in response to a second event (#56, Figs. 4B–6B). Final Act. 7–8.
The Examiner equates the rising edges of the clock signal to a “mark in
time.” Ans. 3. The Examiner further argues that “every clock signal is
generated in response to the occurrence of an event.” Id. at 5. The
Examiner further explains that the first “event” is that of a data signal in an
electrical system, and that the second “event” is that of a data maintenance
in an electrical system. Id. at 6 (citing Lakshmikumar 1:9–25). Alternately,
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the Examiner has determined that an “event” may be the transition from a
logical “1” to or from a logical “0”, which in Lakshmikumar, generates a
rising edge of the clock signal. Ans. 6–7.
The Examiner has further determined that Lakshmikumar discloses
each of the remaining elements of claim 15 in a method of using a plurality
of delayed versions of the second time marker to identify which of the
delayed versions is closest to the first time marker, and estimating the time
difference between first and second time markers thereby. Final Act. 7–8
(citing Figs. 3–4, 4:23–65, 5:40–64, 6:60–67). Specifically, the Examiner
has determined that Lakshmikumar’s “11ΔT” is the estimated time
difference used to align the first and second time markers. Ans. 5–6 (citing
Lakshmikumar 6:36–50).
Appellant contends that the Examiner has not shown Lakshmikumar
to disclose each and every element of claim 15. Appeal Br. 7. Specifically,
Appellant contends that Lakshmikumar is not shown to disclose “generating
a first time marker in response to the occurrence of the first event” or
“generating a second time marker in response to the occurrence of the
second event.” Id. at 8. Appellant argues that the Examiner has not
distinguished between the “marker” and the “event” because the Examiner
has pointed to the same element, the clock signal, as corresponding both to
the claimed event and to the marker generated in response to that event. Id.
at 9, 12–13. Appellant further argues that the Examiner errs in ascribing the
rising edges of the clock signal as either an event or as being in response to
an event. Id. at 11.
Appellant further argues that the Examiner has not identified exactly
what in the disclosure of Lakshmikumar corresponds to the claimed
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“events.” Id. at 13. Appellant argues that the section cited by the Examiner
as disclosing a data signal corresponding to the claimed “first event” is
instead describing the switching-in of a standby clock source when a main
clock source is being disconnected for maintenance, and is not a data signal
that initiates a rising edge of a clock signal. Reply Br. 4. Appellant further
argues that a logic transition between a “1” and a “0” is not an event that
generates a rising edge between the “1” and “0” because the logical “1” does
not exist separately in the circuit or otherwise. Id. Appellant further argues
that Lakshmikumar discloses aligning the phase of signals and, thus, does
not estimate a time difference between first and second events. Appeal Br.
10. Appellant further contends that the Examiner’s interpretation of the term
“event” is outside of the broadest reasonable interpretation standard. Reply
Br. 2.
We are not persuaded that, in determining that Lakshmikumar
discloses the invention of claim 15, the Examiner has construed the phrase
“generating a [first and second] marker in response to the occurrence of
[respectively, the first and second] event,” in a manner that is inconsistent
with the Specification. The claim specifies the actions that must be
performed, i.e., generating the first and second marker, and the time at which
they must be performed; i.e., in response to first and second events. The
claim does not set forth a step of causing an event to occur, or any limitation
on the type of events that may set the time for performance of the act of
generating the first and second markers.
Absent an express intent to impart a novel meaning to a claim term,
the words take on the ordinary and customary meanings attributed to them
by those of ordinary skill in the art. Brookhill-Wilk 1, LLC v. Intuitive
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Surgical, Inc., 334 F.3d 1294, 1298 (Fed. Cir. 2003) (citation omitted).
Appellant does not indicate, nor do we discern, any definition of the term
“event” in the Specification. Appellant states that “events are occurrences.”
Appeal Br. 8. Appellant points to events in the Specification such as the
playing of a media frame by first and second speakers of a media device, in
which time markers are generated to provide an indication of when those
events have occurred. Id. However, the examples to which Appellant refers
do not clearly set forth a special definition of “events” in the Specification
that differs from the plain and ordinary meaning it would otherwise possess.
See, e.g., Starhome GmbH v. AT&T Mobility LLC, 743 F.3d 849, 856 (Fed.
Cir. 2014) (holding that the term “gateway” should be given its ordinary and
customary meaning of “a connection between different networks” because
nothing in the specification indicated a clear intent to depart from that
ordinary meaning).
We, therefore, are guided by the Appellant’s statement, consistent
with the language of claim 15, that “events” are “occurrences.” Appeal Br.
8. The types of occurrences that are disclosed by Appellant include clock
signals, periodically received timing beacons, or other events indicative of
time at a particular clock. Spec. 11:2–5 (“[t]he generators 201 and 202 may
receive the clock signals and output a time marker that indicates that same
particular time according to both clocks.”), 11:33–12:4 (“time marker
generator 201 may generate a time marker in dependence on a signal [which
may be] a timing beacon [that may comprise] a timestamp of the time
(according to a clock[)].”), 11:13–15 (“[i]n another example, the time at a
clock may be obtained indirectly via operations or tasks or events that are
synchroni[z]ed with that clock.”).
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The Examiner has provided two alternative explanations of the
“events;” i.e., the manner by which Lakshmikumar discloses generating a
time marker in dependence on a signal. The Examiner’s first alternative
explanation of the “event” causing generation of time marker signals is that
Lakshmikumar discloses “events” of data signals in an electrical system and
of data maintenance in an electrical system. Ans. 8 (citing Lakshmikumar
1:9–25). With regard to the Examiner’s first alternative explanation,
Appellant has not persuasively explained how such are outside the plain
meaning of “events” or Appellant’s proffered “occurrences.” Appellant
instead argues that the cited passage of Lakshmikumar “is clearly describing
the switching in of a standby clock source when a main clock source is being
disconnected for maintenance.” Reply Br. 4. Even accepting that
interpretation of Lakshmikumar, the switching-in of one clock source, and
switching-out of the other clock source, is an “occurrence” at each of the
respective clocks. Lakshmikumar discloses that the disclosed
synchronization of clocks is for the purpose of providing synchronization of
the clocks at the time the clocks are switched. Lakshmikumar 1:9–26. We
are, therefore, not persuaded by Appellant’s argument that the Examiner has
not explained how Lakshmikumar discloses generating first and second time
markers in response to the occurrence of events in the form of switching-out
and switching-in respective clock sources.
The Examiner’s second alternative explanation of the “event” causing
generation of time marker signals is the transitional logic causing the clock
signal to switch back and forth between “1” and “0” outputs. Ans. 7, 8. The
Examiner has determined that Lakshmikumar discloses a clock signal that
switches from “1” to “0” states based upon logic events, causing a transition
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that the Examiner designates as a time marker representative of the clock.
Id. With regard to the Examiner’s second alternative explanation, Appellant
argues that the transition from “1” to “0” defines a logical “1” rather than
being generated in response to a logical “1”, which Appellant submits does
not separately exist anywhere in the circuit or otherwise. Reply Br. 4. We
are not persuaded by Appellant’s argument that the transition in the
electrical clock signals is definitionally equivalent to the logical states
themselves. Lakshmikumar states that the clock source provides clock
signals to an electrical system; for example, clock signals having a
frequency of 1MHz. Lakshmikumar 6:9–12, 7:65–67. The Examiner has
equated the time markers to rising edges of the electrical clock signals, and
determined that these rising edges of the electrical signals are measured by
electrical components in the form of electrical edge-triggered flip-flops 68.
Final Act. 7–8. The Examiner’s cited portions of Lakshmikumar do not
support an interpretation of clock signals as pure logical states, but instead,
as electrical signals representing certain logical states. Accordingly, we
determine that the disclosure of Lakshmikumar supports the Examiner’s
interpretation of the logical states representing the signals as being distinct
from the electrical signals themselves.
Furthermore, Appellant sets forth an interpretation of Lakshmikumar
in which clock signals having edge transitions between different electrical
states exist, but are not being produced in response to any event or
occurrence. Accepting Appellant’s position would require interpreting the
clock signal’s switching between electrical states as being an effect that has
no particular cause. We decline to accept such an interpretation. Although
Lakshmikumar does not explicitly describe the means by which the clock
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produces its varying signal, Lakshmikumar describes an electrical signal
having a frequency that is produced by a clock source that necessarily
implies the existence of some electrical causative event that produces
variance in the signal. We agree that the Examiner’s identification of the
switching between logical states as producing the electrical signal is
reasonably based upon the properties of the clock source that are necessarily
inherent. Accordingly, we are not persuaded by Appellant that the
Lakshmikumar’s electrical signal edges are not generated in response to an
event or occurrence.
Appellant further argues that the claim limits the meaning of “event”
in that the preamble of the claim recites a “method of estimating a time
difference between an occurrence of a first event and an occurrence of a
second event.” Reply Br. 2, 4. Appellant argues that because
Lakshmikumar’s system aligns the phases between two clock sources, it has
“nothing to do with estimating a time difference between two events.” Id. at
2. However, the Examiner cites Lakshmikumar’s “11ΔT” as an estimated
time difference used to align the first and second time markers that were
generated in response to events, such as transitional logic events. Ans. 5–6,
8 (citing Lakshmikumar 6:36–50).
While the claim recites “estimating a time difference,” nothing in the
claim expressly excludes estimating a time difference in phased signals; any
further exemplary limitations set forth in the Specification are not to be read
into the claims. In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993).
Furthermore, the Specification characterizes signals as not being limited to a
pulse at a particular time, but including varying signals such a signal that
“pulses or changes in polarity every y seconds” according to the clock that is
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relied upon by the marker generators to generate the marker time signals.
Spec. 11:1–11. Accordingly, we are not persuaded that the claim, read in
light of the Specification, excludes estimating a time difference of signals of
different phases as disclosed by Lakshmikumar.
Consequently, we are not persuaded that Appellant has shown error
in the Examiner’s determination that Lakshmikumar discloses the invention
of claim 15. Because Appellant has not separately argued claims 20 and 22,
rejected under the same grounds, we sustain the Examiner’s anticipation
rejection of claims 15, 20, and 22.
B. Obviousness
The Examiner has rejected claims 1–6, 8, 9, 11, 14, 17, and 19 over
the combination of the teachings or suggestions of Lakshmikumar and one
or more of Wolf and Kataria. Appellant has argued that the applied
combinations of references are deficient to make obvious the claimed
invention for the same reasons as set forth for claim 15. Appeal Br. 14–15.
For at least the same reasons as discussed in the analysis of the rejection of
claim 15, supra, we are not persuaded by Appellant’s arguments regarding
claims 1–6, 8, 9, 11, 14, 17, and 19.
With respect to claims 1–6, Appellant further argues that there would
be no motivation to modify Lakshmikumar with the teachings of Wolf,
because it would be sufficient to determine the phase difference between two
clock signals, and there would be no motivation to provide a delay unit as
taught by Wolf. Appeal Br. 14. The Examiner has interpreted the claim
term “delay unit” under 35 U.S.C. § 112(f), and identified the associated
structure as a plurality of delays being a plurality of buffers. Final Act. 11.
The Examiner has determined that Lakshmikumar teaches a circuit having a
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plurality of delays, but not that those delays include a plurality of buffers.
Id. The Examiner has relied on the teachings or suggestions of Wolf that a
delay unit may comprise a plurality of buffers, and that the use of buffers in
a delay unit such as taught by Wolf would “efficiently apply the delay to the
input signal.” Id. at 12.
Appellant, in arguing that no delay unit is needed because of how a
phase difference may be determined, is arguing against features found in
Lakshmikumar, i.e., Lakshmikumar’s delay circuitry. Appellant does not
explain why, given that Lakshmikumar teaches delay circuitry, one having
ordinary skill in the art would not use buffers in that delay circuitry for the
reason identified by the Examiner. Accordingly, Appellant’s argument is
not persuasive as to error in the Examiner’s rejection of claims 1–6.
Consequently, we are not persuaded that Appellant has shown error in
the Examiner’s determination that Lakshmikumar, in view of the applied
combination with Wolf and Kataria, teaches or suggests the invention of
claims 1–6, 8, 9, 11, 14, 17, and 19, we sustain the Examiner’s obviousness
rejection of those claims.

CONCLUSION
For the above-described reasons, we affirm the Examiner’s rejection
of claims 15, 20, and 22 as being anticipated under 35 U.S.C. §102(a)(1),
and the Examiner’s rejection of claims 1–6, 8, 9, 11, 14, 17, and 19 as being
obvious under 35 U.S.C. § 103.

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DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C. § References Affirmed Reversed
15, 20, 22 102(a)(1) Lakshmikumar 15, 20, 22
1–6 103 Lakshmikumar,
Wolf
1–6
8, 9, 11, 14 103 Lakshmikumar,
Wolf, Kataria
8, 9, 11, 14
17, 19 103 Lakshmikumar,
Kataria
17, 19
Overall
Outcome
1–6, 8, 9, 11,
14, 15, 17, 19,
20, 22

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R.
§ 1.136(a)(1)(iv).

AFFIRMED