Gabor Drasny et al.

Patent Trials and Appeals Board

Jul 22, 2019

14547820 - (D) (P.T.A.B. Jul. 22, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/547,820 11/19/2014 Gabor Drasny AUS920130424US1 3884
70426 7590 07/22/2019
IBM AUSTIN IPLAW (DL)
DeLizio Law
C/O DELIZIO LAW, PLLC
15201 MASON ROAD, SUITE 1000-312
CYPRESS, TX 77433
EXAMINER
SIEK, VUTHE
ART UNIT PAPER NUMBER
2851
NOTIFICATION DATE DELIVERY MODE
07/22/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
USPTO2@DELIZIOLAW.COM
USPTO@DELIZIOLAW.COM
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte GABOR DRASNY and GAVIN B. MEIL
____________________

Appeal 2018-008337
Application 14/547,820
Technology Center 2800
____________________

Before JAMES A. WORTH, JEFFREY B. ROBERTSON, and
LILAN REN, Administrative Patent Judges.

REN, Administrative Patent Judge.

DECISION ON APPEAL1

STATEMENT OF THE CASE
Appellants2 appeal under 35 U.S.C. § 134 from a rejection of claims
11–20. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

1 The record on appeal includes the Specification filed November 19, 2014
(“Spec.”), the Examiner’s Final Office Action of October 10, 2017 (“Final
Act.”), Appellants’ Appeal Brief of March 13, 2018 (“Appeal Br.”), the
Examiner’s Answer of June 14, 2018 (“Ans.”), and Appellants’ Reply Brief
of August 14, 2018 (“Reply Br.”).
2 “International Business Machines Corporation” is identified in the Appeal
Brief as the real party in interest. Appeal Br. 3.
Appeal 2018-008337
Application 14/547,820

2
CLAIMED SUBJECT MATTER
Claim 11, reproduced below, is illustrative of the claimed subject
matter:
11. A computer program product for evaluating a circuit
design, the computer program product comprising:
a non-transitory computer readable storage medium
having program instructions including a compact multiwave
based circuit design evaluator stored thereon, the program
instructions, when executed by one or more processors, cause the
one or more processors to perform operations for evaluating a
circuit design, the program instructions comprising:
program instructions to acquire, by the compact
multiwave based circuit design evaluator, a register transfer level
circuit design;
program instructions to determine, by the multiwave based
circuit design evaluator, an input sequence of signal transition
representations associated with an input net of an indicated
component in the register transfer level circuit design, wherein
each signal transition representation represents a non-
deterministic transition from a previous signal state to a set of
one or more possible signal states, and wherein the program
instructions to determine the input sequence of signal transition
representations include program instructions to determine that
the input sequence of signal transition representations indicates
an input gated clock waveform;
program instructions to determine, by the multiwave based
circuit design evaluator and based on the indicated component
and on the input gated clock waveform, an output sequence of
signal transition representations derived from the input sequence
of signal transition representations, wherein
the program instructions to determine the output sequence
of signal transition representations include program instructions
to determine whether at least one signal transition representation
of the output sequence of signal transition representations
indicates an output gated clock waveform.
Claims Appendix (Appeal Br. 15–16).
Appeal 2018-008337
Application 14/547,820

3
REJECTIONS
Claims 11–20 are rejected under 35 U.S.C. § 101. Final Act. 3.

OPINION
The PTO recently published revised guidance on the application of
§ 101. 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed.
Reg. 50 (Jan. 7, 2019) (“Guidance”).3 Under the Guidance, we first look to
whether the claim recites:
(1) any judicial exceptions, including certain groupings
of abstract ideas (i.e., mathematical concepts, certain methods
of organizing human activity such as a fundamental economic
practice, or mental processes); and
(2) additional elements that integrate the judicial
exception into a practical application (see MPEP § 2106.05(a)-
(c), (e)-(h)).
Only if a claim (1) recites a judicial exception and (2) does not
integrate that exception into a practical application, do we then look to
whether the claim:
(3) adds a specific limitation beyond the judicial
exception that is not "well-understood, routine, conventional" in
the field (see MPEP § 2106.05(d)); or
(4) simply appends well-understood, routine,
conventional activities previously known to the industry,
specified at a high level of generality, to the judicial exception.
See Guidance.
In applying prong (1) of the Guidance, to the claims on appeal, we
agree with the Examiner that the independent claim 11 recites an abstract

3 Neither the Examiner nor Appellants had benefit of this Guidance when
advocating their respective positions concerning subject matter eligibility.
Appeal 2018-008337
Application 14/547,820

4
idea by way of a mathematical model or a mathematical correlation. See
Final Act. 3; see also Ans. 5. As the Examiner points out, the recited steps
such as the steps “to determine . . . an input sequence of signal transition
representations associated with an input net of an indicated component in the
register transfer level circuit design” and “to determine . . . an output
sequence of signal transition representations derived from the input sequence
of signal transition representations” are calculations based on mathematical
models or correlations. Final Act. 3. Accordingly, claim 1 recites one or
more mathematical concepts which are abstract ideas under the Guidance.
However, our assessment of Guidance prong (2), reveals that the
independent claim integrates the above abstract idea into a practical
application.
Appellants state that claim 11 “relates to a design tool that can
implement a phase-algebra based design evaluation to evaluate a circuit
design with a compact representation of numerous waveforms without
simulating the individual waveforms.” Appeal Br. 10. Appellants aptly
state that claim 11 “provides a technical solution that optimizes the design
verification process by avoiding simulation of individual wave forms.” Id.
As a result, claim 11 does not attempt to monopolize the mathematical
concepts at issue here but rather provides a tool “to identify potential defects
in a register transfer level (RTL) design on a system on a chip.” Spec. ¶ 2.
More specifically, claim 11 defines a specific application to eliminate
the simulation of individual wave forms when evaluating (e.g., identifying
defects) a circuit design.
To summarize, there is a meaningful limit on the mathematical
concepts, that is, the mathematical concepts are integrated into a practical
Appeal 2018-008337
Application 14/547,820

5
application for optimizing the evaluation of a circuit design which eliminates
the simulation of individual wave forms.
For this reason, we do not sustain the Examiner’s rejection of claims
11–20 under 35 U.S.C. § 101 as directed to a judicial exception without
significantly more.

DECISION
The Examiner’s decision is reversed.

REVERSED