Ex Parte Zheng et al

Patent Trial and Appeal Board

Jul 17, 2018

13652386 (P.T.A.B. Jul. 17, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/652,386 10/15/2012 Hongzhong Zheng
44429 7590 07/19/2018
Peninsula Patent Group
5061 Crail Way
El Dorado Hills, CA 95762
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
RBS2.Pl 71 US 3483
EXAMINER
DEWAN,KAMALK
ART UNIT PAPER NUMBER
2163
NOTIFICATION DATE DELIVERY MODE
07/19/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
lkreisman@peninsulaiplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HONGZHONG ZHENG and JAMES TRINGALI
Appeal 2017-011681
Application 13/652,386 1
Technology Center 2100
Before DEBRA K. STEPHENS, DANIEL J. GALLIGAN, and
DAVID J. CUTITTA II, Administrative Patent Judges.
STEPHENS, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection2 of
claims 1-24, which are all of the claims pending in the application. We
have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
1 According to Appellants, the real party in interest is Rambus, Inc. (App.
Br. 3).
2 We herein refer to the Specification, filed October 15, 2012 ("Spec.");
Final Office Action, mailed November 3, 2016 ("Final Act."); Appeal Brief,
filed April. 19, 2017 ("App. Br."); Examiner's Answer, filed July 27, 2017
("Ans."); and the Reply Brief, filed September 22, 2017 ("Reply Br.").
Appeal2017-011681
Application 13/652,386
CLAIMED SUBJECT MATTER
According to Appellants, the claims are directed to memory address
mapping (Abstract). Claim 1, reproduced below, is illustrative of the
claimed subject matter:
1. A memory system comprising:
an address mapping circuit to receive an input memory
address comprising a first set of address bits, the first set of
address bits including first bits indicating a row address and
second bits indicating a column address, the address mapping
circuit applying a logic function to a subset of the first and second
bits to generate a first portion of a mapped memory address in a
first operation, the address mapping circuit using the subset of
the first and second bits in a separate second operation,
independent of the logic function, to determine a second portion
of the mapped memory address, wherein the contents of the
subset of the first and second bits are unchanged for both the first
and second operations.
(App. Br., Claims Appendix, 18).
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Wong et al.,; hereinafter US 5,943,283 Aug. 24, 1999
"Wong"
Hobson
Yim et al.,; hereinafter
"Yim"
Garratt
US 2008/0276035 Al Nov. 6, 2008
US 2010/0011156 Al Jan. 14, 2010
US 2010/0153616 Al June 17, 2010
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Application 13/652,386
Schaefer et al.,; US 2011/0153908 Al June 23, 2011
hereinafter "Schaefer"
Tucek et al.,; hereinafter US 2012/0233381 Al Sept. 13, 2012
"Tucek"
REJECTIONS
Claims 1-3, 5, 6, 8-10, and 19-23 stand rejected under 35 U.S.C.
§ I03(a) as being unpatentable over Garratt, Wong, and Tucek (Final
Act. 12-28).
Claims 4 and 24 stand rejected under 35 U.S.C. § I03(a) as being
unpatentable over Garratt, Wong, Tucek, and Hobson (id. at 28-30).
Claim 7 stands rejected under 35 U.S.C. § I03(a) as being
unpatentable over Garratt, Wong, Tucek, and Yim (id. at 31-33).
Claims 11-14, 16, and 18 stand rejected under 35 U.S.C. § I03(a) as
being unpatentable over I03(a) as being unpatentable over Garratt, Wong,
Tucek, and Schaefer (id. at 33--41 ).
Claim 15 stands rejected under 35 U.S.C. § I03(a) as being
unpatentable over Garratt, Wong, Tucek, Schaefer, and Hobson (id. at. 41-
44).
Claim 17 stands rejected under 35 U.S.C. § I03(a) as being
unpatentable over Garratt, Wong, Tucek, Schaefer, and Yim (id. at 44--46).
Our review in this appeal is limited only to the above rejections and
the issues raised by Appellants. Arguments not made are waived. See
MPEP § 1205.02; 37 C.F.R. §§ 4I.37(c)(l)(iv) and 4I.39(a)(l).
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Application 13/652,386
ISSUES
35 US.C. § 103(a)
Appellants contend their invention as recited in claims 1, 12, and 19,
is patentable over Garratt, Wong, and Tucek (App. Br. 10-16). The issues
presented by the arguments are:
Issue 1: Has the Examiner shown the combination of Wong and
Tucek teaches or suggests a
first set of address bits including first bits indicating a row
address and second bits indicating a column address ... applying
a logic function to a subset of the first and second bits ... using
the subset of the first and second bits in a separate second
operation ... wherein the contents of the subset of the first and
second bits are unchanged for both the first and second
operations,
as recited in claim 1 and similarly recited in claims 12 and 19?
Issue 2: Did the Examiner improperly combine Garratt, Wong, and
Tucek?
ANALYSIS
Issue 1
Appellants contend the Examiner erred in finding the combination of
Wong and Tucek teaches or suggests "wherein the contents of the subset of
the first and second bits are unchanged for both the first and second
operations," as recited in claim 1 and similarly recited in claims 12 and 19
(App. Br. 13-16; Reply Br. 4--5). Specifically, Appellants argue the
Examiner ignores that Wong and Tucek organize memory arrays using
different architecture (row/column addressing via block addressing) (App.
Br. 15). Appellants argue "Tucek has no relevance to row/column
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Application 13/652,386
addressing" and "fails to disclose the claimed subset of row/column bits"
(App. Br. 15; Reply Br. 5). Appellants further contend Wong does not teach
"the claimed subset ( of row and column address bits), where the contents of
the subset are unchanged for both the first and second operations" (Reply
Br. 5). Still further, Appellants argue, even if Tucek' s line and sub line
addressing is "analogous" to row and column addressing, Tucek's "subline
address bits pass through untouched as a portion of the physical address
without undergoing a second separate operation" and "Tucek also fails to
disclose the line address bits going through any second operation" (App.
Br. 15).
We are not persuaded. The Examiner finds, and we agree, Wong's
disclosure of an "address for a storage location identif-1ying] the row and the
column associated with a memory cell in the storage location" (Wong 1 :35-
42; see Wong 5:2---6) teaches a "first set of address bits including first bits
indicating a row address and second bits indicating a column address" (Final
Act. 14). The Examiner further finds, and we agree, Wong's "mixer 510,"
which "swaps some (but not all) of the bits of logical row address RA and
with some (but not all) of the bits of logical column address CA so that
neither a logical column nor a logical row is mapped to a physical column or
row" (Wong 6:60---65; 7:39-32), teaches applying a logic function to a
"subset of the first and second bits" (see Final Act. 14). The Examiner
further finds, and we agree, Tucek discloses that "logical block address 22
(01) is applied to the block remap table 32" and that "logical block address
22 (01) also is applied to the line remap table 35" (Tucek ,r 27, Fig. 3) and,
thus, teaches "using the subset of the first and second bits in a separate
second operation ... wherein the contents of the subset of the first and
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Application 13/652,386
second bits are unchanged for both the first and second operations" (Final
Act. 14--16).
Appellants' arguments that Tucek's operations are not "row/column
addressing" operations (App. Br. 15; Reply Br. 5) or that Wong's operations
are not for "unchanged" bits (Reply Br. 5) inappropriately attack Tucek and
Wong individually when the rejection is based on the combination of Wong
and Tucek (In re Keller, 642 F.2d 413,426 (CCPA 1981) (citation omitted)).
Appellants argue Tucek does not teach row and column addresses, but the
Examiner's combination relies on Wong to teach row and column addresses
(Final Act. 14--15; Ans. 14).
Additionally, Appellants argue Wong's operations do not use
"unchanged" bits; however, the Examiner's combination relies on Tucek,
not Wong, to teach operations using a subset of unchanged bits (Final
Act. 15-16; Ans. 14--15). As such, Appellants have not persuasively
addressed the Examiner's finding that the combination of Wong and Tucek
teaches "first bits indicating a row address and second bits indicating a
column address ... 'wherein the contents of the subset of the first and
second bits are unchanged for both the first and second operations"
(Final Act. 15-16).
Furthermore, Appellants' argument that Tucek' s "line address bits" or
"subline address bits" do not "undergo[] a second separate operation" (App.
Br. 15) does not address the Examiner's finding that a first and a separate
second operation are performed on Tucek' s block bits (Final Act. 15-16
(citing Tucek ,r 27, Fig. 3)). Even further, Appellants' argument is not
commensurate with the scope of the claims. The claimed operations are
performed on a "subset of the first [ row address] and second [ column
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Application 13/652,386
address] bits" ( emphasis added), but the claims do not require that subset to
include both row address bits and column address bits. Importantly, the
Specification describes operations on subsets of bits that only include row
address bits or column address bits. Specifically, Figure 4A of the
Specification shows first and second operations performed on a subset of
bits that include only column bits: the "Column Address Bits" in "Input
Memory Address 402" is a subset of bits on which a first operation is
performed, "XOR 412," and on which a second operation is performed,
"Block Rotation 422." In particular, Figure 4A does not show any subset of
bits including both row address bits and column address bits that has both
the XOR412 and Block Rotation 422 operations performed on the subset.
As such, a subset of Tucek's bits that consists of a set of sub line bits and an
empty set of line bits ( or vice versa) teaches a subset of row and column bits
within the meaning of the claims.
Accordingly, we are not persuaded the Examiner erred in finding the
combination of Wong and Tucek teaches a
first set of address bits including first bits indicating a row
address and second bits indicating a column address ... applying
a logic function to a subset of the first and second bits ... using
the subset of the first and second bits in a separate second
operation ... wherein the contents of the subset of the first and
second bits are unchanged for both the first and second
operations,
within the meaning of claims 1, 12, and 19.
Moreover, although not relied upon in reaching our decision, we
disagree with Appellants' argument that Tucek "has no relevance to
row/column addressing" (App. Br. 15). As the Examiner points out
(Ans. 13), in Tucek, memory cells "are preferably arranged on a
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Application 13/652,386
semiconductor integrated circuit chip in a two-dimensional array" (Tucek
,r 12); the memory cells in that array are addressed via a line address, i.e., a
row, and a subline address, i.e., a column (Tucek Fig. 3).
Issue 2
Appellants contend the Examiner improperly combined Garratt,
Wong, and Tucek (App. Br. 13-14; Reply Br. 4--5). Specifically, Appellants
argue "Garratt' s mapping is ... NOT based on a logical function" and
"combining either Wong's scrambling algorithm (based on a logic function)
or Tucek's logic function with Garratt necessarily renders Garratt's physical
endurance approach useless, since remappings in Garratt's circuitry would
then be based on logical scrambling instead of physical endurance" (App.
Br. 13-14; Reply Br. 4).
Appellants' arguments, however, inappropriately require the bodily
incorporation of features taught by Garratt that are not included in the
Examiner's combination, i.e., endurance-based memory mapping (In re
Keller, 642 F .2d 425 ("The test for obviousness is not whether the features
of a secondary reference may be bodily incorporated into the structure of the
primary reference ... ")). The Examiner's combination relies on Garratt to
teach "an address mapping circuit to receive an input memory address" and
"map[ping] memory address[es]" (Final Act. 13 (citing Garratt ,r,r 6, 26,
27)). The Examiner's combination, however, does not rely on Garratt to
teach the claimed technique detailing how memory addresses are mapped
(Final Act. 13). Rather, the Examiner relies on Wong and Tucek to teach the
claimed technique for memory mapping (id. at 14--16). As such, Appellants
have not persuaded us that "combining either Wong's scrambling algorithm
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Application 13/652,386
... or Tucek' s logic function with Garratt necessarily renders Garratt[] ...
useless" (App. Br. 14).
Further, even assuming arguendo, that the combination requires the
incorporation of Garratt's endurance-based memory mapping technique, we
are not persuaded by Appellants' argument that Wong or Tucek' s memory
mapping is incompatible with Garratt (App. Br. 13-14; Reply Br. 4--5).
Specifically, that argument is supported only by attorney argument (In re
Pearson, 494 F.2d 1399, 1405 (CCPA 1974) ("Attorney's argument in a
brief cannot take the place of evidence.")). In particular, Appellants have
not provided persuasive evidence that one of ordinary skill in the art would
have been unable to preserve Garratt's endurance-based mapping, or would
have needed to remove endurance-based mapping features, when
incorporating Wong's mapping or Tucek's wear-leveling mapping for
mapping input memory addresses (KSR International Co. v. Teleflex Inc.,
550 U.S. 398, 421 (2007) ("a person of ordinary skill in the art is also a
person of ordinary creativity, not an automaton.")).
Accordingly, we are not persuaded the Examiner improperly
combined Garratt, Wong, and Tucek. Therefore, we sustain the rejection of
claims 1, 12, and 19 under 35 U.S.C. § 103(a) as being unpatentable over
Garratt, Wong, and Tucek. We likewise sustain the Examiner's rejections of
claims 2-11, 13-18, and 20-24 under 35 U.S.C. § 103(a) because
Appellants offer no additional persuasive arguments for patentability (see
App. Br. 10-17).
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DECISION
The Examiner's rejection of claims 1-3, 5, 6, 8-10, and 19-23 under
35 U.S.C. § 103(a) as being unpatentable over Garratt, Wong, and Tucek is
affirmed.
The Examiner's rejection of claims 4 and 24 under 35 U.S.C. § 103(a)
as being unpatentable over Garratt, Wong, Tucek, and Hobson is affirmed.
The Examiner's rejection of claim 7 under 35 U.S.C. § 103(a) as
being unpatentable over Garratt, Wong, Tucek, and Yim is affirmed.
The Examiner's rejection of claims 11-14, 16, and 18 under 35 U.S.C.
§ 103(a) as being unpatentable over 103(a) as being unpatentable over
Garratt, Wong, Tucek, and Schaefer is affirmed.
The Examiner's rejection of claim 15 under 35 U.S.C. § 103(a) as
being unpatentable over Garratt, Wong, Tucek, Schaefer, and Hobson is
affirmed.
The Examiner's rejection of claim 17 under 35 U.S.C. § 103(a) as
being unpatentable over Garratt, Wong, Tucek, Schaefer, and Yim is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(±).
AFFIRMED
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