Ex Parte Yelehanka et al

Board of Patent Appeals and Interferences

Jun 14, 2012

11466350 (B.P.A.I. Jun. 14, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/466,350 08/22/2006 Pradeep Ramachandramurthy Yelehanka 1016-021.D1.C1 1884
22898 7590 06/14/2012
ISHIMARU & ASSOCIATES LLP
2055 GATEWAY PLACE
SUITE 700
SAN JOSE, CA 95110
EXAMINER
TRAN, LONG K
ART UNIT PAPER NUMBER
2829
MAIL DATE DELIVERY MODE
06/14/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
________________

Ex parte PRADEEP RAMACHANDRAMURTHY
YELEHANKA, TONG QING CHEN, ZHI YONG HAN,
ZHEN JIA ZHENG, KELVIN ONG, TIAN HAO GU, and
SYN KEAN CHEAH
________________

Appeal 2010-001933
Application 11/466,350
Technology Center 2800
________________

Before JOHN A. JEFFERY, CARL W. WHITEHEAD, JR., and ANDREW
CALDWELL, Administrative Patent Judges.

CALDWELL, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-001933
Application 11/466,350

2
SUMMARY
Appellants appeal under 35 U.S.C. §§ 6(b) and 134(a) from the
Examiner’s rejection of claims 1-5.
We reverse.

STATEMENT OF CASE
Appellants describe the present invention as an integrated circuit
including a local interconnect opening. Abstract.
Independent claim 1 is illustrative:
1. An integrated circuit comprising:
a semiconductor substrate having a first gate dielectric and a first gate
respectively on and over the semiconductor substrate, the
semiconductor substrate having a junction adjacent the first gate
dielectric;
a first liner over the semiconductor substrate around the first gate;
a first spacer on the first liner;
a first shaped spacer on the first spacer;
a first dielectric layer over the semiconductor substrate having a local
interconnect opening provided therein;
a second dielectric layer over the first dielectric layer having a local
interconnect opening provided therein; and
a conductive material in the local interconnect openings.
The Examiner relies on the following as evidence of unpatentability:
Ootsuka

US 2004/0253790 A1

Dec. 16 2004
(filed May 28, 2004)

Appeal 2010-001933
Application 11/466,350

3
REJECTION
The Examiner rejected claims 1-5 under 35 U.S.C. § 102(e) as being
anticipated by Ootsuka.

ANALYSIS
This application is a continuation of application 11/045,202 filed
January 27, 2005, which is a divisional of application 10/359,975 filed
February 27, 2003. Claims 1-5 of this application are identical to claims 11-
15 of the ‘975 application. Our review of this application file and the prior
application files identified above has determined that this application is
entitled to the benefit of the filing date of the ‘975 application. Ootsuka,
with a filing date of May 28, 2004, is not prior art under 35 U.S.C. § 102(e)
since Ootsuka was filed after this application’s effective filing date of
February 27, 2003. Nor is Ootsuka prior art under any other section of
35 U.S.C. § 102. Although Appellants never raised this issue in either the
Supplemental Appeal Brief filed on April 10, 2009 or in the Reply Brief
filed on September 8, 2009, we raise this issue on our own. Since Ootsuka
is not prior art, we need not address the issues raised by Appellants in either
the Supplemental Appeal Brief or the Reply Brief or by the Examiner in the
Answer mailed on July 8, 2009. Accordingly, the rejection of claims 1-5
under 35 U.S.C. § 102(e) as being anticipated by Ootsuka is reversed.

Appeal 2010-001933
Application 11/466,350

4
DECISION
The Examiner’s decision rejecting claims 1-5 is reversed.

REVERSED

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