Ex Parte Yang et al

Patent Trial and Appeal Board

Sep 28, 2017

13875357 (P.T.A.B. Sep. 28, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/875,357 05/02/2013 Shaohua Yang 5887-434 3060
144016 7590 10/02/2017
SheriHan Rnsis; P P
EXAMINER
1560 Broadway, Suite 1200
Denver, CO 80202
MCMAHON, DANIEL F
ART UNIT PAPER NUMBER
2117
NOTIFICATION DATE DELIVERY MODE
10/02/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
e-docket @ sheridanross. com
mreno @ sheridanross. com
mells worth @ sheridanross .com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SHAOHUA YANG, ANATOLI A. BOLOTOV, and
MIKHAIL I. GRINCHUK
Appeal 2016-0061281
Application 13/875,357
Technology Center 2100
Before THU A. DANG, ELENI MANTIS MERCADER, and CATHERINE
SHIANG, Administrative Patent Judges.
MANTIS MERCADER, Administrative Patent Judge.
DECISION ON APPEAL
1 The real party of interest is Avago Technologies. App. Br. 2.
Appeal 2016-006128
Application 13/875,357
STATEMENT OF CASE
Appellants appeal under 35 U.S.C. § 134 from a rejection of claims 1—
4, 8—17, and 20. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
THE INVENTION
The claimed invention is directed to protected data encoding.
Abstract.
Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. A data processing system, the system comprising:
a data encoder circuit operable to apply a first encoding
algorithm to a data input to yield an encoded data output;
a parity generator circuit operable to generate a parity value
based upon the data input;
a parity encoder circuit operable to apply a second encoding
algorithm to the parity value to yield an encoded parity output;
and
an error flag generation circuit operable indicate an error in the
encoded data output based at least in part on a combination of the
encoded parity output.
REFERENCE
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Gunnam US 2011/0264979 A1 Oct. 27, 2011
REJECTION
The Examiner made the following rejection:
Claims 1—4, 8—17, and 20 stand rejected under 35 U.S.C. § 102(a)(1)
as being anticipated by Gunnam.
2
Appeal 2016-006128
Application 13/875,357
ANALYSIS
We adopt the Examiner’s findings in the Answer, Advisory Action,
and Final Action and we add the following primarily for emphasis. We note
that if Appellants failed to present arguments on a particular rejection, we
will not unilaterally review those uncontested aspects of the rejection. See
Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential); Hyatt v.
Dudas, 551 F.3d 1307, 1313—14 (Fed. Cir. 2008) (The Board may treat
arguments Appellant failed to make for a given ground of rejection as
waived).
Appellants argue that Gunnam does not explicitly disclose an encoder
Circuit, and only implies an encoder circuit based upon discussion of a
decoder circuit which operates on an ‘“encoded codeword’”
which includes both user data and CRC bits encoded together to yield an
“‘FDPC-encoded codeword’” (referring to Gunnam’s Abstract) (App. Br.
10). According to Appellants, encoding a combination of user data and
CRC bits implied in Gunnam requires only a single encoder circuit applying
the same algorithm across the combination of the user data and the CRC
bits, as such any implication of a data encoder circuit in Gunnam cannot be
reasonably alleged as necessarily disclosing two encoder circuits as set forth
in claim 1 (App. Br. 10). Appellants argue that each instance in which an
encoded codeword is discussed does not necessarily or inherently require a
different encoding circuit, the rejection has failed to meet even the minimal
standard of identifying elements in the cited art that correspond to each and
every element of claim 1 (App. Br. 11).
We are not persuaded by Appellants’ argument. Although claims are
interpreted in light of the specification, limitations from the specification are
3
Appeal 2016-006128
Application 13/875,357
not read into the claims. In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir.
1993). During ex parte prosecution, claims must be interpreted as broadly
as their terms reasonably allow because Applicants have the power during
the administrative process to amend the claims to avoid the prior art. In re
Zletz, 893 F.2d 319, 322 (Fed. Cir. 1989). Claim 1 does not require that the
“data encoder circuit” and the “parity encoder circuit” are different encoder
circuits. Thus, Appellants’ argument is not commensurate in scope with the
claimed language.
Appellants further argue that one of ordinary skill in the art would not
understand that a claim element operating based upon an “‘encoded parity
output’” can be construed so broadly as to actually operate on the “parity
value” which is also specifically set forth in the claim. App. Br. 12.
Appellants assert that such a claim construction would effectively read the
encoded parity output out of the claim. App. Br. 12. Appellants further
argue that the claimed “‘at least in part’” modifies “‘the encoded parity
bits’” language of claim 1, and not the “‘indicate an error in the encoded
data output’” of claim 1. App. Br. 12—13.
We are not persuaded by Appellants’ argument. The Examiner finds,
and we agree, claim 1 recites “based at least in part on a combination of the
encoded parity output” (Ans. 8). The Examiner finds that under the broadest
reasonable interpretation, the results of CRC decoding (Fig. 3, element 306)
are at least part of the encoded parity output (Ans. 8). Furthermore, error
determinations in a decoding system use intermediate decoding results for
efficient decoding of LDPC-encoded codewords (Ans. 8). We further agree
with the Examiner that the CRC bits (i.e., parity value as recited in claim 1)
are part of the LDPC-encoded codeword (i.e., encoded parity output as
4
Appeal 2016-006128
Application 13/875,357
recited in claim 1) and not a separate parity value as argued, through the
process disclosed in paragraph 58 ‘“[tjypically a number r of CRC bits are
appended to the user data at the transmitter before LDPC encoding’” (Ans.
8—9). We also agree with the Examiner that the claimed language is ‘“the
encoded parity output’” and not “‘the encoded parity bits’” as argued by
Appellants (Ans. 9).
Appellants further argue that the error checking process of Gunnam
utilizes non-encoded (i.e., decoded) CRC bits (App. Br. 14) and thus, does
not meet the claim language which requires that the error flag generation
circuit operates on the “‘encoded parity output,”’ and not the “‘parity
value’” (App. Br. 14).
We do not agree with Appellants. We agree with the Examiner that
Figure 3, element 306, and paragraph 63, disclose CRC bits which are
disclosed as part of the encoded parity output, used to generate an error flag
(Ans. 9). Thus, Figure 3 discloses an error flag generation system which
starts with an “encoded parity output” and generates intermediate results
which may indicate an error (Ans. 9). Accordingly, Gunnam discloses a
system that inputs “‘encoded [parity] output’” and based on parts of that
value may generate an error flag (Fig. 3, elements 306, 322, and “‘stop’”)
(Ans. 9).
On this record, we affirm the Examiner’s rejection of claim 1. With
respect to additional arguments made regarding claims 2—3 and 4 (App. Br.
15—19), we adopt the Examiner’s findings and conclusions in the Answer
without having to repeat them herein (Ans. 9—11). We also affirm the
Examiner’s rejections of claims 8—17 and 20 not argued separately.
5
Appeal 2016-006128
Application 13/875,357
DECISION
For the above reasons, the Examiner’s rejection of claims 1—4, 8—17,
and 20 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
6