Ex Parte Yang et al

Patent Trial and Appeal Board

Mar 30, 2016

12454283 (P.T.A.B. Mar. 30, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/454,283 05/15/2009
109673 7590 04/01/2016
McClure, Qualey & Rodack, LLP
3100 Interstate North Circle
Suite 150
Atlanta, GA 30339
FIRST NAMED INVENTOR
Li-Ping Yang
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
251812-3230 3562
EXAMINER
DULKA, JOHN P
ART UNIT PAPER NUMBER
2895
NOTIFICATION DATE DELIVERY MODE
04/01/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
uspatents@mqrlaw.com
dan.mcclure@mqrlaw.com
gina.silverio@mqrlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte LI-PING YANG,
PI-CHENG CHEN, HAN-CHANG KANG,
and RAN-HONG YAN
Appeal2014-002280
Application 12/454,283
Technology Center 2800
Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and
JAMES C. HOUSEL, Administrative Patent Judges.
HANLON, Administrative Patent Judge.
DECISION ON APPEAL
A. STATEMENT OF THE CASE
The Appellants filed an appeal under 35 U.S.C. § 134 from a final rejection
of claims 1-15. We have jurisdiction under 35 U.S.C. § 6(b ).
We AFFIRM-IN-PART.
Representative claim 1 is reproduced below from the Claims Appendix of
the Appeal Brief dated October 31, 2012 ("App. Br."). The limitations at issue are
italicized.
1. A method of fabricating integrated circuits, comprising the
steps of:
Appeal2014-002280
Application 12/454,283
a) with reference to a physical design of a circuit of a hardware
unit, preparing an integrated circuit component mask layout set
associated with component photomasks suitable for fabricating an
array of the hardware units on a wafer,
wherein the integrated circuit component mask layout set has an
array of component mask layout portions that correspond respectively
to places of the hardware units on the wafer, and a grid of spacer lines
that serve to isolate adjacent ones of the component mask layout
portions from each other, such that the hardware units are spaced apart
from each other by a grid of scribe lines corresponding to the spacer
lines when the hardware units are formed on the wafer using the
component photomasks, and
wherein the integrated circuit component mask layout set
further has interconnect mask layout portions that are suitable for
fabricating interconnections on the wafer, the interconnections
establishing electrical connections between adjacent ones of the
hardware units on the wafer via a plurality of conductive paths that
span the scribe lines;
b) preparing the component photomasks with reference to the
integrated circuit component mask layout set,
wherein each of the component photomasks has component
mask portions respectively corresponding to the component mask
layout portions, and configured for fabricating the array of the
hardware units on the wafer,
wherein each of a subset of the component photomasks further
has interconnect mask portions corresponding to the interconnect
mask layout portions, and configured for fabricating the
interconnections on the wafer;
c) forming the array of the hardware units and the
interconnections on the wafer using the component photomasks
prepared in step b ); and
d) cutting the wafer along selected ones of the scribe lines so as
to form a plurality of integrated circuit dies;
wherein each of the integrated circuit dies is independently
selected from a single-type including only one of the hardware units,
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Appeal2014-002280
Application 12/454,283
and a multi-type including a plurality of the hardware units that are
interconnected electrically via uncut ones of the conductive paths.
The claims on appeal stand rejected as follows:
(1) claims 1--4, 6-9, and 11-14 under 35 U.S.C. § 103(a) as unpatentable
over Lubow et al. 1 in view ofNishi;2 and
(2) claims 5, 10, and 15 under 35 U.S.C. § 103(a) as unpatentable over
Lubow in view of Nishi, and further in view of Kirloskar et al. 3
B. DISCUSSION
1. Claims 1-5
The Examiner finds Lubow discloses a method of fabricating integrated
circuits comprising, inter alia, forming an array of hardware units and
interconnections on a wafer using a plurality of component photomasks as recited
in the claims on appeal. Ans. 2.4 The Examiner finds "[t]he deficiency of Lubow
with respect to the present application is that Lubow does not specifically teach of
how the masks/reticles are made/designed." Ans. 2. Thus, the Examiner turns to
Nishi. See Ans. 2-3.
The Examiner finds Nishi discloses a method for producing masks/reticles
wherein master reticles (corresponding to the claimed integrated circuit component
mask layout set) are used to make working reticles (corresponding to the claimed
component photomasks ). Ans. 2-3. According to the Examiner, "there is a direct
1-to-l correspondence between the master reticle and the working reticle" in the
method ofNishi. Ans. 3. Thus, the Examiner finds that, in Nishi, the working
reticle is an exact copy of the master reticle. Ans. 5.
1 US 5,801,406, issued September 1, 1998 ("Lubow").
2 US 2004/0036846 Al, published February 26, 2004 ("Nishi").
3 US 2003/0214317 Al, published November 20, 2003 ("Kirloskar").
4 Examiner's Answer dated October 23, 2013.
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Appeal2014-002280
Application 12/454,283
The Examiner concludes that making the photomasks disclosed in Lubow
using the method disclosed in Nishi would have been obvious to one of ordinary
skill in the art. Ans. 4.
The Appellants direct our attention to Nishi Figure 4, reproduced below,
which illustrates a plurality of master reticles 46A to 46H. 5 App. Br. 8.
FIC'' 4 ;;, . ·.
Nishi Fig. 4 is a diagram showing a plurality of master reticles
corresponding to a partial existing pattern.
5 Master reticle 46A, for example, comprises original pattern S 17B which is
surrounded by light shield band 56A and alignment marks 64A and 64B. Nishi
ii 122.
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Application 12/454,283
The Appellants argue that it is unclear how a single master reticle of Nishi
includes interconnect mask [layout] portions as recited in claim 1.6 App. Br. 9.
In response, the Examiner does not direct us to any interconnect mask layout
portions in the master reticles of Nishi. Rather, the Examiner appears to find that
the working reticles in Nishi include interconnect mask portions and directs our
attention to Nishi paragraph 137, disclosing that copies of the working reticle may
be made. Ans. 12. Based on these findings, the Examiner contends that a copy of
the working reticle, rather than Nishi's master reticle, may be considered an
"integrated circuit component mask layout set" as recited in claim 1. Ans. 3, 12.
Nishi discloses that "a necessary number of working reticle having the same
pattern as that of the working reticle 43 can be produced in a short time only by
repeating the steps 111to123." Nishi i-f 137. In short, steps 111 to 123, depicted
in Nishi Figures 8B and 8C, disclose that a master reticle, not a working reticle, is
used to form any subsequent working reticles. Thus, one of ordinary skill in the art
would not have considered a subsequent copy ofNishi's working reticle to be an
"integrated circuit component mask layout set" within the scope of claim 1.
The Examiner also contends that Nishi's design layout, rather than Nishi's
master reticle, can be said to correspond to the "integrated circuit component mask
layout set" recited in claim 1. Ans. 3--4. Thus, in the words of the Examiner,
"Nishi in combination with Lubow teach of 'interconnect mask portions' in the
design-layout and the photo mask itself." Ans. 15.
6 According to the Appellants, "[t]he interconnect mask layout portions (Pconnect)
correspond to places of the interconnections 33 that are to be formed on the wafer
3 for establishing electrical connections between the hardware units (unitl, unit2,
unit3, unit4) in each integrated circuit die 30." Spec. 14, 1. 24--15, 1. 2; see also
Appellants' Fig. 1.
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Appeal2014-002280
Application 12/454,283
Claim 1 recites, in relevant part, the steps of:
a) with reference to a physical design of a circuit of a hardware
unit, preparing an integrated circuit component mask layout set
associated with component photomasks suitable for fabricating an
array of the hardware units on a wafer ... ;
b) preparing the component photomasks with reference to the
integrated circuit component mask layout set ....
App. Br., Claims Appendix A-1.
Interpreting Nishi' s design layout as the claimed "integrated circuit
component mask layout set," there is no showing on this record that either Lubow
or Nishi disclose the step of preparing an integrated circuit component mask layout
set with reference to a physical design of a circuit. Thus, the Examiner has failed
to show that the combined teachings of Lubow and Nishi disclose all of the
limitations in claim 1.
For the reasons set forth above, the Examiner has failed to satisfy the initial
burden of presenting a prima facie case of obviousness. See In re Piasecki, 745
F.2d 1468, 1472 (Fed. Cir. 1984) (Examiner bears the initial burden of presenting a
prima facie case ofunpatentability). Therefore, the§ 103(a) rejection of claims 1-
4 is not sustained.
The Examiner's reliance on Kirloskar in the rejection of dependent claim 5
does not cure the deficiencies discussed above. Therefore, the§ 103(a) rejection of
claim 5 is not sustained.
2. Claims 11-15
Independent claim 11 recites a method of fabricating integrated circuits,
comprising, inter alia, the step of "preparing an integrated circuit component mask
layout set associated with component photomasks suitable for fabricating an array
of the hardware units on a wafer." App. Br., Claims Appendix A-5. Claim 11
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Application 12/454,283
does not otherwise recite the structure of the integrated circuit component mask
layout set.
The Examiner concludes that preparing an integrated circuit component
mask layout set associated with the photomasks disclosed in Lubow would have
been obvious to one of ordinary skill in the art based on the teachings in Nishi.
Final 7-8, 14;7 Ans. 4.
In the Reply Brief, the Appellants argue for the first time on appeal that the
Examiner's reasons for combining the disclosures of Lubow and Nishi are
erroneous. Reply Br. 3--4. 8 Suffice it to say that the Appellants have failed to
show good cause why their arguments could not have been presented in the Appeal
Brief. 37 C.F.R. § 41.41(b)(2) (2012). Therefore, the Appellants' arguments will
not be considered on appeal.
For the reasons set forth in the Final Office Action and the Examiner's
Answer, the§ 103(a) rejection of claims 11-14 is sustained.
The Appellants do not present arguments in support of the separate
patentability of claim 15. Therefore, the§ 103(a) rejection of claim 15 is also
sustained.
3. Claims 6-10
Independent claim 6 recites a method of fabricating integrated circuits,
comprising, inter alia, the step of "preparing a plurality of component photomasks
suitable for fabricating an array of hardware units on a wafer." App. Br., Claims
Appendix A-3.
7 Final Office Action dated May 18, 2012.
8 Reply Brief dated December 3, 2013.
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Application 12/454,283
The Appellants summarily argue that claim 6 is patentable over the
combination of Lubow and Nishi for the reasons discussed in connection with the
rejection of claim 1 and dependent claims 7-10 are allowable because they depend
from claim 6. App. Br. 10-11.
Significantly, claim 6 does not recite that the plurality of component
photomasks are prepared using an integrated circuit component mask layout set as
recited in claim 1. Therefore, the Appellants' arguments do not demonstrate
reversible error in the Examiner's rejection of claim 6.
For the reasons set forth in the Final Office Action and the Examiner's
Answer, the§ 103(a) rejections of claim 6-10 are sustained.
C. DECISION
The Examiner's decision to reject claims 1--4 under 35 U.S.C. § 103(a) as
unpatentable over Lubow in view of Nishi is reversed.
The Examiner's decision to reject claim 5 under 35 U.S.C. § 103(a) as
unpatentable over Lubow in view of Nishi, and further in view of Kirloskar is
reversed.
The Examiner's decision to reject claims 6-9 and 11-14 under 35 U.S.C.
§ 103(a) as unpatentable over Lubow in view of Nishi is affirmed.
The Examiner's decision to reject claims 10 and 15 under 35 U.S.C.
§ 103(a) as unpatentable over Lubow in view of Nishi, and further in view of
Kirloskar is affirmed.
No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(l).
AFFIRMED-IN-PART
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