Ex Parte Yamazaki

Patent Trial and Appeal Board

Jul 27, 2018

12913464 (P.T.A.B. Jul. 27, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/913,464 10/27/2010
26171 7590 07/31/2018
FISH & RICHARDSON P.C. (DC)
P.O. BOX 1022
MINNEAPOLIS, MN 55440-1022
UNITED ST A TES OF AMERICA
FIRST NAMED INVENTOR
Shunpei Yamazaki
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
12732-0725001 3934
EXAMINER
BELL, LAUREN R
ART UNIT PAPER NUMBER
2816
NOTIFICATION DATE DELIVERY MODE
07/31/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
P ATDOCTC@fr.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SHUNPEI YAMAZAKI
Appeal2016-008587 1
Application 12/913,4642
Technology Center 2800
Before JUSTIN BUSCH, JOHN D. HAMANN, and JOYCE CRAIG,
Administrative Patent Judges.
HAMANN, Administrative Patent Judge.
DECISION ON APPEAL
Appellant files this appeal under 35 U.S.C. § 134(a) from the
Examiner's Final Rejection of claims 1-28, 32, and 36-38. We have
jurisdiction under 35 U.S.C. § 6(b). We heard oral arguments on April 17,
2018. A transcript of the hearing was added to the record.
We reverse.
1 Our decision relies upon Appellant's Appeal Brief ("App. Br.," filed
Dec. 28, 2015), ReplyBrief("ReplyBr.," filed August 29, 2016), and
Specification ("Spec.," filed October 27, 2010), as well as the Examiner's
Answer ("Ans.," mailed June 29, 2016) and the Final Office Action ("Final
Act.," mailed April 9, 2015).
2 Appellant identified the real party in interest as Semiconductor Energy
Laboratory Co., Ltd. App. Br. 1.
Appeal2016-008587
Application 12/913,464
THE CLAIMED INVENTION
Appellant's claimed invention relates to a first transistor and a second
transistor, where the second transistor has an oxide semiconductor layer and
an extremely low off current. Abstract. The gate of the first transistor and
either the source or drain of the second transistor are electrically connected
to each other. Id. Claim 1 is illustrative of subject matter on appeal and is
reproduced below.
1. A semiconductor device comprising:
a first transistor comprising a first gate electrode, the first
gate electrode being formed over a substrate; and
a second transistor over the substrate, the second
transistor comprising a second source electrode and a second
drain electrode,
wherein a channel formation region of the first transistor
comprises crystalline silicon;
wherein the second transistor includes an oxide
semiconductor layer, the oxide semiconductor layer including a
channel formation region, the channel formation region of the
second transistor being intrinsic or substantially intrinsic,
wherein the first gate electrode and one of the second
source electrode and the second drain electrode are electrically
connected to each other, and
wherein an off current of the second transistor is 1 x 10-20
A or less.
REJECTIONS 3 ON APPEAL
(1) The Examiner rejected claims 1, 2, 4--11, 13-20, 22, 23, 25-28,
32, and 36--38 under 35 U.S.C. § I03(a) as being unpatentable over the
combination of Kondou et al. (US 4,902,637; issued Feb. 20, 1990)
(hereinafter "Kondou"), Wang et al. (US 2009/0114918 Al; published May
3 The Examiner withdrew the 35 U.S.C. § 112, fourth paragraph, rejection of
claim 27. Ans. 2.
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Application 12/913,464
7, 2009) (hereinafter "Wang"), Kochi et al. (US 5,812,231; issued Sept. 22,
1998) (hereinafter "Kochi"), and Yano4 et al. (US 2010/0295042 Al;
published Nov. 25, 2010) (hereinafter "Yano").
(2) The Examiner rejected claims 3, 12, and 24 under 35 U.S.C.
§ I03(a) over Kondou, Wang, Kochi, Yano, and Hiramoto et al. (US
6,989,569 Bl; issued Jan. 24, 2006) (hereinafter "Hiramoto").
(3) The Examiner rejected claim 21 under 35 U.S.C. § I03(a) over
Kondou, Wang, Kochi, Yano, and Irving et al. (US 2008/0296567 Al;
published Dec. 4, 2008) (hereinafter "Irving").
(4) The Examiner rejected claims 1-9, 22-28, 30, and 32 for non-
statutory double patenting over claims 1, 5, and 6 of U.S. Patent No.
8,389,417 in view ofKondou, Kochi, and Yano.
(5) The Examiner provisionally rejected claims 1-6, 10-15, and
22-27 for non-statutory double patenting over claims 1, 5, and 10 of co-
pending U.S. Application No. 12/906,565 in view ofKochi and Yano.
(6) The Examiner provisionally rejected claims 7-9, 16-18, 20, 28,
30, and 32 for non-statutory double patenting over claims 1 and 5 of co-
pending U.S. Application No. 12/906,565 in view ofKondou, Kochi, and
Yano.
(7) The Examiner provisionally rejected claims 1, 2, 5, 7, 9, 22, 23,
and 26-32 for non-statutory double patenting over claims 4, 10, and 13 of
co-pending U.S. Application No. 13/336,549 in view of Kochi and Yano.
4 We rely on the English language equivalent of WO 2009/093625, as the
Examiner did. Final Act. 3.
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Application 12/913,464
(8) The Examiner provisionally rejected claims 8, 28, and 30 for
non-statutory double patenting over claims 4, 10, and 13 of co-pending U.S.
Application No. 13/336,549 in view ofKondou, Kochi, and Yano.
(9) The Examiner provisionally rejected claims 10 and 14--20 for
non-statutory double patenting over claims 4, 10, and 13 of co-pending U.S.
Application No. 13/336,549 in view of Wang, Kochi, and Yano.
ISSUE
The dispositive issue for this appeal is whether Y ano teaches or
suggests a semiconductor layer that includes a channel formation region that
is "intrinsic or substantially intrinsic."
ANALYSIS
We find Appellant's arguments discussed herein persuasive.
(1) § 103 reiections
Appellant argues that Y ano does not teach or suggest a semiconductor
layer that includes a channel formation region that is "intrinsic or
substantially intrinsic," in accordance with independent claims 1, 10, and 22.
App. Br. 3-5. More specifically, Appellant argues that the portions ofYano
that the Examiner cites do not teach or suggest that the channel formation
region "is intrinsic or substantially intrinsic." Id. at 5 ( citing Y ano ,r,r 44,
99-100, 156).
The Examiner finds that Y ano teaches or suggests the disputed
limitation. See Ans. 7-8. The Examiner finds that the broadest reasonable
interpretation of "intrinsic" is a semiconductor that "is not doped with
impurities." Id. at 7 (citing COLLINS ENGLISH DICTIONARY-COMPLETE AND
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Application 12/913,464
UNABRIDGED (12th ed. 2014) (defining an intrinsic semiconductor as "an
almost pure semiconductor to which no impurities have been added and in
which the electron and hole densities are equal at thermal equilibrium")).
Using this interpretation, the Examiner finds that Y ano teaches a
semiconductor's channel formation region is "intrinsic or substantially
intrinsic" because Yano teaches not doping the channel formation region.
Id. (Yano ,r,r 101-103). The Examiner also finds that Yano teaches
purifying the channel formation region by removing elements, such as
hydrogen, which degrade the channel's characteristics, consistent with the
Specification's teachings. Id. at 7-8 (citing Yano ,r,r 100-103; Spec. ,r,r 59,
149).
We agree with Appellant that Y ano fails to teach or suggest the
disputed limitation. We find that the Examiner errs as to the broadest
reasonable interpretation of "intrinsic." As the Specification makes clear, an
oxide semiconductor is made to be "intrinsic or substantially intrinsic," in
the context of the present invention, by the "elimination of impurities such
as hydrogen and water and oxygen vacancy as much as possible." See Spec.
,r 149; see also Helmsderfer v. Bobrick Washroom Equip., Inc., 527 F .3d
1379, 1381 (Fed. Cir. 2008) ("A patentee may act as its own lexicographer
and assign to a term a unique definition that is different from its ordinary
and customary meaning; however, a patentee must clearly express that intent
in the written description."). Accordingly, the Examiner's interpretation is
unreasonably broad in light of the Specification. See In re Suitco Surface,
Inc., 603 F.3d 1255, 1259---60 (Fed. Cir. 2010) (finding that although "the
PTO must give claims their broadest reasonable construction consistent with
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Application 12/913,464
the specification[,] ... claims should always be read in light of the
specification and teachings in the underlying patent") ( citation omitted).
As to Y ano 's teachings, we disagree with the Examiner that Y ano
teaches or suggests removing hydrogen in accordance with the present
invention. Rather than removing as many impurities ( e.g., hydrogen) as
possible, Yano teaches obtaining a uniform concentration of hydrogen to
alleviate problems that occur when an oxide film differs in composition from
part to part. See Y ano ,r,r 100-103. Further, Y ano makes no mention of
addressing oxygen vacancies. Id. Accordingly, we find that the cited
portions of Y ano fail to teach or suggest the disputed limitation.
Accordingly, we do not sustain the Examiner's§ 103 rejection of
independent claims 1, 10, and 22, as well as claims 2, 4--9, 11, 13-20, 23,
25-28, 32, and 36-38, as they depend from one of these independent claims.
We also do not sustain the Examiner's§ 103 rejections of (i) claims 3, 12,
and 24; and (ii) claim 21, as they depend from one of independent claims 1,
10, and 22.
(2) Non-statutory obviousness double patenting reiections
The Examiner rejects claims 1-20 and 22-32 for non-statutory double
patenting across various grounds of rejection. See supra Rejections (4}-(9).
For each of these double patenting rejections, the Examiner relies on Yano
for teaching or suggesting a semiconductor layer that includes a channel
formation region that is "intrinsic or substantially intrinsic," with respect to
the independent claims. Final Act. 23--48.
Appellant argues that the Examiner errs with respect to the double
patenting rejections because Yano does not disclose the features of the
independent claims. App. Br. 8. As we find above, we agree with Appellant
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that Y ano fails to teach or suggest a semiconductor layer that includes a
channel formation region that is "intrinsic or substantially intrinsic," which
is recited in each of the independent claims. See supra § 1.
Accordingly, we do not sustain any of the Examiner's non-statutory
double patenting rejections.
DECISION
We reverse the Examiner's decision rejecting claims 1-28, 32, and
36-38 under§ 103.
We reverse the Examiner's decision rejecting claims 1-20 and 22-32
for non-statutory double patenting.
REVERSED
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