Ex Parte Yamazaki

Patent Trial and Appeal Board

Sep 6, 2017

13298469 (P.T.A.B. Sep. 6, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/298,469 11/17/2011 Shunpei YAMAZAKI 740756-3650 4371
22204 7590 09/08/2017
NIXON PEABODY, LLP
799 Ninth Street, NW
SUITE 500
WASHINGTON, DC 20001
EXAMINER
LIU, BENJAMIN T
ART UNIT PAPER NUMBER
2893
NOTIFICATION DATE DELIVERY MODE
09/08/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
nppatent @ nixonpeabody. com
ipairlink @ nixonpeabody. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SHUNPEI YAMAZAKI
Appeal 2016-000590
Application 13/298,4691
Technology Center 2800
Before JEAN R. HOMERE, MICHAEL J. STRAUSS,
and PHILLIP J. BENNETT, Administrative Patent Judges.
HOMERE, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant seeks our review under 35 U.S.C. § 134(a) of the
Examiner’s Final Rejection of claims 1—16, which constitute all of the
claims pending in this appeal. App. Br. 3. We have jurisdiction under 35
U.S.C. § 6(b).
We affirm.
1 Appellant identifies the real party in interest as Semiconductor Energy
Laboratory Co., Ltd. App. Br. 3.
Appeal 2016-000590
Application 13/298,469
Introduction
According to Appellant, the claimed subject matter is directed to a
complementary metal oxide semiconductor (CMOS) device including an n-
channel thin film transistor (TNT) and a p-channel TNT. Spec. 1:5—17, Fig.
10F. In particular, the n-channel transistor includes a first gate electrode
containing a first conductive layer extending beyond the side edges of a
second conductive layer. Further, the p-channel transistor includes a second
gate electrode containing a third and fourth conductive layers such that the
angle between an upper surface of a gate insulating film and the side edges
of the first conductive layer is smaller than an angle between an upper
surface of the second gate insulating film and side edges of the third
conductive layer. Id. at 38:1—17, id. at 41, 42.
Illustrative Claim
Independent claim 1 is illustrative, and reads as follows:
1. A semiconductor device comprising a CMOS circuit, the
CMOS circuit comprising:
(a) a first transistor comprising:
a first semiconductor layer on an insulating layer;
a first gate insulating film over the first semiconductor layer;
and
a first gate electrode over the first semiconductor layer with the
first gate insulating film interposed therebetween, the first gate
electrode comprising a first conductive layer and a second conductive
layer,
wherein the first transistor is an n-channel transistor, and
wherein the first conductive layer extends beyond side edges of
the second onductive layer, and
(b) a second transistor comprising:
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Application 13/298,469
a second semiconductor layer on the insulating layer;
a second gate insulating film over the second semiconductor
layer, and
a second gate electrode over the second semiconductor layer
with the second gate insulating film interposed therebetween, the
second gate electrode comprising a third conductive layer and a fourth
conductive layer,
wherein the second transistor is a p-channel transistor, and
wherein an angle between an upper surface of the first gate
insulating film and side edges of the first conductive layer is smaller
than an angle between an upper surface of the second gate insulating
film and side edges of the third conductive layer.
Prior Art Relied Upon
Satoh
Chien
Zhang
Klingbeil, Jr.
Kobayashi et al.
US 5,177,571
US 5,413,945
US 5,508,209
US 5,882,961
US 6,146,930
Jan. 5, 1993
May 9, 1995
Apr. 16, 1996
Mar. 16, 1999
Nov. 14, 2000
Rejections on Appeal
Claims 1, 3—6, and 8—11 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Chien, Satoh, and Zhang. Final
Act. 2—8.
Claims 2 and 7 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Chien, Satoh, Zhang, and Kobayashi.
Final Act. 8—9.
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Application 13/298,469
Claims 12, and 14—16 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Chien, Satoh, Zhang, and
Klingbell. Final Act. 9—13.
Claims 13 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Chien, Satoh, Zhang, Klingbell and
Kobayashi. Final Act. 13—14.
ANALYSIS
We consider Appellant’s arguments seriatim, as they are presented in
the Appeal Brief, pages 5—12, in the Reply Brief pages 1—5.2 Except as
otherwise indicated hereinbelow, we adopt as our own the findings and
reasons set forth in the Final Action, and the Examiner’s Answer in response
to Appellant’s Appeal Brief. Final Act. 2—14, Ans. 2—6. However, we
highlight and address specific arguments and findings for emphasis as
follows.
Appellant argues that the Examiner has not provided sufficient reason
to combine Chien and Satoh to render claim 1 unpatentable. App. Br. 6—7,
Reply Br. 1. In particular, Appellant argues that the proposed modification
of Chien with Satoh would render Chien unsatisfactory for its intended
2 Rather than reiterate the arguments of Appellant and the Examiner, we
refer to the Appeal Brief (filed January 28, 2015), the Reply Brief (filed
September 21, 2015), and the Answer (mailed July 20, 2015) for their
respective details. We have considered in this Decision only those
arguments Appellant actually raised in the Briefs. Any other arguments
Appellant could have made but chose not to make in the Briefs are deemed
to be waived. See 37 C.F.R. § 41.37(c)(l)(iv) (2013).
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Application 13/298,469
purpose, and would thereby change the principle of operation of Chien.
App. Br. 8. According to Appellant, because the object of Chien’s
invention is for making submicron NMOS devices (which do not suffer from
the hot carrier effect) and PMOS devices with improved short channel
effect/performance, whereas Satoh is concerned with a lightly doped drain
metal oxide semiconductor (LDDMOS), one of ordinary skill in the art
would not use the extended lower gate electrode in Satoh to replace the gate
of the n-transistor in Chien. App. Br. 7—8, Reply Br. 1—2. More particularly,
Appellant argues that the Examiner has not provided a reason for replacing
Chien’s N-channel transistor with Satoh’s teaching of a tapered lower gate
electrode to thereby miniaturize only one side (NMOS) of Chien’s CMOS
device while the other side (PMOS) of the device is unaltered. App. Br. 10-
11, Reply Br. 3—5. Accordingly, Appellant submits that the miniaturization
of only one side of the transistor would not significantly reduce the overall
thickness of the semiconductor device. Id. These arguments are not
persuasive.
At the outset, we echo the Examiner’s finding that the intended
function of both Chien and Satoh is to make the NMOS device immune to
the hot electron effect. Ans. 2 (citing Chien 2:22—25, Satoh 1:34—50). In
particular, Chien indicates that using a lightly doped drain (LDD) is a known
method for redressing the hot carrier problem. Chien 1:34-40. Likewise,
Satoh discloses LDD method as a way to tackle the hot electron problem.
Satoh 1: 28-42. Further, as correctly noted by the Examiner, the cited
portions of Chien are relied upon for their teaching of reducing the hot
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carrier problem in the NMOS device only. Id. at 3 (citing Chien 2:22—27).
Although Chien also discusses improving the performance of the PMOS
device, such improvement is discussed within the context of reducing the
short channel effect in the PMOS device, which is not the focus of the
proposed combination. Id. Accordingly, we agree with the Examiner’s
finding that Chien’s disclosure of manufacturing an LDDMOS transistor as
a way to redress the hot carrier problem in the NMOS device (Chien 1:38—
41) is a sufficient reason for the proposed combination of Chien with Satoh.
Id. at 3^4. Furthermore, we agree with the Examiner that because only the
NMOS device needs improvement, the replacement in Chien should be
limited to the NMOS, and not extended to the PMOS device. Id. We thus
find on this record that the Examiner has provided sufficient rationale for the
proposed combination of Chien and Satoh. We likewise agree with the
Examiner that the proposed combination is proper, and would not render
Chien unsatisfactory for its intended purpose. Accordingly, we are not
persuaded that the Examiner erred in finding that the combination of Chien,
Satoh, and Zhang renders claim 1 unpatentable.
We also sustain the Examiner’s rejection of the remaining claims,
which are not argued separately. Therefore, the rejections of these claims
are sustained for the foregoing reasons. See 37 C.F.R. § 1.37(c)(l)(iv).
DECISION
We affirm the Examiner’s obviousness rejections of claim 1—16 under
35U.S.C. § 103(a).
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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