12189319 (P.T.A.B. Jun. 9, 2016)

Ex Parte Yamashiro et al

Patent Trial and Appeal BoardJun 9, 2016

12189319 (P.T.A.B. Jun. 9, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 12/189,319 08/1112008 37013 7590 06/13/2016 Rossi, Kimms & McDowell LLP 20609 Gordon Park Square Suite 150 Ashburn, VA 20147 FIRST NAMED INVENTOR Keisuke YAMASHIRO UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. FUJI-0502 6791 EXAMINER 0 TOOLE, COLLEEN J ART UNIT PAPER NUMBER 2842 NOTIFICATION DATE DELIVERY MODE 06/13/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): mail@rkmllp.com EOfficeAction@rkmllp.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte KEISUKE YAMASHIRO and HIROMU TAKUBO Appeal2015-000607 Application 12/189,319 Technology Center 2800 Before BRUCE R. WINSOR, LINZY T. McCARTNEY, and NATHAN A. ENGELS, Administrative Patent Judges. ENGELS, Administrative Patent Judge. DECISION ON APPEAL Appellants 1 appeal under 35 U.S.C. Â§ 134(a) from the Final Rejection of claims 1, 2, 9, 10, 14, 20, and 23. Claims 3-8, 11-13, 15-19, 21, and 22 are canceled. App. Br. 16. We have jurisdiction under 35 U.S.C. Â§ 6(b). We reverse. STATEMENT OF THE CASE The Claims Claim 1 of Appellants' invention is independent and illustrative of the subject matter on appeal: 1 According to Appellants, the real party in interest is Fuji Electric Co., Ltd. App. Br. 2. Appeal2015-000607 Application 12/189,319 1. A gate driving circuit for controllably turning ON and OFF a semiconductor device having a gate and an emitter, the gate driving circuit comprising: a first series circuit having a first MOSFET and a second MOSFET connected in series with the first MOSFET; a second series circuit having a capacitor and a third MOSFET connected in series with the capacitor; a fourth MOSFET connected in parallel with the second MOSFET, wherein the first series circuit configured to be connected to a positive side and a negative side of a DC power supply, wherein the second series circuit is connected in parallel with the second MOSFET, wherein the gate of the semiconductor device is connected to a negative potential side of the first MOSFET and a positive potential side of each of the second, third, and fourth MOSFETs, and the emitter of the semiconductor device is connected to a negative potential side of each of the second, third, and fourth MOSFETs, wherein a common ON/OFF activating signal is concurrently input to both the second and third MOSFETs to tum ON/OFF both the second and third MOSFETs, wherein turning OFF the first MOSFET and turning ON the second and third MOSFETs tum OFF the semiconductor device, wherein the fourth MOSFET is turned ON as the semiconductor device is brought into an OFF state to keep the semiconductor device in the OFF state, wherein the third MOSFET is always turned ON, from an OFF-state, before turning ON the second MOSFET to draw charges accumulated between the gate and the emitter of the semiconductor device into the capacitor, each time the semiconductor device is switched OFF, wherein at least one of the gate resistance or the ON-state resistance of the second MOSFET is higher than the 2 Appeal2015-000607 Application 12/189,319 corresponding gate resistance or the ON-state resistance of the third MOSFET to tum ON the third MOSFET before turning ON the second MOSFET, wherein the second series circuit prevents tum-OFF noise and tum-OFF loss of the semiconductor device, and wherein the second series circuit increases a change rate dv/dt of a voltage Vee when Vee< Vdc, Vdc being a DC voltage, while the change rate dv/dt of the voltage Vee remains substantially the same when V ce > V de, relative to when the gate driving circuit omits the second series circuit. App. Br. 15. The Examiners Rejections Claims 1, 2, 9, 10, 14, 20, and 23 stand rejected under 35 U.S.C. Â§ 103(a) as unpatentable over Appellants' admitted prior art ("AAP A"), Hoshi et al. (US 6,271, 708 B 1; issued Aug. 7, 2001 ), Ishii (US 5,977,814; issued Nov. 2, 1999), and Iadanza et al. (US 5,815,009; issued Sept. 29, 2008). See Final Act. 2-7. ANALYSIS Appellants contend the Examiner erred because the combination of AAP A, Hoshi, Ishii, and Iadanza does not teach or suggest "wherein turning OFF the first MOSFET and turning ON the second and third MOSFETs tum OFF the semiconductor device." See App. Br 5-7; Reply Br. 2; see also Final Act. 4 (citing Hoshi col. 4, 11. 55---62). Relevant to this limitation, the Examiner finds ( 1) AAP A teaches a first series circuit having a first MOSFET and a second MOSFET (see Final Act. 3 (citing Appellants' Fig. 5, items 21, 22)); and (2) Ishii teaches a second series circuit having a capacitor and a third MOSFET (see Final Act. 4 (citing Ishii Fig. 1, item 13, 3 Appeal2015-000607 Application 12/189,319 14) ). The Examiner further finds Hoshi teaches ( 1) a first series circuit having a first switch SWan and a second switch SWofJ2; and (2) a second series circuit having a third switch SWaffÂ· See Final Act. 3 (citing Hoshi Fig. 6). In view of the foregoing, the Examiner finds Hoshi teaches or suggests the disputed limitation by closing SWaJJWhen an OFF signal is applied and closing SWafJ2 after a time Tl that is set by the time-delay circuit TD. See Ans. 3 (citing Hoshi Fig. 6; col. 4, 11. 55---62). The Examiner explains that "closing SWoff2 completes the essential part of the tum-off operation." Ans. 3; Hoshi col. 6, 11. 13-16. Appellants argue Hoshi does not teach or suggest the disputed limitation because SWafJ2 is not for turning off Hoshi' s semiconductor S 1. See App. Br. 5. Appellants explain that turning on SWafJ2 does not tum off S 1 because SW afJ2 is turned on after S 1 has already been turned off. See App. Br. 5. According to Appellants, "the purpose of turning on Hoshi's second switch SWoff2, at a delayed timing in relation to the first switch SWoff, is to ensure that the IGBT stays turned OFF after it is turned OFF, and not to tum OFF the IGBT SI." App. Br. 7. Having reviewed Appellants' arguments in light of the Examiner's findings, we agree with Appellants that the Examiner erred. As an initial matter, we agree with the Examiner that Hoshi's closing of SWaJJWhen an OFF signal is applied, in combination with Ishii's third MOSFET, suggests "wherein ... turning ON the ... third MOSFET[] tum[s] OFF the semiconductor device." See Ans. 3; Final Act. 3--4; Hoshi col. 4, 11. 55---62; Ishii Fig. 1, item 14. But, as Appellants argue, closing SWafJ2 does not tum off Hoshi' s semiconductor S 1 because SW afJ2 is closed after S 1 has already been turned off. See App. Br. 5; Reply Br. 2. Indeed, Hoshi "closes SWafJ2 4 Appeal2015-000607 Application 12/189,319 after time Tl ... for example after a time Tl that is a little longer than the completion time of the tum-off operation, for instance after 10 Âµs." Hoshi col. 4, 11. 58---61 (emphasis added); see Reply Br. 2. Therefore, we find the Examiner erred because Hos hi' s closing of SW affe does not teach or suggest "wherein ... turning ON the second ... MOSFET[] tum[s] OFF the semiconductor device." Similarly, we disagree with the Examiner that Hoshi' s closing of SW op completes the essential part of the tum-off operation. See Ans. 3 (citing Hoshi col. 6, 11. 13-16). To the contrary, the cited passage of Hoshi merely indicates that SW affe is closed when the gate voltage V GE becomes the set voltage Vref, at which time the essential part of the tum-off operation has already been completed. See Hoshi col. 6, 11. 13- 16; Reply Br. 2. For these reasons, we agree with Appellants that the Examiner erred in finding that Hoshi teaches or suggests "wherein turning OFF the first MOSFET and turning ON the second and third MOSFETs tum OFF the semiconductor device" as recited in claim 1. The Examiner also has not shown that AAP A, Ishii, or Iadanza cures this deficiency of Hoshi. Accordingly, we reverse the Examiner's rejection of claim 1, as well as independent claim 23 and dependent claims 2, 9, 10, 14, and 20, which include the same deficiency. DECISION The decision of the Examiner to reject claims 1, 2, 9, 10, 14, 20, and 23 is reversed. REVERSED 5