Ex Parte Yamamoto et al

Patent Trial and Appeal Board

Mar 13, 2018

14066742 (P.T.A.B. Mar. 13, 2018)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/066,742 10/30/2013 Tetsuro Yamamoto 880125-5618-US01 7491
134795 7590 03/15/2018
MICHAEL BEST & FRIEDRICH LLP (DC)
100 E WISCONSIN AVENUE
Suite 3300
MILWAUKEE, WI 53202
EXAMINER
MARINELLI, PATRICK
ART UNIT PAPER NUMBER
2694
NOTIFICATION DATE DELIVERY MODE
03/15/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
DCipdocket @ michaelbest. com
sbj ames @michaelbest.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte TETSURO YAMAMOTO and KATSUHIDE UCHINO
Appeal 2016-007449
Application 14/066,742
Technology Center 2600
Before JUSTIN BUSCH, JOHN P. PINKERTON, and
JAMES W. DEJMEK, Administrative Patent Judges.
PINKERTON, Administrative Patent Judge
DECISION ON APPEAL
Appellants1 appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 40-55.2 Claims 1—39 are canceled. We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm.
1 Appellants identify JOLED Inc. as the real party in interest. App. Br. 3.
2 An oral hearing was held in this case on March 5, 2018.
Appeal 2016-007449
Application 14/066,742
STATEMENT OF THE CASE
Introduction
Appellants generally describe the disclosed and claimed invention as
follows:
Disclosed herein is a display device that allows a vertical
scanning line to be shared between a plurality of rows without
increasing the number of control lines or control signals, the
display device including pixel circuits; vertical scanning lines;
and horizontal scanning lines.
Abstract.3
Claims 40, 41, and 43 are representative and reproduced below (with
the disputed limitations emphasized in italics and labelled in brackets):
40. A display device comprising:
scanning line wiring that directly electrically connects a
gate terminal of a first switching transistor to a gate terminal
of a second switching transistor, the scanning line wiring
directly electrically connects a gate terminal of a third
switching transistor to a gate terminal of a fourth switching
transistor [“the scanning line limitation”];
a first signal line directly electrically connected to a
source terminal of the first switching transistor and to a source
terminal of the third switching transistor [“the first signal line
limitation”], the gate terminal of the third switching transistor is
directly electrically connected to the gate terminal of the first
switching transistor; and
a second signal line directly electrically connected to a
source terminal of the second switching transistor and to a
3 Our Decision refers to the Final Action mailed Oct. 23, 2015 (“Final
Act.”); Appellants’ Appeal Brief filed Jan. 21, 2016 (“App. Br.”) and Reply
Brief filed July 27, 2016 (“Reply Br.”); the Examiner’s Answer mailed
June 7, 2016 (“Ans.”); and the original Specification filed Oct. 30, 2013
(“Spec.”).
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Application 14/066,742
source terminal of the fourth switching transistor, the gate
terminal of the fourth switching transistor is directly electrically
connected to the gate terminal of the second switching
transistor.
41. The display device according to claim 40, further
comprising:
a first sampling transistor that makes and breaks an
electrical connection between a drain terminal of the first
switching transistor and a gate terminal of a first driving
transistor, a second sampling transistor makes and breaks an
electrical connection between a drain terminal of the second
switching transistor and a gate terminal of a second driving
transistor.
43. The display device according to claim 41, wherein the
first switching transistor is configured to make and break an
electrical connection between the first signal line and a source
terminal of the first sampling transistor.
App. Br. 20-21 (Claims App’x).
Rejections on Appeal
Claim 40 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Itoh et al. (US 5,844,535; issued Dec. 1, 1998) (“Itoh”).
Claims 41—55 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Itoh and Yamazaki et al. (US 2004/0245529 Al;
published Dec. 9, 2004) (“Yamazaki”).
ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments in the Briefs and are not persuaded the Examiner erred. Unless
otherwise noted, we adopt as our own the findings and reasons set forth by
the Examiner in the Office Action from which this appeal is taken (Final
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Act. 4—15) and in the Examiner’s Answer (Ans. 2—6), and we concur with
the conclusions reached by the Examiner. For emphasis, we consider and
highlight specific arguments as presented in the Briefs.
Rejection of Claim 40 under § 103(a)
In the Final Action, the Examiner finds Itoh teaches the scanning line
limitation of claim 41. Final Act. 5. In particular, the Examiner finds pixel
block address line 222 connects directly to (1) the gate terminal of switching
transistors SW2 of the first and second pixels in row N of Figure 19B (that
correspond to the claimed gate terminal of the first and second switching
transistors) and (2) the gate terminal of switching transistors SW2 of the first
and second pixels in row N+l of Figure 19B (which correspond to the
claimed gate terminal of the third and fourth switching transistors). Id.
(citing Itoh, Fig. 19B and col. 14,1. 25—col. 15,1. 37).
The Examiner also finds, although Itoh does not expressly teach the
first signal line limitation, it would have been obvious to a person or
ordinary skill in the art to rearrange transistor SW2 to be between signal line
220 and transistor SW1 for each pixel. Final Act. 6. Thus, based on this
rearrangement of transistors, the Examiner finds Itoh teaches a first signal
line 220 is connected to a source terminal of transistor SW2 in the first pixel
in row N (the claimed first switching transistor) and to a source terminal of
transistor SW2 in the first pixel in row N+l (the claimed third switching
transistor). Id. In the Answer, the Examiner reaffirms these findings with
respect to the scanning line and first signal line limitations. Ans. 3.
In the Appeal Brief, Appellants argue Itoh fails to disclose the
scanning line limitation. App. Br. 8—9. Appellants also provide a
comparison of a portion of Figure 8 A of the Specification with a portion of
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Application 14/066,742
Figure 19B of Itoh (with annotations added in the manner provided in the
Final Action). Id. at 9.
Appellants also argue Itoh fails to teach the first signal line limitation
because switching device SW1 is an intervening component between signal
line 220 and the second switching device SW2. Id. at 10. According to
Appellants, Figure 19B of Itoh fails to show signal line 220 “being directly
electrically connected to the second switching device (SW2) when the first
switching device (SW1) is energized.” Id. Appellants also argue, because
signal VA1 occurs at a time different that signal VA2, it would not have
been possible for signal line 220 to be directly connected to both the source
terminal of the first pixel switching device SW2 and the source terminal of
the third pixel switching device SW2. Id. at 11.
We are not persuaded of Examiner error. Regarding the scanning line
limitation. Appellants’ statement that Itoh fails to teach the disputed
limitation amounts to no more than reciting the claim language and alleging
the cited prior art is deficient, which does not constitute a separate argument
for patentability of the claim. See 37 C.F.R. § 41.37(c)(l)(iv)(2015) (“A
statement which merely points out what a claim recites will not be
considered an argument for separate patentability of the claim”); see also In
re Lovin, 652 F.3d 1349, 1357 (Fed. Cir. 2011) (“[W]e hold that the Board
reasonably interpreted Rule 41.37 to require more substantive arguments in
an appeal brief than a mere recitation of the claim elements and a naked
assertion that the corresponding elements were not found in the prior art”).
In addition, Appellants’ statement, and comparison chart, are conclusory and
fail to provide evidence or reasoning why Itoh allegedly does not teach or
suggest the scanning line limitation. Mere attorney arguments and
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Application 14/066,742
conclusory statements that are unsupported by factual evidence are entitled
to little probative value. In re Geisler, 116 F.3d 1465, 1470 (Fed. Cir.
1997); In re De Blauwe, 736 F.2d 699, 705 (Fed. Cir. 1984).
Regarding the first signal line limitation. Appellants’ arguments are
not persuasive of Examiner error because they are not responsive to the
Examiner’s proposed modification of Figure 19B of Itoh. That is,
Appellants’ arguments that signal line 220 is not directly connected to
transistor SW2, and that the timing of signals VA1 and VA2 shown in
Figure 21A, which is based on Figure 19B, would not be possible, fail to
consider or address the Examiner’s modification in which transistor SW2 of
each pixel is rearranged to be between signal line 220 and transistor SW1.
See Final Act. 6; Ans. 3. Instead, Appellants’ arguments are based on Figure
19B without the Examiner’s rearrangement of transistors SW1 and SW2.
Below is a portion of Figure 19B illustrating, inter alia, four pixels of a
display and the connections of transistors S W1 and S W2 within each pixel
as shown in Itoh.
We have modified the portion of Fig 19B shown above to reflect the
Examiner’s proposed modification. Thus, in the configuration shown below,
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Application 14/066,742
the locations of transistors SW1 and S W2 are switched so that transistor
SW2 is moved to be between the signal line 220 and transistor SW 1 for each
pixel.
Considering this modification of Figure 19B as proposed by the
Examiner, we agree with the Examiner’s finding that Itoh, as modified,
teaches first signal line 220 is directly connected to the source terminal of
the first switching transistor SW2 in the first pixel in row N and to the
source terminal of the third switching transistor SW2 in the first pixel in row
N+l.
In the Reply Brief, Appellants make numerous arguments for the first
time that the Examiner’s proposed modification of Itoh is improper,
including arguments that (1) the modification would render Itoh
unsatisfactory for its intended purpose, (2) the modification would have
required a substantial reconstruction and redesign of the elements of Figure
19B, as well as a change in the basic principles of Itoh, (3) the
rearrangement of parts is not by itself sufficient to show obviousness,
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(4) there must be some articulated reasoning with rational underpinning to
support the conclusion of obviousness, and (5) the Examiner used
impermissible hindsight to show obviousness. See Reply Br. 8—12. Because
Appellants raised these arguments for the first time in the Reply Brief not in
response to a shift in the Examiner’s position and without otherwise showing
good cause, the arguments are waived. See 37 C.F.R.§ 41.41(b)(2); see also
Ex parte Borden, 93 USPQ2d 1473, 1474 (BPAI 2010) (informative)
(“[T]he reply brief [is not] an opportunity to make arguments that could
have been made in the principal brief on appeal to rebut the Examiner’s
rejections, but were not.”).
For these reasons, we agree with the Examiner’s findings that (1) Itoh
teaches or suggests the scanning line limitation and (2) Itoh modified by
switching the locations of transistors S W1 and S W2 in each of the pixels
teaches or suggests the first signal line limitation of claim 40. Thus, we
sustain the Examiner’s rejection of claim 40 under § 103(a).
Rejection of Claims 41—55 under § 103(a)
Claims 41, 42, and 53
Claim 41 recites “a first sampling transistor that makes and breaks an
electrical connection between a drain terminal of the first switching
transistor and a gate terminal of a first driving transistor.” In the Final
Action, the Examiner finds this limitation is taught by the combination of
Yamazaki and the modification of Figure 19B of Itoh. Final Act. 10. In
particular, the Examiner finds Yamazaki teaches a pixel comprising a
switching transistor 901, a driving transistor 902, and a light emitting
element 903. Final Act. 8 (citing Yamazaki Fig. 5,128). The Examiner
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Application 14/066,742
also concludes it would have been obvious to a person of ordinary skill in
the art, at the time the invention was made,
to modify, the teachings of Itoh to further include the teachings
of Yamazaki in order to provide replacing the liquid crystal
capacitor and the storage capacitor with the driving TFT and
light emitting element of Yamazaki. The motivation to combine
these arts is because Yamazaki teaches that self-light emitting
elements can be used to replace a liquid crystal element for a
pixel (Yamazaki: [0002];).
Id. at 9—10. Thus, the Examiner finds the combination of Itoh and Yamazaki
teaches the disputed limitation of claim 42— “a transistor TFT SW1 (first
sampling transistor) is between the transistor TFT SW2 (first switching
transistor) and the gate of driving transistor (first driving transistor) to make
and break an electrical connection between the two.” Id. at 10 (emphasis
omitted) (citing Itoh Fig. 19B, col. 14,11.25—col. 15,11. 37; Yamazaki,
Fig.5,T|2, 28—29).4
Appellants argue no sampling transistor similar to sampling transistor
625 in Figure 8A of the Specification can be found in Itoh. App. Br. 13.
Appellants also argue “no intervening sampling transistor exists anywhere
between the switching device (SW2) in Figure 19B of Itoh and “a gate
electrode of a driving transistor. Id. at 14. According to Appellants, there
is no teaching in Itoh of transistor SW1 being configured in Figure 19B to
make and break an electrical connection between a drain terminal of
transistor SW2 and “a gate terminal of a driving transistor, especially when
no driving transistor exists anywhere within Itoh.’ '' Reply Br. 15—16.
4 For similar reasons, the Examiner finds the combination of Itoh and
Yamazaki teaches the “second sampling transistor” limitation of claim 41.
See Final Act. 10.
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Appellants also argue “no sampling transistor exists in Yamazaki.” Reply
Br. 15; App. Br. 15. Appellants further argue the Examiner’s combination
of Itoh and Yamazaki is conclusory, “unsupported by a proper factual
showing,” and based on hindsight. App. Br. 15.
We are not persuaded by Appellants’ arguments. First, contrary to
Appellants’ argument that Itoh fails to teach a sampling transistor similar to
sampling transistor 625 in Figure 8 A of the Specification, we agree with the
Examiner’s finding that “TFT transistor SW1 would correspond to the
Appellants sampling transistor 625, and thus, TFT transistor SW2 would be
configured to make and break the electrical connection between the signal
line 220 and the TFT transistor SW1.” Ans. 5.
Second, Appellants’ attacks on Itoh and Yamazaki individually are
not persuasive because the arguments fail to address the Examiner’s
rejection. “Non-obviousness cannot be established by attacking references
individually where the rejection is based upon the teachings of a
combination of references.” In re Merck & Co., 800 F.2d 1091, 1097 (Fed.
Cir. 1986). For example, although Appellants attack Itoh for failing to teach
a driving transistor, the Examiner relies on Yamazaki to teach the driving
transistor 902. Ans. 4. And, although Appellants attack Yamazaki for not
teaching a sampling transistor, we agree with the Examiner’s finding, as
stated supra, that transistor SW1 is the sampling transistor in the Examiner’s
modification of Figure 19B of Itoh. Id. at 5.
Third, contrary to Appellants’ argument that the Examiner’s
obviousness finding based on the combination of Itoh and Yamazaki is
conclusory and unsupported by a proper factual showing (see App. Br. 15),
the Examiner expressly states the rationale for the combination:
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the teachings of Yamazaki describe that “In recent years, a light
emitting device using a light emitting element represented by an
electroluminescent (EL) element and the like has been developed
in substitution for a liquid crystal display (LCD) comprising a
pixel using a liquid crystal element as a light emitting element”
(Yamazaki: [0002]). This would have been sufficient evidence
to suggest one of ordinary skill in the art to have substituted the
liquid crystal unit Clc and the capacitor Cs with the driving
transitor[] 902 and light emitting element 903 of Yamazaki. This
would result in each pixel consisting of a first switching device
SW1 and a second switching device SW2, as described in Itoh,
and also comprising of the driving transistor 902 and the light
emitting element 903, as described in Yamazaki.
Ans. 4.
We agree with the Examiner’s stated rationale for combining the
references and find it constitutes articulated reasoning with some rational
underpinning in accordance with KSR Int’l Co. v. Teleflex Inc., 550 U.S.
398,418 (2007).
fourth, we are not persuaded by Appellants’ argument the Examiner’s
rejection is based on improper hindsight because the rejection “takes into
account only knowledge which was within the level of ordinary skill at the
time the claimed invention was made, and does not include knowledge
gleaned only from [the] applicant’s disclosure.” In re McLaughlin, 443 F.2d
1392, 113-14 (CCPA 1971).
Accordingly, for these reasons, we sustain the Examiner’s rejection of
claim 41, and dependent claims 42 and 53, which are not separately argued,
under § 103(a).
Claims 43—52, 54, and 55
Appellants incorporate by reference the arguments made with respect
to claim 41 in regard to claims 43—52, 54, and 55. App. Br. 17—19. In
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particular, Appellants argue Itoh does not teach a sampling transistor similar
to sampling transistor 625 in Figure 8 A of the Specification and no
intervening sampling transistor exists in Yamazaki and, therefore, “a
sampling transistor is absent from within the combination of Itoh and
Yamazaki.” App. Br. 17—19; Reply Br. 16—19. For the reasons stated supra
regarding claim 41, we are not persuaded by these arguments. Accordingly,
we sustain the Examiner’s rejection of claims 43—52, 54, and 55 under
§ 103(a).
DECISION
We affirm the Examiner’s rejection of claims 40—55 under 35 U.S.C.
§ 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv).
AFFIRMED
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